Import uapi/i915_drm.h from v4.10-rc5-950-g152d5750dda9

To sync with "drm/i915: Support explicit fencing for execbuf"

1 files changed, 266 insertions, 10 deletions

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index eb611a7a..5ebe0462 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -29,6 +29,10 @@
 
 #include "drm.h"
 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
  */
@@ -58,6 +62,30 @@
 #define I915_ERROR_UEVENT               "ERROR"
 #define I915_RESET_UEVENT               "RESET"
 
+/*
+ * MOCS indexes used for GPU surfaces, defining the cacheability of the
+ * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
+ */
+enum i915_mocs_table_index {
+        /*
+         * Not cached anywhere, coherency between CPU and GPU accesses is
+         * guaranteed.
+         */
+        I915_MOCS_UNCACHED,
+        /*
+         * Cacheability and coherency controlled by the kernel automatically
+         * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
+         * usage of the surface (used for display scanout or not).
+         */
+        I915_MOCS_PTE,
+        /*
+         * Cached in all GPU caches available on the platform.
+         * Coherency between CPU and GPU accesses to the surface is not
+         * guaranteed without extra synchronization.
+         */
+        I915_MOCS_CACHED,
+};
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
@@ -218,6 +246,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_OVERLAY_PUT_IMAGE      0x27
 #define DRM_I915_OVERLAY_ATTRS  0x28
 #define DRM_I915_GEM_EXECBUFFER2        0x29
+#define DRM_I915_GEM_EXECBUFFER2_WR     DRM_I915_GEM_EXECBUFFER2
 #define DRM_I915_GET_SPRITE_COLORKEY    0x2a
 #define DRM_I915_SET_SPRITE_COLORKEY    0x2b
 #define DRM_I915_GEM_WAIT       0x2c
@@ -230,6 +259,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GEM_USERPTR            0x33
 #define DRM_I915_GEM_CONTEXT_GETPARAM   0x34
 #define DRM_I915_GEM_CONTEXT_SETPARAM   0x35
+#define DRM_I915_PERF_OPEN              0x36
 
 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -251,6 +281,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 #define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
@@ -283,6 +314,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_USERPTR                      DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM     DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM     DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
+#define DRM_IOCTL_I915_PERF_OPEN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -357,8 +389,28 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_GPU_RESET         35
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
 #define I915_PARAM_HAS_EXEC_SOFTPIN      37
-#define I915_PARAM_HAS_POOLED_EU         38
-#define I915_PARAM_MIN_EU_IN_POOL        39
+#define I915_PARAM_HAS_POOLED_EU         38
+#define I915_PARAM_MIN_EU_IN_POOL        39
+#define I915_PARAM_MMAP_GTT_VERSION      40
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
+ * priorities and the driver will attempt to execute batches in priority order.
+ */
+#define I915_PARAM_HAS_SCHEDULER         41
+#define I915_PARAM_HUC_STATUS            42
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
+ * synchronisation with implicit fencing on individual objects.
+ * See EXEC_OBJECT_ASYNC.
+ */
+#define I915_PARAM_HAS_EXEC_ASYNC        43
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
+ * both being able to pass in a sync_file fd to wait upon before executing,
+ * and being able to return a new sync_file fd that is signaled when the
+ * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
+ */
+#define I915_PARAM_HAS_EXEC_FENCE        44
 
 typedef struct drm_i915_getparam {
         __s32 param;
@@ -694,15 +746,41 @@ struct drm_i915_gem_exec_object2 {
          */
         __u64 offset;
 
-#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
-#define EXEC_OBJECT_NEEDS_GTT   (1<<1)
-#define EXEC_OBJECT_WRITE       (1<<2)
+#define EXEC_OBJECT_NEEDS_FENCE          (1<<0)
+#define EXEC_OBJECT_NEEDS_GTT            (1<<1)
+#define EXEC_OBJECT_WRITE                (1<<2)
 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
-#define EXEC_OBJECT_PINNED      (1<<4)
-#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
+#define EXEC_OBJECT_PINNED               (1<<4)
+#define EXEC_OBJECT_PAD_TO_SIZE          (1<<5)
+/* The kernel implicitly tracks GPU activity on all GEM objects, and
+ * synchronises operations with outstanding rendering. This includes
+ * rendering on other devices if exported via dma-buf. However, sometimes
+ * this tracking is too coarse and the user knows better. For example,
+ * if the object is split into non-overlapping ranges shared between different
+ * clients or engines (i.e. suballocating objects), the implicit tracking
+ * by kernel assumes that each operation affects the whole object rather
+ * than an individual range, causing needless synchronisation between clients.
+ * The kernel will also forgo any CPU cache flushes prior to rendering from
+ * the object as the client is expected to be also handling such domain
+ * tracking.
+ *
+ * The kernel maintains the implicit tracking in order to manage resources
+ * used by the GPU - this flag only disables the synchronisation prior to
+ * rendering with this object in this execbuf.
+ *
+ * Opting out of implicit synhronisation requires the user to do its own
+ * explicit tracking to avoid rendering corruption. See, for example,
+ * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
+ */
+#define EXEC_OBJECT_ASYNC               (1<<6)
+/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
+#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1)
         __u64 flags;
 
-        __u64 rsvd1;
+        union {
+                __u64 rsvd1;
+                __u64 pad_to_size;
+        };
         __u64 rsvd2;
 };
 
@@ -786,7 +864,32 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_RESOURCE_STREAMER     (1<<15)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
+/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_IN              (1<<16)
+
+/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
+ * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
+ * to the caller, and it should be close() after use. (The fd is a regular
+ * file descriptor and will be cleaned up on process termination. It holds
+ * a reference to the request, but nothing else.)
+ *
+ * The sync_file fd can be combined with other sync_file and passed either
+ * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
+ * will only occur after this request completes), or to other devices.
+ *
+ * Using I915_EXEC_FENCE_OUT requires use of
+ * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
+ * back to userspace. Failure to do so will cause the out-fence to always
+ * be reported as zero, and the real fence fd to be leaked.
+ */
+#define I915_EXEC_FENCE_OUT             (1<<17)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
 
 #define I915_EXEC_CONTEXT_ID_MASK       (0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
@@ -822,7 +925,16 @@ struct drm_i915_gem_busy {
          * having flushed any pending activity), and a non-zero return that
          * the object is still in-flight on the GPU. (The GPU has not yet
          * signaled completion for all pending requests that reference the
-         * object.)
+         * object.) An object is guaranteed to become idle eventually (so
+         * long as no new GPU commands are executed upon it). Due to the
+         * asynchronous nature of the hardware, an object reported
+         * as busy may become idle before the ioctl is completed.
+         *
+         * Furthermore, if the object is busy, which engine is busy is only
+         * provided as a guide. There are race conditions which prevent the
+         * report of which engines are busy from being always accurate.
+         * However, the converse is not true. If the object is idle, the
+         * result of the ioctl, that all engines are idle, is accurate.
          *
          * The returned dword is split into two fields to indicate both
          * the engines on which the object is being read, and the
@@ -845,6 +957,11 @@ struct drm_i915_gem_busy {
          * execution engines, e.g. multiple media engines, which are
          * mapped to the same identifier in the EXECBUFFER2 ioctl and
          * so are not separately reported for busyness.
+         *
+         * Caveat emptor:
+         * Only the boolean result of this query is reliable; that is whether
+         * the object is idle or busy. The report of which engines are busy
+         * should be only used as a heuristic.
          */
         __u32 busy;
 };
@@ -893,6 +1010,7 @@ struct drm_i915_gem_caching {
 #define I915_TILING_NONE        0
 #define I915_TILING_X           1
 #define I915_TILING_Y           2
+#define I915_TILING_LAST        I915_TILING_Y
 
 #define I915_BIT_6_SWIZZLE_NONE         0
 #define I915_BIT_6_SWIZZLE_9            1
@@ -1169,7 +1287,145 @@ struct drm_i915_gem_context_param {
 #define I915_CONTEXT_PARAM_BAN_PERIOD   0x1
 #define I915_CONTEXT_PARAM_NO_ZEROMAP   0x2
 #define I915_CONTEXT_PARAM_GTT_SIZE     0x3
+#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE     0x4
+#define I915_CONTEXT_PARAM_BANNABLE     0x5
         __u64 value;
 };
 
+enum drm_i915_oa_format {
+        I915_OA_FORMAT_A13 = 1,
+        I915_OA_FORMAT_A29,
+        I915_OA_FORMAT_A13_B8_C8,
+        I915_OA_FORMAT_B4_C8,
+        I915_OA_FORMAT_A45_B8_C8,
+        I915_OA_FORMAT_B4_C8_A16,
+        I915_OA_FORMAT_C4_B8,
+
+        I915_OA_FORMAT_MAX          /* non-ABI */
+};
+
+enum drm_i915_perf_property_id {
+        /**
+         * Open the stream for a specific context handle (as used with
+         * execbuffer2). A stream opened for a specific context this way
+         * won't typically require root privileges.
+         */
+        DRM_I915_PERF_PROP_CTX_HANDLE = 1,
+
+        /**
+         * A value of 1 requests the inclusion of raw OA unit reports as
+         * part of stream samples.
+         */
+        DRM_I915_PERF_PROP_SAMPLE_OA,
+
+        /**
+         * The value specifies which set of OA unit metrics should be
+         * be configured, defining the contents of any OA unit reports.
+         */
+        DRM_I915_PERF_PROP_OA_METRICS_SET,
+
+        /**
+         * The value specifies the size and layout of OA unit reports.
+         */
+        DRM_I915_PERF_PROP_OA_FORMAT,
+
+        /**
+         * Specifying this property implicitly requests periodic OA unit
+         * sampling and (at least on Haswell) the sampling frequency is derived
+         * from this exponent as follows:
+         *
+         *   80ns * 2^(period_exponent + 1)
+         */
+        DRM_I915_PERF_PROP_OA_EXPONENT,
+
+        DRM_I915_PERF_PROP_MAX /* non-ABI */
+};
+
+struct drm_i915_perf_open_param {
+        __u32 flags;
+#define I915_PERF_FLAG_FD_CLOEXEC       (1<<0)
+#define I915_PERF_FLAG_FD_NONBLOCK      (1<<1)
+#define I915_PERF_FLAG_DISABLED         (1<<2)
+
+        /** The number of u64 (id, value) pairs */
+        __u32 num_properties;
+
+        /**
+         * Pointer to array of u64 (id, value) pairs configuring the stream
+         * to open.
+         */
+        __u64 properties_ptr;
+};
+
+/**
+ * Enable data capture for a stream that was either opened in a disabled state
+ * via I915_PERF_FLAG_DISABLED or was later disabled via
+ * I915_PERF_IOCTL_DISABLE.
+ *
+ * It is intended to be cheaper to disable and enable a stream than it may be
+ * to close and re-open a stream with the same configuration.
+ *
+ * It's undefined whether any pending data for the stream will be lost.
+ */
+#define I915_PERF_IOCTL_ENABLE  _IO('i', 0x0)
+
+/**
+ * Disable data capture for a stream.
+ *
+ * It is an error to try and read a stream that is disabled.
+ */
+#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
+
+/**
+ * Common to all i915 perf records
+ */
+struct drm_i915_perf_record_header {
+        __u32 type;
+        __u16 pad;
+        __u16 size;
+};
+
+enum drm_i915_perf_record_type {
+
+        /**
+         * Samples are the work horse record type whose contents are extensible
+         * and defined when opening an i915 perf stream based on the given
+         * properties.
+         *
+         * Boolean properties following the naming convention
+         * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
+         * every sample.
+         *
+         * The order of these sample properties given by userspace has no
+         * affect on the ordering of data within a sample. The order is
+         * documented here.
+         *
+         * struct {
+         *     struct drm_i915_perf_record_header header;
+         *
+         *     { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
+         * };
+         */
+        DRM_I915_PERF_RECORD_SAMPLE = 1,
+
+        /*
+         * Indicates that one or more OA reports were not written by the
+         * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
+         * command collides with periodic sampling - which would be more likely
+         * at higher sampling frequencies.
+         */
+        DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
+
+        /**
+         * An error occurred that resulted in all pending OA reports being lost.
+         */
+        DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
+
+        DRM_I915_PERF_RECORD_MAX /* non-ABI */
+};
+
+#if defined(__cplusplus)
+}
+#endif
+
 #endif /* _I915_DRM_H_ */