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authorGrazvydas Ignotas2016-11-20 12:25:46 -0600
committerEmil Velikov2016-11-22 07:54:31 -0600
commit1924b6704aa34bb3dd044b8e1e29558c521c6902 (patch)
tree2b11d30381d9f89e4cd73c46b21ff9b17dc2c70e /radeon
parent1fc32f1cc5046fe76f2d5094fc576e097ea031e7 (diff)
downloadexternal-libdrm-1924b6704aa34bb3dd044b8e1e29558c521c6902.tar.gz
external-libdrm-1924b6704aa34bb3dd044b8e1e29558c521c6902.tar.xz
external-libdrm-1924b6704aa34bb3dd044b8e1e29558c521c6902.zip
libdrm: random typo fixes
Just some trivial boring typo fixes all over the tree. READMEs and comments only. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Diffstat (limited to 'radeon')
-rw-r--r--radeon/radeon_cs_gem.c10
-rw-r--r--radeon/radeon_surface.c2
2 files changed, 6 insertions, 6 deletions
diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
index 23f33af4..f3dccb6c 100644
--- a/radeon/radeon_cs_gem.c
+++ b/radeon/radeon_cs_gem.c
@@ -189,7 +189,7 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
189 /* check domains */ 189 /* check domains */
190 if ((read_domain && write_domain) || (!read_domain && !write_domain)) { 190 if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
191 /* in one CS a bo can only be in read or write domain but not 191 /* in one CS a bo can only be in read or write domain but not
192 * in read & write domain at the same sime 192 * in read & write domain at the same time
193 */ 193 */
194 return -EINVAL; 194 return -EINVAL;
195 } 195 }
@@ -242,7 +242,7 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
242 } 242 }
243 /* new relocation */ 243 /* new relocation */
244 if (csg->base.crelocs >= csg->nrelocs) { 244 if (csg->base.crelocs >= csg->nrelocs) {
245 /* allocate more memory (TODO: should use a slab allocatore maybe) */ 245 /* allocate more memory (TODO: should use a slab allocator maybe) */
246 uint32_t *tmp, size; 246 uint32_t *tmp, size;
247 size = ((csg->nrelocs + 1) * sizeof(struct radeon_bo*)); 247 size = ((csg->nrelocs + 1) * sizeof(struct radeon_bo*));
248 tmp = (uint32_t*)realloc(csg->relocs_bo, size); 248 tmp = (uint32_t*)realloc(csg->relocs_bo, size);
@@ -268,7 +268,7 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
268 reloc->flags = flags; 268 reloc->flags = flags;
269 csg->chunks[1].length_dw += RELOC_SIZE; 269 csg->chunks[1].length_dw += RELOC_SIZE;
270 radeon_bo_ref(bo); 270 radeon_bo_ref(bo);
271 /* bo might be referenced from another context so have to use atomic opertions */ 271 /* bo might be referenced from another context so have to use atomic operations */
272 atomic_add((atomic_t *)radeon_gem_get_reloc_in_cs(bo), cs->id); 272 atomic_add((atomic_t *)radeon_gem_get_reloc_in_cs(bo), cs->id);
273 cs->relocs_total_size += boi->size; 273 cs->relocs_total_size += boi->size;
274 radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000); 274 radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000);
@@ -449,7 +449,7 @@ static int cs_gem_emit(struct radeon_cs_int *cs)
449 &csg->cs, sizeof(struct drm_radeon_cs)); 449 &csg->cs, sizeof(struct drm_radeon_cs));
450 for (i = 0; i < csg->base.crelocs; i++) { 450 for (i = 0; i < csg->base.crelocs; i++) {
451 csg->relocs_bo[i]->space_accounted = 0; 451 csg->relocs_bo[i]->space_accounted = 0;
452 /* bo might be referenced from another context so have to use atomic opertions */ 452 /* bo might be referenced from another context so have to use atomic operations */
453 atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id); 453 atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id);
454 radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]); 454 radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
455 csg->relocs_bo[i] = NULL; 455 csg->relocs_bo[i] = NULL;
@@ -481,7 +481,7 @@ static int cs_gem_erase(struct radeon_cs_int *cs)
481 if (csg->relocs_bo) { 481 if (csg->relocs_bo) {
482 for (i = 0; i < csg->base.crelocs; i++) { 482 for (i = 0; i < csg->base.crelocs; i++) {
483 if (csg->relocs_bo[i]) { 483 if (csg->relocs_bo[i]) {
484 /* bo might be referenced from another context so have to use atomic opertions */ 484 /* bo might be referenced from another context so have to use atomic operations */
485 atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id); 485 atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id);
486 radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]); 486 radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
487 csg->relocs_bo[i] = NULL; 487 csg->relocs_bo[i] = NULL;
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 16a8b00b..965be24c 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -981,7 +981,7 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man,
981 /* bankw or bankh greater than 1 increase alignment requirement, not 981 /* bankw or bankh greater than 1 increase alignment requirement, not
982 * sure if it's worth using smaller bankw & bankh to stick with 2D 982 * sure if it's worth using smaller bankw & bankh to stick with 2D
983 * tiling on small surface rather than falling back to 1D tiling. 983 * tiling on small surface rather than falling back to 1D tiling.
984 * Use recommanded value based on tile size for now. 984 * Use recommended value based on tile size for now.
985 * 985 *
986 * fmask buffer has different optimal value figure them out once we 986 * fmask buffer has different optimal value figure them out once we
987 * use it. 987 * use it.