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authorThomas Klausner2014-07-15 12:22:52 -0500
committerMichel Dänzer2014-07-15 22:15:29 -0500
commit72f84b85afbe762b86ea8c095fee01e7d406b131 (patch)
treea1e9ac61977650910a5933dfd687194ef5189c07 /radeon
parente8c3c1358ecaf4e90f7d43762357ae6f8e2022b6 (diff)
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radeon: Remove superfluous parentheses.
Signed-off-by: Thomas Klausner <wiz@NetBSD.org>
Diffstat (limited to 'radeon')
-rw-r--r--radeon/radeon_surface.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 109bd6b5..9c3a1923 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -282,7 +282,7 @@ static int r6_surface_init_linear(struct radeon_surface_manager *surf_man,
282 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); 282 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
283 /* level0 and first mipmap need to have alignment */ 283 /* level0 and first mipmap need to have alignment */
284 offset = surf->bo_size; 284 offset = surf->bo_size;
285 if ((i == 0)) { 285 if (i == 0) {
286 offset = ALIGN(offset, surf->bo_alignment); 286 offset = ALIGN(offset, surf->bo_alignment);
287 } 287 }
288 } 288 }
@@ -310,7 +310,7 @@ static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_ma
310 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); 310 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
311 /* level0 and first mipmap need to have alignment */ 311 /* level0 and first mipmap need to have alignment */
312 offset = surf->bo_size; 312 offset = surf->bo_size;
313 if ((i == 0)) { 313 if (i == 0) {
314 offset = ALIGN(offset, surf->bo_alignment); 314 offset = ALIGN(offset, surf->bo_alignment);
315 } 315 }
316 } 316 }
@@ -343,7 +343,7 @@ static int r6_surface_init_1d(struct radeon_surface_manager *surf_man,
343 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); 343 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
344 /* level0 and first mipmap need to have alignment */ 344 /* level0 and first mipmap need to have alignment */
345 offset = surf->bo_size; 345 offset = surf->bo_size;
346 if ((i == 0)) { 346 if (i == 0) {
347 offset = ALIGN(offset, surf->bo_alignment); 347 offset = ALIGN(offset, surf->bo_alignment);
348 } 348 }
349 } 349 }
@@ -384,7 +384,7 @@ static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
384 } 384 }
385 /* level0 and first mipmap need to have alignment */ 385 /* level0 and first mipmap need to have alignment */
386 offset = surf->bo_size; 386 offset = surf->bo_size;
387 if ((i == 0)) { 387 if (i == 0) {
388 offset = ALIGN(offset, surf->bo_alignment); 388 offset = ALIGN(offset, surf->bo_alignment);
389 } 389 }
390 } 390 }
@@ -632,7 +632,7 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
632 surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset); 632 surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset);
633 /* level0 and first mipmap need to have alignment */ 633 /* level0 and first mipmap need to have alignment */
634 offset = surf->bo_size; 634 offset = surf->bo_size;
635 if ((i == 0)) { 635 if (i == 0) {
636 offset = ALIGN(offset, surf->bo_alignment); 636 offset = ALIGN(offset, surf->bo_alignment);
637 } 637 }
638 } 638 }
@@ -685,7 +685,7 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
685 } 685 }
686 /* level0 and first mipmap need to have alignment */ 686 /* level0 and first mipmap need to have alignment */
687 offset = surf->bo_size; 687 offset = surf->bo_size;
688 if ((i == 0)) { 688 if (i == 0) {
689 offset = ALIGN(offset, surf->bo_alignment); 689 offset = ALIGN(offset, surf->bo_alignment);
690 } 690 }
691 } 691 }
@@ -1524,7 +1524,7 @@ static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_ma
1524 si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset); 1524 si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset);
1525 /* level0 and first mipmap need to have alignment */ 1525 /* level0 and first mipmap need to have alignment */
1526 offset = surf->bo_size; 1526 offset = surf->bo_size;
1527 if ((i == 0)) { 1527 if (i == 0) {
1528 offset = ALIGN(offset, surf->bo_alignment); 1528 offset = ALIGN(offset, surf->bo_alignment);
1529 } 1529 }
1530 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { 1530 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
@@ -1567,7 +1567,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
1567 si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset); 1567 si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset);
1568 /* level0 and first mipmap need to have alignment */ 1568 /* level0 and first mipmap need to have alignment */
1569 offset = surf->bo_size; 1569 offset = surf->bo_size;
1570 if ((i == 0)) { 1570 if (i == 0) {
1571 offset = ALIGN(offset, alignment); 1571 offset = ALIGN(offset, alignment);
1572 } 1572 }
1573 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { 1573 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
@@ -1669,7 +1669,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
1669 } 1669 }
1670 /* level0 and first mipmap need to have alignment */ 1670 /* level0 and first mipmap need to have alignment */
1671 aligned_offset = offset = surf->bo_size; 1671 aligned_offset = offset = surf->bo_size;
1672 if ((i == 0)) { 1672 if (i == 0) {
1673 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); 1673 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
1674 } 1674 }
1675 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { 1675 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {