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authorMichel Dänzer2015-09-08 01:03:55 -0500
committerMichel Dänzer2015-11-10 03:06:57 -0600
commitc3deddd9c2bf54fa6bec3dbd9ec7eae5fa22e220 (patch)
treec984ba5bd876395b05b348a5e383f494f01da6c7 /radeon
parentce3185d3455c7711bffa3762ad32adee2537b773 (diff)
downloadexternal-libdrm-c3deddd9c2bf54fa6bec3dbd9ec7eae5fa22e220.tar.gz
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radeon: Handle surface offsets exceeding 32 bits correctly
The slice_size and bo_size fields were getting truncated to 32 bits. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'radeon')
-rw-r--r--radeon/radeon_surface.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index fad4bda3..5ec97454 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -163,7 +163,7 @@ static void surf_minify(struct radeon_surface *surf,
163 struct radeon_surface_level *surflevel, 163 struct radeon_surface_level *surflevel,
164 unsigned bpe, unsigned level, 164 unsigned bpe, unsigned level,
165 uint32_t xalign, uint32_t yalign, uint32_t zalign, 165 uint32_t xalign, uint32_t yalign, uint32_t zalign,
166 unsigned offset) 166 uint64_t offset)
167{ 167{
168 surflevel->npix_x = mip_minify(surf->npix_x, level); 168 surflevel->npix_x = mip_minify(surf->npix_x, level);
169 surflevel->npix_y = mip_minify(surf->npix_y, level); 169 surflevel->npix_y = mip_minify(surf->npix_y, level);
@@ -184,7 +184,7 @@ static void surf_minify(struct radeon_surface *surf,
184 184
185 surflevel->offset = offset; 185 surflevel->offset = offset;
186 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; 186 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
187 surflevel->slice_size = surflevel->pitch_bytes * surflevel->nblk_y; 187 surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y;
188 188
189 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; 189 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
190} 190}
@@ -570,7 +570,7 @@ static void eg_surf_minify(struct radeon_surface *surf,
570 unsigned mtilew, 570 unsigned mtilew,
571 unsigned mtileh, 571 unsigned mtileh,
572 unsigned mtileb, 572 unsigned mtileb,
573 unsigned offset) 573 uint64_t offset)
574{ 574{
575 unsigned mtile_pr, mtile_ps; 575 unsigned mtile_pr, mtile_ps;
576 576
@@ -598,7 +598,7 @@ static void eg_surf_minify(struct radeon_surface *surf,
598 598
599 surflevel->offset = offset; 599 surflevel->offset = offset;
600 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; 600 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
601 surflevel->slice_size = mtile_ps * mtileb * slice_pt; 601 surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;
602 602
603 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; 603 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
604} 604}
@@ -1415,7 +1415,7 @@ static void si_surf_minify(struct radeon_surface *surf,
1415 struct radeon_surface_level *surflevel, 1415 struct radeon_surface_level *surflevel,
1416 unsigned bpe, unsigned level, 1416 unsigned bpe, unsigned level,
1417 uint32_t xalign, uint32_t yalign, uint32_t zalign, 1417 uint32_t xalign, uint32_t yalign, uint32_t zalign,
1418 uint32_t slice_align, unsigned offset) 1418 uint32_t slice_align, uint64_t offset)
1419{ 1419{
1420 if (level == 0) { 1420 if (level == 0) {
1421 surflevel->npix_x = surf->npix_x; 1421 surflevel->npix_x = surf->npix_x;
@@ -1453,7 +1453,8 @@ static void si_surf_minify(struct radeon_surface *surf,
1453 1453
1454 surflevel->offset = offset; 1454 surflevel->offset = offset;
1455 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; 1455 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
1456 surflevel->slice_size = ALIGN(surflevel->pitch_bytes * surflevel->nblk_y, slice_align); 1456 surflevel->slice_size = ALIGN((uint64_t)surflevel->pitch_bytes * surflevel->nblk_y,
1457 (uint64_t)slice_align);
1457 1458
1458 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; 1459 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1459} 1460}
@@ -1462,7 +1463,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
1462 struct radeon_surface_level *surflevel, 1463 struct radeon_surface_level *surflevel,
1463 unsigned bpe, unsigned level, unsigned slice_pt, 1464 unsigned bpe, unsigned level, unsigned slice_pt,
1464 uint32_t xalign, uint32_t yalign, uint32_t zalign, 1465 uint32_t xalign, uint32_t yalign, uint32_t zalign,
1465 unsigned mtileb, unsigned offset) 1466 unsigned mtileb, uint64_t offset)
1466{ 1467{
1467 unsigned mtile_pr, mtile_ps; 1468 unsigned mtile_pr, mtile_ps;
1468 1469
@@ -1501,7 +1502,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
1501 mtile_ps = (mtile_pr * surflevel->nblk_y) / yalign; 1502 mtile_ps = (mtile_pr * surflevel->nblk_y) / yalign;
1502 surflevel->offset = offset; 1503 surflevel->offset = offset;
1503 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; 1504 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
1504 surflevel->slice_size = mtile_ps * mtileb * slice_pt; 1505 surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;
1505 1506
1506 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; 1507 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1507} 1508}