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authorDave Airlie2015-01-08 21:34:41 -0600
committerDave Airlie2015-01-19 00:47:34 -0600
commiteca91cf163d50090db36d0b2abbffcff813a2adf (patch)
tree304617ab1f38f8612537fd71ac7fb940860d7dbc /radeon
parenta5003c6f859c90d6e7693ce085c1cb4dd7d95f26 (diff)
downloadexternal-libdrm-eca91cf163d50090db36d0b2abbffcff813a2adf.tar.gz
external-libdrm-eca91cf163d50090db36d0b2abbffcff813a2adf.tar.xz
external-libdrm-eca91cf163d50090db36d0b2abbffcff813a2adf.zip
radeon: align r600/700 fmask to 128 X blocks.
After much searching and empricial testing, and reading of things I've no justifcation for this fix, other than it really appears this is what the hw is doing or close enough. It makes sense that each entry in the FMASK corresponds to an entry in the CMASKm and the CMASK is organised into 128x128 blocks, but I can't find anything in any of the docs/info from AMD. But I've spent a lot of time on this, and this seems to be the simplest fix, in that we don't over allocate things too much, once this fix in place we can nuke the extra multiplier in mesa. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'radeon')
-rw-r--r--radeon/radeon_surface.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 930017ef..bd9ee6d1 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -366,6 +366,8 @@ static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
366 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / 366 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
367 (tilew * surf->bpe * surf->nsamples); 367 (tilew * surf->bpe * surf->nsamples);
368 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); 368 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
369 if (surf->flags & RADEON_SURF_FMASK)
370 xalign = MAX2(128, xalign);
369 yalign = tilew * surf_man->hw_info.num_pipes; 371 yalign = tilew * surf_man->hw_info.num_pipes;
370 if (surf->flags & RADEON_SURF_SCANOUT) { 372 if (surf->flags & RADEON_SURF_SCANOUT) {
371 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); 373 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);