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author | Leo Liu | 2016-12-05 10:18:09 -0600 |
---|---|---|
committer | Marek Olšák | 2017-03-27 14:42:07 -0500 |
commit | 5a44f9e6c6a460a5ea0b698fb64d02b359927999 (patch) | |
tree | 3ce98d5ed070220f02315df82e2ab83c95587d66 /tests | |
parent | fee173dc77295c8624291a4336075361d5dafd67 (diff) | |
download | external-libdrm-5a44f9e6c6a460a5ea0b698fb64d02b359927999.tar.gz external-libdrm-5a44f9e6c6a460a5ea0b698fb64d02b359927999.tar.xz external-libdrm-5a44f9e6c6a460a5ea0b698fb64d02b359927999.zip |
tests/amdgpu: add uvd unit test support for vega10
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tests')
-rw-r--r-- | tests/amdgpu/cs_tests.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 82c55aa8..0885d974 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c | |||
@@ -175,11 +175,11 @@ static int submit(unsigned ndw, unsigned ip) | |||
175 | 175 | ||
176 | static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx) | 176 | static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx) |
177 | { | 177 | { |
178 | ib_cpu[(*idx)++] = 0x3BC4; | 178 | ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4; |
179 | ib_cpu[(*idx)++] = addr; | 179 | ib_cpu[(*idx)++] = addr; |
180 | ib_cpu[(*idx)++] = 0x3BC5; | 180 | ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5; |
181 | ib_cpu[(*idx)++] = addr >> 32; | 181 | ib_cpu[(*idx)++] = addr >> 32; |
182 | ib_cpu[(*idx)++] = 0x3BC3; | 182 | ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3; |
183 | ib_cpu[(*idx)++] = cmd << 1; | 183 | ib_cpu[(*idx)++] = cmd << 1; |
184 | } | 184 | } |
185 | 185 | ||
@@ -211,10 +211,12 @@ static void amdgpu_cs_uvd_create(void) | |||
211 | CU_ASSERT_EQUAL(r, 0); | 211 | CU_ASSERT_EQUAL(r, 0); |
212 | 212 | ||
213 | memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); | 213 | memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); |
214 | |||
214 | if (family_id >= AMDGPU_FAMILY_VI) { | 215 | if (family_id >= AMDGPU_FAMILY_VI) { |
215 | ((uint8_t*)msg)[0x10] = 7; | 216 | ((uint8_t*)msg)[0x10] = 7; |
216 | /* chip polaris 10/11 */ | 217 | /* chip beyond polaris 10/11 */ |
217 | if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { | 218 | if ((family_id == AMDGPU_FAMILY_AI) || |
219 | (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { | ||
218 | /* dpb size */ | 220 | /* dpb size */ |
219 | ((uint8_t*)msg)[0x28] = 0x00; | 221 | ((uint8_t*)msg)[0x28] = 0x00; |
220 | ((uint8_t*)msg)[0x29] = 0x94; | 222 | ((uint8_t*)msg)[0x29] = 0x94; |
@@ -287,13 +289,15 @@ static void amdgpu_cs_uvd_decode(void) | |||
287 | CU_ASSERT_EQUAL(r, 0); | 289 | CU_ASSERT_EQUAL(r, 0); |
288 | 290 | ||
289 | memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg)); | 291 | memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg)); |
292 | |||
290 | if (family_id >= AMDGPU_FAMILY_VI) { | 293 | if (family_id >= AMDGPU_FAMILY_VI) { |
291 | ptr[0x10] = 7; | 294 | ptr[0x10] = 7; |
292 | ptr[0x98] = 0x00; | 295 | ptr[0x98] = 0x00; |
293 | ptr[0x99] = 0x02; | 296 | ptr[0x99] = 0x02; |
294 | /* chip polaris10/11 */ | 297 | /* chip beyond polaris10/11 */ |
295 | if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { | 298 | if ((family_id == AMDGPU_FAMILY_AI) || |
296 | /*dpb size */ | 299 | (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { |
300 | /* dpb size */ | ||
297 | ptr[0x24] = 0x00; | 301 | ptr[0x24] = 0x00; |
298 | ptr[0x25] = 0x94; | 302 | ptr[0x25] = 0x94; |
299 | ptr[0x26] = 0x6B; | 303 | ptr[0x26] = 0x6B; |
@@ -335,9 +339,11 @@ static void amdgpu_cs_uvd_decode(void) | |||
335 | bs_addr = fb_addr + 4*1024; | 339 | bs_addr = fb_addr + 4*1024; |
336 | dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); | 340 | dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); |
337 | 341 | ||
338 | if ((family_id >= AMDGPU_FAMILY_VI) && | 342 | if (family_id >= AMDGPU_FAMILY_VI) { |
339 | (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { | 343 | if ((family_id == AMDGPU_FAMILY_AI) || |
340 | ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); | 344 | (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { |
345 | ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); | ||
346 | } | ||
341 | } | 347 | } |
342 | 348 | ||
343 | dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); | 349 | dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); |
@@ -348,12 +354,15 @@ static void amdgpu_cs_uvd_decode(void) | |||
348 | uvd_cmd(dt_addr, 0x2, &i); | 354 | uvd_cmd(dt_addr, 0x2, &i); |
349 | uvd_cmd(fb_addr, 0x3, &i); | 355 | uvd_cmd(fb_addr, 0x3, &i); |
350 | uvd_cmd(bs_addr, 0x100, &i); | 356 | uvd_cmd(bs_addr, 0x100, &i); |
357 | |||
351 | if (family_id >= AMDGPU_FAMILY_VI) { | 358 | if (family_id >= AMDGPU_FAMILY_VI) { |
352 | uvd_cmd(it_addr, 0x204, &i); | 359 | uvd_cmd(it_addr, 0x204, &i); |
353 | if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) | 360 | if ((family_id == AMDGPU_FAMILY_AI) || |
361 | (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) | ||
354 | uvd_cmd(ctx_addr, 0x206, &i); | 362 | uvd_cmd(ctx_addr, 0x206, &i); |
355 | } | 363 | } |
356 | ib_cpu[i++] = 0x3BC6; | 364 | |
365 | ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6; | ||
357 | ib_cpu[i++] = 0x1; | 366 | ib_cpu[i++] = 0x1; |
358 | for (; i % 16; ++i) | 367 | for (; i % 16; ++i) |
359 | ib_cpu[i] = 0x80000000; | 368 | ib_cpu[i] = 0x80000000; |