aboutsummaryrefslogtreecommitdiffstats
path: root/tests
diff options
context:
space:
mode:
authorAndrey Grodzovsky2017-11-09 22:30:01 -0600
committerChristian König2017-11-13 11:20:22 -0600
commit806d0803600000faecb4025d8e9c7490cb097c25 (patch)
treeb9dabfa5b4f388a375dabc762c003253b84d34e4 /tests
parent864219425d9cf2fb4df677aa93bd54051ebcafc2 (diff)
downloadexternal-libdrm-806d0803600000faecb4025d8e9c7490cb097c25.tar.gz
external-libdrm-806d0803600000faecb4025d8e9c7490cb097c25.tar.xz
external-libdrm-806d0803600000faecb4025d8e9c7490cb097c25.zip
amdgpu: Use new suite/test disabling functionality.
Switch from disabling tests during run to using the new disable API. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'tests')
-rw-r--r--tests/amdgpu/amdgpu_test.c14
-rw-r--r--tests/amdgpu/amdgpu_test.h15
-rw-r--r--tests/amdgpu/deadlock_tests.c8
-rw-r--r--tests/amdgpu/uvd_enc_tests.c81
-rw-r--r--tests/amdgpu/vce_tests.c65
-rw-r--r--tests/amdgpu/vcn_tests.c74
6 files changed, 123 insertions, 134 deletions
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 68ec5d39..91010dcc 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -150,15 +150,15 @@ static Suites_Active_Status suites_active_stat[] = {
150 }, 150 },
151 { 151 {
152 .pName = VCE_TESTS_STR, 152 .pName = VCE_TESTS_STR,
153 .pActive = always_active, 153 .pActive = suite_vce_tests_enable,
154 }, 154 },
155 { 155 {
156 .pName = VCN_TESTS_STR, 156 .pName = VCN_TESTS_STR,
157 .pActive = always_active, 157 .pActive = suite_vcn_tests_enable,
158 }, 158 },
159 { 159 {
160 .pName = UVD_ENC_TESTS_STR, 160 .pName = UVD_ENC_TESTS_STR,
161 .pActive = always_active, 161 .pActive = suite_uvd_enc_tests_enable,
162 }, 162 },
163 { 163 {
164 .pName = DEADLOCK_TESTS_STR, 164 .pName = DEADLOCK_TESTS_STR,
@@ -409,6 +409,14 @@ static void amdgpu_disable_suits()
409 if (amdgpu_set_suite_active(suites_active_stat[i].pName, 409 if (amdgpu_set_suite_active(suites_active_stat[i].pName,
410 suites_active_stat[i].pActive())) 410 suites_active_stat[i].pActive()))
411 fprintf(stderr, "suit deactivation failed - %s\n", CU_get_error_msg()); 411 fprintf(stderr, "suit deactivation failed - %s\n", CU_get_error_msg());
412
413 /* Explicitly disable specific tests due to known bugs or preferences */
414 /*
415 * BUG: Compute ring stalls and never recovers when the address is
416 * written after the command already submitted
417 */
418 if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, "compute ring block test", CU_FALSE))
419 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
412} 420}
413 421
414/* The main() function for setting up and running the tests. 422/* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 9ccc1ffd..dd236edc 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -100,6 +100,11 @@ int suite_vce_tests_init();
100int suite_vce_tests_clean(); 100int suite_vce_tests_clean();
101 101
102/** 102/**
103 * Decide if the suite is enabled by default or not.
104 */
105CU_BOOL suite_vce_tests_enable(void);
106
107/**
103 * Tests in vce test suite 108 * Tests in vce test suite
104 */ 109 */
105extern CU_TestInfo vce_tests[]; 110extern CU_TestInfo vce_tests[];
@@ -115,6 +120,11 @@ int suite_vcn_tests_init();
115int suite_vcn_tests_clean(); 120int suite_vcn_tests_clean();
116 121
117/** 122/**
123 * Decide if the suite is enabled by default or not.
124 */
125CU_BOOL suite_vcn_tests_enable(void);
126
127/**
118+ * Tests in vcn test suite 128+ * Tests in vcn test suite
119+ */ 129+ */
120extern CU_TestInfo vcn_tests[]; 130extern CU_TestInfo vcn_tests[];
@@ -130,6 +140,11 @@ int suite_uvd_enc_tests_init();
130int suite_uvd_enc_tests_clean(); 140int suite_uvd_enc_tests_clean();
131 141
132/** 142/**
143 * Decide if the suite is enabled by default or not.
144 */
145CU_BOOL suite_uvd_enc_tests_enable(void);
146
147/**
133 * Tests in uvd enc test suite 148 * Tests in uvd enc test suite
134 */ 149 */
135extern CU_TestInfo uvd_enc_tests[]; 150extern CU_TestInfo uvd_enc_tests[];
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index e23d903f..f5c4552a 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -119,13 +119,7 @@ int suite_deadlock_tests_clean(void)
119 119
120CU_TestInfo deadlock_tests[] = { 120CU_TestInfo deadlock_tests[] = {
121 { "gfx ring block test", amdgpu_deadlock_gfx }, 121 { "gfx ring block test", amdgpu_deadlock_gfx },
122 122 { "compute ring block test", amdgpu_deadlock_compute },
123 /*
124 * BUG: Compute ring stalls and never recovers when the address is
125 * written after the command already submitted
126 */
127 /* { "compute ring block test", amdgpu_deadlock_compute }, */
128
129 CU_TEST_INFO_NULL, 123 CU_TEST_INFO_NULL,
130}; 124};
131 125
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
index bbda1312..bed8494a 100644
--- a/tests/amdgpu/uvd_enc_tests.c
+++ b/tests/amdgpu/uvd_enc_tests.c
@@ -79,7 +79,6 @@ static void amdgpu_cs_uvd_enc_session_init(void);
79static void amdgpu_cs_uvd_enc_encode(void); 79static void amdgpu_cs_uvd_enc_encode(void);
80static void amdgpu_cs_uvd_enc_destroy(void); 80static void amdgpu_cs_uvd_enc_destroy(void);
81 81
82static bool uvd_enc_support(void);
83 82
84CU_TestInfo uvd_enc_tests[] = { 83CU_TestInfo uvd_enc_tests[] = {
85 { "UVD ENC create", amdgpu_cs_uvd_enc_create }, 84 { "UVD ENC create", amdgpu_cs_uvd_enc_create },
@@ -89,6 +88,27 @@ CU_TestInfo uvd_enc_tests[] = {
89 CU_TEST_INFO_NULL, 88 CU_TEST_INFO_NULL,
90}; 89};
91 90
91CU_BOOL suite_uvd_enc_tests_enable(void)
92{
93 int r;
94 struct drm_amdgpu_info_hw_ip info;
95
96 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
97 &minor_version, &device_handle))
98 return CU_FALSE;
99
100 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info);
101
102 if (amdgpu_device_deinitialize(device_handle))
103 return CU_FALSE;
104
105 if (!info.available_rings)
106 printf("\n\nThe ASIC NOT support UVD ENC, suite disabled.\n");
107
108 return (r == 0 && (info.available_rings ? CU_TRUE : CU_FALSE));
109}
110
111
92int suite_uvd_enc_tests_init(void) 112int suite_uvd_enc_tests_init(void)
93{ 113{
94 int r; 114 int r;
@@ -100,11 +120,6 @@ int suite_uvd_enc_tests_init(void)
100 120
101 family_id = device_handle->info.family_id; 121 family_id = device_handle->info.family_id;
102 122
103 if (!uvd_enc_support()) {
104 printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n");
105 return CUE_SUCCESS;
106 }
107
108 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 123 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
109 if (r) 124 if (r)
110 return CUE_SINIT_FAILED; 125 return CUE_SINIT_FAILED;
@@ -123,28 +138,18 @@ int suite_uvd_enc_tests_clean(void)
123{ 138{
124 int r; 139 int r;
125 140
126 if (!uvd_enc_support()) { 141 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
127 142 ib_mc_address, IB_SIZE);
128 r = amdgpu_device_deinitialize(device_handle); 143 if (r)
129 if (r) 144 return CUE_SCLEAN_FAILED;
130 return CUE_SCLEAN_FAILED;
131
132 return CUE_SUCCESS;
133 } else {
134
135 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
136 ib_mc_address, IB_SIZE);
137 if (r)
138 return CUE_SCLEAN_FAILED;
139 145
140 r = amdgpu_cs_ctx_free(context_handle); 146 r = amdgpu_cs_ctx_free(context_handle);
141 if (r) 147 if (r)
142 return CUE_SCLEAN_FAILED; 148 return CUE_SCLEAN_FAILED;
143 149
144 r = amdgpu_device_deinitialize(device_handle); 150 r = amdgpu_device_deinitialize(device_handle);
145 if (r) 151 if (r)
146 return CUE_SCLEAN_FAILED; 152 return CUE_SCLEAN_FAILED;
147 }
148 153
149 return CUE_SUCCESS; 154 return CUE_SUCCESS;
150} 155}
@@ -240,26 +245,10 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo)
240 memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); 245 memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo));
241} 246}
242 247
243static bool uvd_enc_support(void)
244{
245 int r;
246 struct drm_amdgpu_info_hw_ip info;
247
248 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info);
249
250 if (r)
251 return false;
252 else
253 return (info.available_rings?true:false);
254}
255
256static void amdgpu_cs_uvd_enc_create(void) 248static void amdgpu_cs_uvd_enc_create(void)
257{ 249{
258 int len, r; 250 int len, r;
259 251
260 if (!uvd_enc_support())
261 return;
262
263 enc.width = 160; 252 enc.width = 160;
264 enc.height = 128; 253 enc.height = 128;
265 254
@@ -296,9 +285,6 @@ static void amdgpu_cs_uvd_enc_session_init(void)
296{ 285{
297 int len, r; 286 int len, r;
298 287
299 if (!uvd_enc_support())
300 return;
301
302 len = 0; 288 len = 0;
303 memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); 289 memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
304 len += sizeof(uve_session_info) / 4; 290 len += sizeof(uve_session_info) / 4;
@@ -354,8 +340,6 @@ static void amdgpu_cs_uvd_enc_encode(void)
354 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; 340 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
355 cpb_size = vbuf_size * 10; 341 cpb_size = vbuf_size * 10;
356 342
357 if (!uvd_enc_support())
358 return;
359 343
360 num_resources = 0; 344 num_resources = 0;
361 alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM); 345 alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM);
@@ -489,9 +473,6 @@ static void amdgpu_cs_uvd_enc_destroy(void)
489 struct amdgpu_uvd_enc_bo sw_ctx; 473 struct amdgpu_uvd_enc_bo sw_ctx;
490 int len, r; 474 int len, r;
491 475
492 if (!uvd_enc_support())
493 return;
494
495 num_resources = 0; 476 num_resources = 0;
496 resources[num_resources++] = ib_handle; 477 resources[num_resources++] = ib_handle;
497 478
diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c
index cf44c132..75821bbb 100644
--- a/tests/amdgpu/vce_tests.c
+++ b/tests/amdgpu/vce_tests.c
@@ -88,6 +88,27 @@ CU_TestInfo vce_tests[] = {
88 CU_TEST_INFO_NULL, 88 CU_TEST_INFO_NULL,
89}; 89};
90 90
91
92CU_BOOL suite_vce_tests_enable(void)
93{
94 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
95 &minor_version, &device_handle))
96 return CU_FALSE;
97
98 family_id = device_handle->info.family_id;
99
100 if (amdgpu_device_deinitialize(device_handle))
101 return CU_FALSE;
102
103
104 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
105 printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
106 return CU_FALSE;
107 }
108
109 return CU_TRUE;
110}
111
91int suite_vce_tests_init(void) 112int suite_vce_tests_init(void)
92{ 113{
93 int r; 114 int r;
@@ -106,11 +127,6 @@ int suite_vce_tests_init(void)
106 family_id = device_handle->info.family_id; 127 family_id = device_handle->info.family_id;
107 vce_harvest_config = device_handle->info.vce_harvest_config; 128 vce_harvest_config = device_handle->info.vce_harvest_config;
108 129
109 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
110 printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n");
111 return CUE_SUCCESS;
112 }
113
114 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 130 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
115 if (r) 131 if (r)
116 return CUE_SINIT_FAILED; 132 return CUE_SINIT_FAILED;
@@ -131,24 +147,18 @@ int suite_vce_tests_clean(void)
131{ 147{
132 int r; 148 int r;
133 149
134 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { 150 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
135 r = amdgpu_device_deinitialize(device_handle); 151 ib_mc_address, IB_SIZE);
136 if (r) 152 if (r)
137 return CUE_SCLEAN_FAILED; 153 return CUE_SCLEAN_FAILED;
138 } else { 154
139 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, 155 r = amdgpu_cs_ctx_free(context_handle);
140 ib_mc_address, IB_SIZE); 156 if (r)
141 if (r) 157 return CUE_SCLEAN_FAILED;
142 return CUE_SCLEAN_FAILED; 158
143 159 r = amdgpu_device_deinitialize(device_handle);
144 r = amdgpu_cs_ctx_free(context_handle); 160 if (r)
145 if (r) 161 return CUE_SCLEAN_FAILED;
146 return CUE_SCLEAN_FAILED;
147
148 r = amdgpu_device_deinitialize(device_handle);
149 if (r)
150 return CUE_SCLEAN_FAILED;
151 }
152 162
153 return CUE_SUCCESS; 163 return CUE_SUCCESS;
154} 164}
@@ -248,9 +258,6 @@ static void amdgpu_cs_vce_create(void)
248 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 258 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
249 int len, r; 259 int len, r;
250 260
251 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
252 return;
253
254 enc.width = vce_create[6]; 261 enc.width = vce_create[6];
255 enc.height = vce_create[7]; 262 enc.height = vce_create[7];
256 263
@@ -444,9 +451,6 @@ static void amdgpu_cs_vce_encode(void)
444 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 451 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
445 int i, r; 452 int i, r;
446 453
447 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
448 return;
449
450 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; 454 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
451 cpb_size = vbuf_size * 10; 455 cpb_size = vbuf_size * 10;
452 num_resources = 0; 456 num_resources = 0;
@@ -525,9 +529,6 @@ static void amdgpu_cs_vce_destroy(void)
525{ 529{
526 int len, r; 530 int len, r;
527 531
528 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI)
529 return;
530
531 num_resources = 0; 532 num_resources = 0;
532 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 533 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
533 resources[num_resources++] = enc.fb[0].handle; 534 resources[num_resources++] = enc.fb[0].handle;
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index 2b1696dd..53a2d08e 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -82,6 +82,27 @@ CU_TestInfo vcn_tests[] = {
82 CU_TEST_INFO_NULL, 82 CU_TEST_INFO_NULL,
83}; 83};
84 84
85CU_BOOL suite_vcn_tests_enable(void)
86{
87
88 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
89 &minor_version, &device_handle))
90 return CU_FALSE;
91
92 family_id = device_handle->info.family_id;
93
94 if (amdgpu_device_deinitialize(device_handle))
95 return CU_FALSE;
96
97
98 if (family_id < AMDGPU_FAMILY_RV) {
99 printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
100 return CU_FALSE;
101 }
102
103 return CU_TRUE;
104}
105
85int suite_vcn_tests_init(void) 106int suite_vcn_tests_init(void)
86{ 107{
87 int r; 108 int r;
@@ -93,11 +114,6 @@ int suite_vcn_tests_init(void)
93 114
94 family_id = device_handle->info.family_id; 115 family_id = device_handle->info.family_id;
95 116
96 if (family_id < AMDGPU_FAMILY_RV) {
97 printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n");
98 return CUE_SUCCESS;
99 }
100
101 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 117 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
102 if (r) 118 if (r)
103 return CUE_SINIT_FAILED; 119 return CUE_SINIT_FAILED;
@@ -116,26 +132,18 @@ int suite_vcn_tests_clean(void)
116{ 132{
117 int r; 133 int r;
118 134
119 if (family_id < AMDGPU_FAMILY_RV) { 135 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
120 r = amdgpu_device_deinitialize(device_handle); 136 ib_mc_address, IB_SIZE);
121 if (r) 137 if (r)
122 return CUE_SCLEAN_FAILED; 138 return CUE_SCLEAN_FAILED;
123 } else {
124 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
125 ib_mc_address, IB_SIZE);
126 if (r)
127 return CUE_SCLEAN_FAILED;
128
129 r = amdgpu_cs_ctx_free(context_handle);
130 if (r)
131 return CUE_SCLEAN_FAILED;
132
133 r = amdgpu_device_deinitialize(device_handle);
134 if (r)
135 return CUE_SCLEAN_FAILED;
136 }
137 139
138 return CUE_SUCCESS; 140 r = amdgpu_cs_ctx_free(context_handle);
141 if (r)
142 return CUE_SCLEAN_FAILED;
143
144 r = amdgpu_device_deinitialize(device_handle);
145 if (r)
146 return CUE_SCLEAN_FAILED;
139} 147}
140 148
141static int submit(unsigned ndw, unsigned ip) 149static int submit(unsigned ndw, unsigned ip)
@@ -244,9 +252,6 @@ static void amdgpu_cs_vcn_dec_create(void)
244 struct amdgpu_vcn_bo msg_buf; 252 struct amdgpu_vcn_bo msg_buf;
245 int len, r; 253 int len, r;
246 254
247 if (family_id < AMDGPU_FAMILY_RV)
248 return;
249
250 num_resources = 0; 255 num_resources = 0;
251 alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT); 256 alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
252 resources[num_resources++] = msg_buf.handle; 257 resources[num_resources++] = msg_buf.handle;
@@ -282,9 +287,6 @@ static void amdgpu_cs_vcn_dec_decode(void)
282 int size, len, i, r; 287 int size, len, i, r;
283 uint8_t *dec; 288 uint8_t *dec;
284 289
285 if (family_id < AMDGPU_FAMILY_RV)
286 return;
287
288 size = 4*1024; /* msg */ 290 size = 4*1024; /* msg */
289 size += 4*1024; /* fb */ 291 size += 4*1024; /* fb */
290 size += 4096; /*it_scaling_table*/ 292 size += 4096; /*it_scaling_table*/
@@ -355,9 +357,6 @@ static void amdgpu_cs_vcn_dec_destroy(void)
355 struct amdgpu_vcn_bo msg_buf; 357 struct amdgpu_vcn_bo msg_buf;
356 int len, r; 358 int len, r;
357 359
358 if (family_id < AMDGPU_FAMILY_RV)
359 return;
360
361 num_resources = 0; 360 num_resources = 0;
362 alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT); 361 alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
363 resources[num_resources++] = msg_buf.handle; 362 resources[num_resources++] = msg_buf.handle;
@@ -387,24 +386,15 @@ static void amdgpu_cs_vcn_dec_destroy(void)
387 386
388static void amdgpu_cs_vcn_enc_create(void) 387static void amdgpu_cs_vcn_enc_create(void)
389{ 388{
390 if (family_id < AMDGPU_FAMILY_RV)
391 return;
392
393 /* TODO */ 389 /* TODO */
394} 390}
395 391
396static void amdgpu_cs_vcn_enc_encode(void) 392static void amdgpu_cs_vcn_enc_encode(void)
397{ 393{
398 if (family_id < AMDGPU_FAMILY_RV)
399 return;
400
401 /* TODO */ 394 /* TODO */
402} 395}
403 396
404static void amdgpu_cs_vcn_enc_destroy(void) 397static void amdgpu_cs_vcn_enc_destroy(void)
405{ 398{
406 if (family_id < AMDGPU_FAMILY_RV)
407 return;
408
409 /* TODO */ 399 /* TODO */
410} 400}