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authorHawking Zhang2018-01-07 21:20:29 -0600
committerAlex Deucher2018-01-12 11:15:40 -0600
commitcbbb8a332d972a4ab18622f1c53de21324735fef (patch)
treec2900ccaf430af34703246cc2ccf98fa7399d540 /tests
parent168dbe9a0ee29dbe5ddd16706147f2e6d8ad5576 (diff)
downloadexternal-libdrm-cbbb8a332d972a4ab18622f1c53de21324735fef.tar.gz
external-libdrm-cbbb8a332d972a4ab18622f1c53de21324735fef.tar.xz
external-libdrm-cbbb8a332d972a4ab18622f1c53de21324735fef.zip
tests/amdgpu: execute const fill on all the available rings
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian K├Ânig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tests')
-rw-r--r--tests/amdgpu/basic_tests.c147
1 files changed, 77 insertions, 70 deletions
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 837ee9aa..0a198e48 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -981,9 +981,10 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
981 struct amdgpu_cs_request *ibs_request; 981 struct amdgpu_cs_request *ibs_request;
982 uint64_t bo_mc; 982 uint64_t bo_mc;
983 volatile uint32_t *bo_cpu; 983 volatile uint32_t *bo_cpu;
984 int i, j, r, loop; 984 int i, j, r, loop, ring_id;
985 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; 985 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
986 amdgpu_va_handle va_handle; 986 amdgpu_va_handle va_handle;
987 struct drm_amdgpu_info_hw_ip hw_ip_info;
987 988
988 pm4 = calloc(pm4_dw, sizeof(*pm4)); 989 pm4 = calloc(pm4_dw, sizeof(*pm4));
989 CU_ASSERT_NOT_EQUAL(pm4, NULL); 990 CU_ASSERT_NOT_EQUAL(pm4, NULL);
@@ -994,6 +995,9 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
994 ibs_request = calloc(1, sizeof(*ibs_request)); 995 ibs_request = calloc(1, sizeof(*ibs_request));
995 CU_ASSERT_NOT_EQUAL(ibs_request, NULL); 996 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
996 997
998 r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info);
999 CU_ASSERT_EQUAL(r, 0);
1000
997 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 1001 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
998 CU_ASSERT_EQUAL(r, 0); 1002 CU_ASSERT_EQUAL(r, 0);
999 1003
@@ -1001,83 +1005,86 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
1001 resources = calloc(1, sizeof(amdgpu_bo_handle)); 1005 resources = calloc(1, sizeof(amdgpu_bo_handle));
1002 CU_ASSERT_NOT_EQUAL(resources, NULL); 1006 CU_ASSERT_NOT_EQUAL(resources, NULL);
1003 1007
1004 loop = 0; 1008 for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) {
1005 while(loop < 2) { 1009 loop = 0;
1006 /* allocate UC bo for sDMA use */ 1010 while(loop < 2) {
1007 r = amdgpu_bo_alloc_and_map(device_handle, 1011 /* allocate UC bo for sDMA use */
1008 sdma_write_length, 4096, 1012 r = amdgpu_bo_alloc_and_map(device_handle,
1009 AMDGPU_GEM_DOMAIN_GTT, 1013 sdma_write_length, 4096,
1010 gtt_flags[loop], &bo, (void**)&bo_cpu, 1014 AMDGPU_GEM_DOMAIN_GTT,
1011 &bo_mc, &va_handle); 1015 gtt_flags[loop], &bo, (void**)&bo_cpu,
1012 CU_ASSERT_EQUAL(r, 0); 1016 &bo_mc, &va_handle);
1017 CU_ASSERT_EQUAL(r, 0);
1013 1018
1014 /* clear bo */ 1019 /* clear bo */
1015 memset((void*)bo_cpu, 0, sdma_write_length); 1020 memset((void*)bo_cpu, 0, sdma_write_length);
1016 1021
1017 resources[0] = bo; 1022 resources[0] = bo;
1018 1023
1019 /* fulfill PM4: test DMA const fill */ 1024 /* fulfill PM4: test DMA const fill */
1020 i = j = 0; 1025 i = j = 0;
1021 if (ip_type == AMDGPU_HW_IP_DMA) { 1026 if (ip_type == AMDGPU_HW_IP_DMA) {
1022 if (family_id == AMDGPU_FAMILY_SI) { 1027 if (family_id == AMDGPU_FAMILY_SI) {
1023 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, 0, 0, 0, 1028 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI,
1024 sdma_write_length / 4); 1029 0, 0, 0,
1025 pm4[i++] = 0xfffffffc & bo_mc; 1030 sdma_write_length / 4);
1026 pm4[i++] = 0xdeadbeaf; 1031 pm4[i++] = 0xfffffffc & bo_mc;
1027 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; 1032 pm4[i++] = 0xdeadbeaf;
1028 } else { 1033 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16;
1029 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 1034 } else {
1030 SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); 1035 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
1031 pm4[i++] = 0xffffffff & bo_mc; 1036 SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
1032 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; 1037 pm4[i++] = 0xffffffff & bo_mc;
1033 pm4[i++] = 0xdeadbeaf; 1038 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1034 if (family_id >= AMDGPU_FAMILY_AI) 1039 pm4[i++] = 0xdeadbeaf;
1035 pm4[i++] = sdma_write_length - 1; 1040 if (family_id >= AMDGPU_FAMILY_AI)
1036 else 1041 pm4[i++] = sdma_write_length - 1;
1042 else
1043 pm4[i++] = sdma_write_length;
1044 }
1045 } else if ((ip_type == AMDGPU_HW_IP_GFX) ||
1046 (ip_type == AMDGPU_HW_IP_COMPUTE)) {
1047 if (family_id == AMDGPU_FAMILY_SI) {
1048 pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4);
1049 pm4[i++] = 0xdeadbeaf;
1050 pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) |
1051 PACKET3_DMA_DATA_SI_DST_SEL(0) |
1052 PACKET3_DMA_DATA_SI_SRC_SEL(2) |
1053 PACKET3_DMA_DATA_SI_CP_SYNC;
1054 pm4[i++] = 0xffffffff & bo_mc;
1055 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1037 pm4[i++] = sdma_write_length; 1056 pm4[i++] = sdma_write_length;
1057 } else {
1058 pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
1059 pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
1060 PACKET3_DMA_DATA_DST_SEL(0) |
1061 PACKET3_DMA_DATA_SRC_SEL(2) |
1062 PACKET3_DMA_DATA_CP_SYNC;
1063 pm4[i++] = 0xdeadbeaf;
1064 pm4[i++] = 0;
1065 pm4[i++] = 0xfffffffc & bo_mc;
1066 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1067 pm4[i++] = sdma_write_length;
1068 }
1038 } 1069 }
1039 } else if ((ip_type == AMDGPU_HW_IP_GFX) ||
1040 (ip_type == AMDGPU_HW_IP_COMPUTE)) {
1041 if (family_id == AMDGPU_FAMILY_SI) {
1042 pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4);
1043 pm4[i++] = 0xdeadbeaf;
1044 pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) |
1045 PACKET3_DMA_DATA_SI_DST_SEL(0) |
1046 PACKET3_DMA_DATA_SI_SRC_SEL(2) |
1047 PACKET3_DMA_DATA_SI_CP_SYNC;
1048 pm4[i++] = 0xffffffff & bo_mc;
1049 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1050 pm4[i++] = sdma_write_length;
1051 } else {
1052 pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
1053 pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
1054 PACKET3_DMA_DATA_DST_SEL(0) |
1055 PACKET3_DMA_DATA_SRC_SEL(2) |
1056 PACKET3_DMA_DATA_CP_SYNC;
1057 pm4[i++] = 0xdeadbeaf;
1058 pm4[i++] = 0;
1059 pm4[i++] = 0xfffffffc & bo_mc;
1060 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1061 pm4[i++] = sdma_write_length;
1062 }
1063 }
1064 1070
1065 amdgpu_test_exec_cs_helper(context_handle, 1071 amdgpu_test_exec_cs_helper(context_handle,
1066 ip_type, 0, 1072 ip_type, ring_id,
1067 i, pm4, 1073 i, pm4,
1068 1, resources, 1074 1, resources,
1069 ib_info, ibs_request); 1075 ib_info, ibs_request);
1070 1076
1071 /* verify if SDMA test result meets with expected */ 1077 /* verify if SDMA test result meets with expected */
1072 i = 0; 1078 i = 0;
1073 while(i < (sdma_write_length / 4)) { 1079 while(i < (sdma_write_length / 4)) {
1074 CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); 1080 CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
1075 } 1081 }
1076 1082
1077 r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, 1083 r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc,
1078 sdma_write_length); 1084 sdma_write_length);
1079 CU_ASSERT_EQUAL(r, 0); 1085 CU_ASSERT_EQUAL(r, 0);
1080 loop++; 1086 loop++;
1087 }
1081 } 1088 }
1082 /* clean resources */ 1089 /* clean resources */
1083 free(resources); 1090 free(resources);