diff options
-rw-r--r-- | include/drm/nouveau_class.h | 611 | ||||
-rw-r--r-- | include/drm/nouveau_ioctl.h | 128 |
2 files changed, 739 insertions, 0 deletions
diff --git a/include/drm/nouveau_class.h b/include/drm/nouveau_class.h new file mode 100644 index 00000000..cbfeea0e --- /dev/null +++ b/include/drm/nouveau_class.h | |||
@@ -0,0 +1,611 @@ | |||
1 | #ifndef __NVIF_CLASS_H__ | ||
2 | #define __NVIF_CLASS_H__ | ||
3 | |||
4 | /******************************************************************************* | ||
5 | * class identifiers | ||
6 | ******************************************************************************/ | ||
7 | |||
8 | /* the below match nvidia-assigned (either in hw, or sw) class numbers */ | ||
9 | #define NV_DEVICE 0x00000080 | ||
10 | |||
11 | #define NV_DMA_FROM_MEMORY 0x00000002 | ||
12 | #define NV_DMA_TO_MEMORY 0x00000003 | ||
13 | #define NV_DMA_IN_MEMORY 0x0000003d | ||
14 | |||
15 | #define FERMI_TWOD_A 0x0000902d | ||
16 | |||
17 | #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x0000903d | ||
18 | |||
19 | #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 | ||
20 | #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 | ||
21 | |||
22 | #define NV04_DISP 0x00000046 | ||
23 | |||
24 | #define NV03_CHANNEL_DMA 0x0000006b | ||
25 | #define NV10_CHANNEL_DMA 0x0000006e | ||
26 | #define NV17_CHANNEL_DMA 0x0000176e | ||
27 | #define NV40_CHANNEL_DMA 0x0000406e | ||
28 | #define NV50_CHANNEL_DMA 0x0000506e | ||
29 | #define G82_CHANNEL_DMA 0x0000826e | ||
30 | |||
31 | #define NV50_CHANNEL_GPFIFO 0x0000506f | ||
32 | #define G82_CHANNEL_GPFIFO 0x0000826f | ||
33 | #define FERMI_CHANNEL_GPFIFO 0x0000906f | ||
34 | #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f | ||
35 | #define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f | ||
36 | |||
37 | #define NV50_DISP 0x00005070 | ||
38 | #define G82_DISP 0x00008270 | ||
39 | #define GT200_DISP 0x00008370 | ||
40 | #define GT214_DISP 0x00008570 | ||
41 | #define GT206_DISP 0x00008870 | ||
42 | #define GF110_DISP 0x00009070 | ||
43 | #define GK104_DISP 0x00009170 | ||
44 | #define GK110_DISP 0x00009270 | ||
45 | #define GM107_DISP 0x00009470 | ||
46 | #define GM204_DISP 0x00009570 | ||
47 | |||
48 | #define NV50_DISP_CURSOR 0x0000507a | ||
49 | #define G82_DISP_CURSOR 0x0000827a | ||
50 | #define GT214_DISP_CURSOR 0x0000857a | ||
51 | #define GF110_DISP_CURSOR 0x0000907a | ||
52 | #define GK104_DISP_CURSOR 0x0000917a | ||
53 | |||
54 | #define NV50_DISP_OVERLAY 0x0000507b | ||
55 | #define G82_DISP_OVERLAY 0x0000827b | ||
56 | #define GT214_DISP_OVERLAY 0x0000857b | ||
57 | #define GF110_DISP_OVERLAY 0x0000907b | ||
58 | #define GK104_DISP_OVERLAY 0x0000917b | ||
59 | |||
60 | #define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c | ||
61 | #define G82_DISP_BASE_CHANNEL_DMA 0x0000827c | ||
62 | #define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c | ||
63 | #define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c | ||
64 | #define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c | ||
65 | #define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c | ||
66 | #define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c | ||
67 | |||
68 | #define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d | ||
69 | #define G82_DISP_CORE_CHANNEL_DMA 0x0000827d | ||
70 | #define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d | ||
71 | #define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d | ||
72 | #define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d | ||
73 | #define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d | ||
74 | #define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d | ||
75 | #define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d | ||
76 | #define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d | ||
77 | #define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d | ||
78 | |||
79 | #define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e | ||
80 | #define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e | ||
81 | #define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e | ||
82 | #define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e | ||
83 | #define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e | ||
84 | #define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e | ||
85 | |||
86 | #define FERMI_A 0x00009097 | ||
87 | #define FERMI_B 0x00009197 | ||
88 | #define FERMI_C 0x00009297 | ||
89 | |||
90 | #define KEPLER_A 0x0000a097 | ||
91 | #define KEPLER_B 0x0000a197 | ||
92 | #define KEPLER_C 0x0000a297 | ||
93 | |||
94 | #define MAXWELL_A 0x0000b097 | ||
95 | #define MAXWELL_B 0x0000b197 | ||
96 | |||
97 | #define FERMI_COMPUTE_A 0x000090c0 | ||
98 | #define FERMI_COMPUTE_B 0x000091c0 | ||
99 | |||
100 | #define KEPLER_COMPUTE_A 0x0000a0c0 | ||
101 | #define KEPLER_COMPUTE_B 0x0000a1c0 | ||
102 | |||
103 | #define MAXWELL_COMPUTE_A 0x0000b0c0 | ||
104 | #define MAXWELL_COMPUTE_B 0x0000b1c0 | ||
105 | |||
106 | #define MAXWELL_DMA_COPY_A 0x0000b0b5 | ||
107 | |||
108 | /******************************************************************************* | ||
109 | * client | ||
110 | ******************************************************************************/ | ||
111 | |||
112 | #define NV_CLIENT_DEVLIST 0x00 | ||
113 | |||
114 | struct nv_client_devlist_v0 { | ||
115 | __u8 version; | ||
116 | __u8 count; | ||
117 | __u8 pad02[6]; | ||
118 | __u64 device[]; | ||
119 | }; | ||
120 | |||
121 | |||
122 | /******************************************************************************* | ||
123 | * device | ||
124 | ******************************************************************************/ | ||
125 | |||
126 | struct nv_device_v0 { | ||
127 | __u8 version; | ||
128 | __u8 pad01[7]; | ||
129 | __u64 device; /* device identifier, ~0 for client default */ | ||
130 | #define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL | ||
131 | #define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL | ||
132 | #define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL | ||
133 | #define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL | ||
134 | #define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL | ||
135 | #define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL | ||
136 | #define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL | ||
137 | #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL | ||
138 | #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL | ||
139 | #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL | ||
140 | #define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL | ||
141 | #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL | ||
142 | #define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL | ||
143 | #define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL | ||
144 | #define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL | ||
145 | #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL | ||
146 | #define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL | ||
147 | #define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL | ||
148 | #define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL | ||
149 | #define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL | ||
150 | #define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL | ||
151 | __u64 disable; /* disable particular subsystems */ | ||
152 | __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ | ||
153 | }; | ||
154 | |||
155 | #define NV_DEVICE_V0_INFO 0x00 | ||
156 | |||
157 | struct nv_device_info_v0 { | ||
158 | __u8 version; | ||
159 | #define NV_DEVICE_INFO_V0_IGP 0x00 | ||
160 | #define NV_DEVICE_INFO_V0_PCI 0x01 | ||
161 | #define NV_DEVICE_INFO_V0_AGP 0x02 | ||
162 | #define NV_DEVICE_INFO_V0_PCIE 0x03 | ||
163 | #define NV_DEVICE_INFO_V0_SOC 0x04 | ||
164 | __u8 platform; | ||
165 | __u16 chipset; /* from NV_PMC_BOOT_0 */ | ||
166 | __u8 revision; /* from NV_PMC_BOOT_0 */ | ||
167 | #define NV_DEVICE_INFO_V0_TNT 0x01 | ||
168 | #define NV_DEVICE_INFO_V0_CELSIUS 0x02 | ||
169 | #define NV_DEVICE_INFO_V0_KELVIN 0x03 | ||
170 | #define NV_DEVICE_INFO_V0_RANKINE 0x04 | ||
171 | #define NV_DEVICE_INFO_V0_CURIE 0x05 | ||
172 | #define NV_DEVICE_INFO_V0_TESLA 0x06 | ||
173 | #define NV_DEVICE_INFO_V0_FERMI 0x07 | ||
174 | #define NV_DEVICE_INFO_V0_KEPLER 0x08 | ||
175 | #define NV_DEVICE_INFO_V0_MAXWELL 0x09 | ||
176 | __u8 family; | ||
177 | __u8 pad06[2]; | ||
178 | __u64 ram_size; | ||
179 | __u64 ram_user; | ||
180 | }; | ||
181 | |||
182 | |||
183 | /******************************************************************************* | ||
184 | * context dma | ||
185 | ******************************************************************************/ | ||
186 | |||
187 | struct nv_dma_v0 { | ||
188 | __u8 version; | ||
189 | #define NV_DMA_V0_TARGET_VM 0x00 | ||
190 | #define NV_DMA_V0_TARGET_VRAM 0x01 | ||
191 | #define NV_DMA_V0_TARGET_PCI 0x02 | ||
192 | #define NV_DMA_V0_TARGET_PCI_US 0x03 | ||
193 | #define NV_DMA_V0_TARGET_AGP 0x04 | ||
194 | __u8 target; | ||
195 | #define NV_DMA_V0_ACCESS_VM 0x00 | ||
196 | #define NV_DMA_V0_ACCESS_RD 0x01 | ||
197 | #define NV_DMA_V0_ACCESS_WR 0x02 | ||
198 | #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) | ||
199 | __u8 access; | ||
200 | __u8 pad03[5]; | ||
201 | __u64 start; | ||
202 | __u64 limit; | ||
203 | /* ... chipset-specific class data */ | ||
204 | }; | ||
205 | |||
206 | struct nv50_dma_v0 { | ||
207 | __u8 version; | ||
208 | #define NV50_DMA_V0_PRIV_VM 0x00 | ||
209 | #define NV50_DMA_V0_PRIV_US 0x01 | ||
210 | #define NV50_DMA_V0_PRIV__S 0x02 | ||
211 | __u8 priv; | ||
212 | #define NV50_DMA_V0_PART_VM 0x00 | ||
213 | #define NV50_DMA_V0_PART_256 0x01 | ||
214 | #define NV50_DMA_V0_PART_1KB 0x02 | ||
215 | __u8 part; | ||
216 | #define NV50_DMA_V0_COMP_NONE 0x00 | ||
217 | #define NV50_DMA_V0_COMP_1 0x01 | ||
218 | #define NV50_DMA_V0_COMP_2 0x02 | ||
219 | #define NV50_DMA_V0_COMP_VM 0x03 | ||
220 | __u8 comp; | ||
221 | #define NV50_DMA_V0_KIND_PITCH 0x00 | ||
222 | #define NV50_DMA_V0_KIND_VM 0x7f | ||
223 | __u8 kind; | ||
224 | __u8 pad05[3]; | ||
225 | }; | ||
226 | |||
227 | struct gf100_dma_v0 { | ||
228 | __u8 version; | ||
229 | #define GF100_DMA_V0_PRIV_VM 0x00 | ||
230 | #define GF100_DMA_V0_PRIV_US 0x01 | ||
231 | #define GF100_DMA_V0_PRIV__S 0x02 | ||
232 | __u8 priv; | ||
233 | #define GF100_DMA_V0_KIND_PITCH 0x00 | ||
234 | #define GF100_DMA_V0_KIND_VM 0xff | ||
235 | __u8 kind; | ||
236 | __u8 pad03[5]; | ||
237 | }; | ||
238 | |||
239 | struct gf110_dma_v0 { | ||
240 | __u8 version; | ||
241 | #define GF110_DMA_V0_PAGE_LP 0x00 | ||
242 | #define GF110_DMA_V0_PAGE_SP 0x01 | ||
243 | __u8 page; | ||
244 | #define GF110_DMA_V0_KIND_PITCH 0x00 | ||
245 | #define GF110_DMA_V0_KIND_VM 0xff | ||
246 | __u8 kind; | ||
247 | __u8 pad03[5]; | ||
248 | }; | ||
249 | |||
250 | |||
251 | /******************************************************************************* | ||
252 | * perfmon | ||
253 | ******************************************************************************/ | ||
254 | |||
255 | struct nvif_perfctr_v0 { | ||
256 | __u8 version; | ||
257 | __u8 pad01[1]; | ||
258 | __u16 logic_op; | ||
259 | __u8 pad04[4]; | ||
260 | char name[4][64]; | ||
261 | }; | ||
262 | |||
263 | #define NVIF_PERFCTR_V0_QUERY 0x00 | ||
264 | #define NVIF_PERFCTR_V0_SAMPLE 0x01 | ||
265 | #define NVIF_PERFCTR_V0_READ 0x02 | ||
266 | |||
267 | struct nvif_perfctr_query_v0 { | ||
268 | __u8 version; | ||
269 | __u8 pad01[3]; | ||
270 | __u32 iter; | ||
271 | char name[64]; | ||
272 | }; | ||
273 | |||
274 | struct nvif_perfctr_sample { | ||
275 | }; | ||
276 | |||
277 | struct nvif_perfctr_read_v0 { | ||
278 | __u8 version; | ||
279 | __u8 pad01[7]; | ||
280 | __u32 ctr; | ||
281 | __u32 clk; | ||
282 | }; | ||
283 | |||
284 | |||
285 | /******************************************************************************* | ||
286 | * device control | ||
287 | ******************************************************************************/ | ||
288 | |||
289 | #define NVIF_CONTROL_PSTATE_INFO 0x00 | ||
290 | #define NVIF_CONTROL_PSTATE_ATTR 0x01 | ||
291 | #define NVIF_CONTROL_PSTATE_USER 0x02 | ||
292 | |||
293 | struct nvif_ustate { | ||
294 | __s8 min; | ||
295 | __s8 max; | ||
296 | }; | ||
297 | |||
298 | struct nvif_control_pstate_info_v0 { | ||
299 | __u8 version; | ||
300 | __u8 count; /* out: number of power states */ | ||
301 | #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) | ||
302 | #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) | ||
303 | struct { | ||
304 | struct nvif_ustate dc; // pwrsrc == 0 | ||
305 | struct nvif_ustate ac; // pwrsrc == 1 | ||
306 | } ustate; /* out: target pstate index */ | ||
307 | __s8 pwrsrc; /* out: current power source */ | ||
308 | #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) | ||
309 | #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) | ||
310 | __s8 pstate; /* out: current pstate index */ | ||
311 | __u8 pad06[2]; | ||
312 | }; | ||
313 | |||
314 | struct nvif_control_pstate_attr_v0 { | ||
315 | __u8 version; | ||
316 | #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) | ||
317 | __s8 state; /* in: index of pstate to query | ||
318 | * out: pstate identifier | ||
319 | */ | ||
320 | __u8 index; /* in: index of attribute to query | ||
321 | * out: index of next attribute, or 0 if no more | ||
322 | */ | ||
323 | __u8 pad03[5]; | ||
324 | __u32 min; | ||
325 | __u32 max; | ||
326 | char name[32]; | ||
327 | char unit[16]; | ||
328 | }; | ||
329 | |||
330 | struct nvif_control_pstate_user_v0 { | ||
331 | __u8 version; | ||
332 | #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) | ||
333 | #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) | ||
334 | struct nvif_ustate ustate; /* in: pstate identifier */ | ||
335 | __s8 pwrsrc; /* in: target power source */ | ||
336 | __u8 pad03[5]; | ||
337 | }; | ||
338 | |||
339 | |||
340 | /******************************************************************************* | ||
341 | * DMA FIFO channels | ||
342 | ******************************************************************************/ | ||
343 | |||
344 | struct nv03_channel_dma_v0 { | ||
345 | __u8 version; | ||
346 | __u8 chid; | ||
347 | __u8 pad02[2]; | ||
348 | __u32 pushbuf; | ||
349 | __u64 offset; | ||
350 | }; | ||
351 | |||
352 | #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 | ||
353 | |||
354 | /******************************************************************************* | ||
355 | * GPFIFO channels | ||
356 | ******************************************************************************/ | ||
357 | |||
358 | struct nv50_channel_gpfifo_v0 { | ||
359 | __u8 version; | ||
360 | __u8 chid; | ||
361 | __u8 pad01[6]; | ||
362 | __u32 pushbuf; | ||
363 | __u32 ilength; | ||
364 | __u64 ioffset; | ||
365 | }; | ||
366 | |||
367 | struct kepler_channel_gpfifo_a_v0 { | ||
368 | __u8 version; | ||
369 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 | ||
370 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 | ||
371 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 | ||
372 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 | ||
373 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 | ||
374 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 | ||
375 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 | ||
376 | __u8 engine; | ||
377 | __u16 chid; | ||
378 | __u8 pad04[4]; | ||
379 | __u32 pushbuf; | ||
380 | __u32 ilength; | ||
381 | __u64 ioffset; | ||
382 | }; | ||
383 | |||
384 | #define CHANNEL_GPFIFO_ERROR_NOTIFIER_EEVENT 0x01 | ||
385 | |||
386 | /******************************************************************************* | ||
387 | * legacy display | ||
388 | ******************************************************************************/ | ||
389 | |||
390 | #define NV04_DISP_NTFY_VBLANK 0x00 | ||
391 | #define NV04_DISP_NTFY_CONN 0x01 | ||
392 | |||
393 | struct nv04_disp_mthd_v0 { | ||
394 | __u8 version; | ||
395 | #define NV04_DISP_SCANOUTPOS 0x00 | ||
396 | __u8 method; | ||
397 | __u8 head; | ||
398 | __u8 pad03[5]; | ||
399 | }; | ||
400 | |||
401 | struct nv04_disp_scanoutpos_v0 { | ||
402 | __u8 version; | ||
403 | __u8 pad01[7]; | ||
404 | __s64 time[2]; | ||
405 | __u16 vblanks; | ||
406 | __u16 vblanke; | ||
407 | __u16 vtotal; | ||
408 | __u16 vline; | ||
409 | __u16 hblanks; | ||
410 | __u16 hblanke; | ||
411 | __u16 htotal; | ||
412 | __u16 hline; | ||
413 | }; | ||
414 | |||
415 | /******************************************************************************* | ||
416 | * display | ||
417 | ******************************************************************************/ | ||
418 | |||
419 | #define NV50_DISP_MTHD 0x00 | ||
420 | |||
421 | struct nv50_disp_mthd_v0 { | ||
422 | __u8 version; | ||
423 | #define NV50_DISP_SCANOUTPOS 0x00 | ||
424 | __u8 method; | ||
425 | __u8 head; | ||
426 | __u8 pad03[5]; | ||
427 | }; | ||
428 | |||
429 | struct nv50_disp_mthd_v1 { | ||
430 | __u8 version; | ||
431 | #define NV50_DISP_MTHD_V1_DAC_PWR 0x10 | ||
432 | #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 | ||
433 | #define NV50_DISP_MTHD_V1_SOR_PWR 0x20 | ||
434 | #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 | ||
435 | #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 | ||
436 | #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 | ||
437 | #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 | ||
438 | #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 | ||
439 | __u8 method; | ||
440 | __u16 hasht; | ||
441 | __u16 hashm; | ||
442 | __u8 pad06[2]; | ||
443 | }; | ||
444 | |||
445 | struct nv50_disp_dac_pwr_v0 { | ||
446 | __u8 version; | ||
447 | __u8 state; | ||
448 | __u8 data; | ||
449 | __u8 vsync; | ||
450 | __u8 hsync; | ||
451 | __u8 pad05[3]; | ||
452 | }; | ||
453 | |||
454 | struct nv50_disp_dac_load_v0 { | ||
455 | __u8 version; | ||
456 | __u8 load; | ||
457 | __u8 pad02[2]; | ||
458 | __u32 data; | ||
459 | }; | ||
460 | |||
461 | struct nv50_disp_sor_pwr_v0 { | ||
462 | __u8 version; | ||
463 | __u8 state; | ||
464 | __u8 pad02[6]; | ||
465 | }; | ||
466 | |||
467 | struct nv50_disp_sor_hda_eld_v0 { | ||
468 | __u8 version; | ||
469 | __u8 pad01[7]; | ||
470 | __u8 data[]; | ||
471 | }; | ||
472 | |||
473 | struct nv50_disp_sor_hdmi_pwr_v0 { | ||
474 | __u8 version; | ||
475 | __u8 state; | ||
476 | __u8 max_ac_packet; | ||
477 | __u8 rekey; | ||
478 | __u8 pad04[4]; | ||
479 | }; | ||
480 | |||
481 | struct nv50_disp_sor_lvds_script_v0 { | ||
482 | __u8 version; | ||
483 | __u8 pad01[1]; | ||
484 | __u16 script; | ||
485 | __u8 pad04[4]; | ||
486 | }; | ||
487 | |||
488 | struct nv50_disp_sor_dp_pwr_v0 { | ||
489 | __u8 version; | ||
490 | __u8 state; | ||
491 | __u8 pad02[6]; | ||
492 | }; | ||
493 | |||
494 | struct nv50_disp_pior_pwr_v0 { | ||
495 | __u8 version; | ||
496 | __u8 state; | ||
497 | __u8 type; | ||
498 | __u8 pad03[5]; | ||
499 | }; | ||
500 | |||
501 | /* core */ | ||
502 | struct nv50_disp_core_channel_dma_v0 { | ||
503 | __u8 version; | ||
504 | __u8 pad01[3]; | ||
505 | __u32 pushbuf; | ||
506 | }; | ||
507 | |||
508 | #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 | ||
509 | |||
510 | /* cursor immediate */ | ||
511 | struct nv50_disp_cursor_v0 { | ||
512 | __u8 version; | ||
513 | __u8 head; | ||
514 | __u8 pad02[6]; | ||
515 | }; | ||
516 | |||
517 | #define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 | ||
518 | |||
519 | /* base */ | ||
520 | struct nv50_disp_base_channel_dma_v0 { | ||
521 | __u8 version; | ||
522 | __u8 pad01[2]; | ||
523 | __u8 head; | ||
524 | __u32 pushbuf; | ||
525 | }; | ||
526 | |||
527 | #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 | ||
528 | |||
529 | /* overlay */ | ||
530 | struct nv50_disp_overlay_channel_dma_v0 { | ||
531 | __u8 version; | ||
532 | __u8 pad01[2]; | ||
533 | __u8 head; | ||
534 | __u32 pushbuf; | ||
535 | }; | ||
536 | |||
537 | #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 | ||
538 | |||
539 | /* overlay immediate */ | ||
540 | struct nv50_disp_overlay_v0 { | ||
541 | __u8 version; | ||
542 | __u8 head; | ||
543 | __u8 pad02[6]; | ||
544 | }; | ||
545 | |||
546 | #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 | ||
547 | |||
548 | /******************************************************************************* | ||
549 | * fermi | ||
550 | ******************************************************************************/ | ||
551 | |||
552 | #define FERMI_A_ZBC_COLOR 0x00 | ||
553 | #define FERMI_A_ZBC_DEPTH 0x01 | ||
554 | |||
555 | struct fermi_a_zbc_color_v0 { | ||
556 | __u8 version; | ||
557 | #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 | ||
558 | #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 | ||
559 | #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 | ||
560 | #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 | ||
561 | #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c | ||
562 | #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 | ||
563 | #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 | ||
564 | #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 | ||
565 | #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 | ||
566 | #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c | ||
567 | #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 | ||
568 | #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 | ||
569 | #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 | ||
570 | #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c | ||
571 | #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 | ||
572 | #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 | ||
573 | #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 | ||
574 | #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c | ||
575 | #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 | ||
576 | __u8 format; | ||
577 | __u8 index; | ||
578 | __u8 pad03[5]; | ||
579 | __u32 ds[4]; | ||
580 | __u32 l2[4]; | ||
581 | }; | ||
582 | |||
583 | struct fermi_a_zbc_depth_v0 { | ||
584 | __u8 version; | ||
585 | #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 | ||
586 | __u8 format; | ||
587 | __u8 index; | ||
588 | __u8 pad03[5]; | ||
589 | __u32 ds; | ||
590 | __u32 l2; | ||
591 | }; | ||
592 | |||
593 | #define KEPLER_SET_CHANNEL_PRIORITY 0x00 | ||
594 | #define KEPLER_SET_CHANNEL_TIMEOUT 0x01 | ||
595 | |||
596 | struct kepler_set_channel_priority_v0 { | ||
597 | __u8 version; | ||
598 | #define KEPLER_SET_CHANNEL_PRIORITY_LOW 0x00 | ||
599 | #define KEPLER_SET_CHANNEL_PRIORITY_MEDIUM 0x01 | ||
600 | #define KEPLER_SET_CHANNEL_PRIORITY_HIGH 0x02 | ||
601 | __u8 priority; | ||
602 | __u8 pad03[6]; | ||
603 | }; | ||
604 | |||
605 | struct kepler_set_channel_timeout_v0 { | ||
606 | __u8 version; | ||
607 | __u8 pad03[3]; | ||
608 | __u32 timeout_ms; | ||
609 | }; | ||
610 | |||
611 | #endif | ||
diff --git a/include/drm/nouveau_ioctl.h b/include/drm/nouveau_ioctl.h new file mode 100644 index 00000000..4cd8e323 --- /dev/null +++ b/include/drm/nouveau_ioctl.h | |||
@@ -0,0 +1,128 @@ | |||
1 | #ifndef __NVIF_IOCTL_H__ | ||
2 | #define __NVIF_IOCTL_H__ | ||
3 | |||
4 | struct nvif_ioctl_v0 { | ||
5 | __u8 version; | ||
6 | #define NVIF_IOCTL_V0_OWNER_NVIF 0x00 | ||
7 | #define NVIF_IOCTL_V0_OWNER_ANY 0xff | ||
8 | __u8 owner; | ||
9 | #define NVIF_IOCTL_V0_NOP 0x00 | ||
10 | #define NVIF_IOCTL_V0_SCLASS 0x01 | ||
11 | #define NVIF_IOCTL_V0_NEW 0x02 | ||
12 | #define NVIF_IOCTL_V0_DEL 0x03 | ||
13 | #define NVIF_IOCTL_V0_MTHD 0x04 | ||
14 | #define NVIF_IOCTL_V0_RD 0x05 | ||
15 | #define NVIF_IOCTL_V0_WR 0x06 | ||
16 | #define NVIF_IOCTL_V0_MAP 0x07 | ||
17 | #define NVIF_IOCTL_V0_UNMAP 0x08 | ||
18 | #define NVIF_IOCTL_V0_NTFY_NEW 0x09 | ||
19 | #define NVIF_IOCTL_V0_NTFY_DEL 0x0a | ||
20 | #define NVIF_IOCTL_V0_NTFY_GET 0x0b | ||
21 | #define NVIF_IOCTL_V0_NTFY_PUT 0x0c | ||
22 | __u8 type; | ||
23 | __u8 path_nr; | ||
24 | #define NVIF_IOCTL_V0_ROUTE_NVIF 0x00 | ||
25 | #define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff | ||
26 | __u8 pad04[3]; | ||
27 | __u8 route; | ||
28 | __u64 token; | ||
29 | __u32 path[8]; /* in reverse */ | ||
30 | __u8 data[]; /* ioctl data (below) */ | ||
31 | }; | ||
32 | |||
33 | struct nvif_ioctl_nop { | ||
34 | }; | ||
35 | |||
36 | struct nvif_ioctl_sclass_v0 { | ||
37 | /* nvif_ioctl ... */ | ||
38 | __u8 version; | ||
39 | __u8 count; | ||
40 | __u8 pad02[6]; | ||
41 | __u32 oclass[]; | ||
42 | }; | ||
43 | |||
44 | struct nvif_ioctl_new_v0 { | ||
45 | /* nvif_ioctl ... */ | ||
46 | __u8 version; | ||
47 | __u8 pad01[6]; | ||
48 | __u8 route; | ||
49 | __u64 token; | ||
50 | __u32 handle; | ||
51 | /* these class numbers are made up by us, and not nvidia-assigned */ | ||
52 | #define NVIF_IOCTL_NEW_V0_PERFCTR 0x0000ffff | ||
53 | #define NVIF_IOCTL_NEW_V0_CONTROL 0x0000fffe | ||
54 | __u32 oclass; | ||
55 | __u8 data[]; /* class data (class.h) */ | ||
56 | }; | ||
57 | |||
58 | struct nvif_ioctl_del { | ||
59 | }; | ||
60 | |||
61 | struct nvif_ioctl_rd_v0 { | ||
62 | /* nvif_ioctl ... */ | ||
63 | __u8 version; | ||
64 | __u8 size; | ||
65 | __u8 pad02[2]; | ||
66 | __u32 data; | ||
67 | __u64 addr; | ||
68 | }; | ||
69 | |||
70 | struct nvif_ioctl_wr_v0 { | ||
71 | /* nvif_ioctl ... */ | ||
72 | __u8 version; | ||
73 | __u8 size; | ||
74 | __u8 pad02[2]; | ||
75 | __u32 data; | ||
76 | __u64 addr; | ||
77 | }; | ||
78 | |||
79 | struct nvif_ioctl_map_v0 { | ||
80 | /* nvif_ioctl ... */ | ||
81 | __u8 version; | ||
82 | __u8 pad01[3]; | ||
83 | __u32 length; | ||
84 | __u64 handle; | ||
85 | }; | ||
86 | |||
87 | struct nvif_ioctl_unmap { | ||
88 | }; | ||
89 | |||
90 | struct nvif_ioctl_ntfy_new_v0 { | ||
91 | /* nvif_ioctl ... */ | ||
92 | __u8 version; | ||
93 | __u8 event; | ||
94 | __u8 index; | ||
95 | __u8 pad03[5]; | ||
96 | __u8 data[]; /* event request data (event.h) */ | ||
97 | }; | ||
98 | |||
99 | struct nvif_ioctl_ntfy_del_v0 { | ||
100 | /* nvif_ioctl ... */ | ||
101 | __u8 version; | ||
102 | __u8 index; | ||
103 | __u8 pad02[6]; | ||
104 | }; | ||
105 | |||
106 | struct nvif_ioctl_ntfy_get_v0 { | ||
107 | /* nvif_ioctl ... */ | ||
108 | __u8 version; | ||
109 | __u8 index; | ||
110 | __u8 pad02[6]; | ||
111 | }; | ||
112 | |||
113 | struct nvif_ioctl_ntfy_put_v0 { | ||
114 | /* nvif_ioctl ... */ | ||
115 | __u8 version; | ||
116 | __u8 index; | ||
117 | __u8 pad02[6]; | ||
118 | }; | ||
119 | |||
120 | struct nvif_ioctl_mthd_v0 { | ||
121 | /* nvif_ioctl ... */ | ||
122 | __u8 version; | ||
123 | __u8 method; | ||
124 | __u8 pad02[6]; | ||
125 | __u8 data[]; /* method data (class.h) */ | ||
126 | }; | ||
127 | |||
128 | #endif | ||