diff options
-rw-r--r-- | tests/amdgpu/basic_tests.c | 66 |
1 files changed, 65 insertions, 1 deletions
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 635cd23a..67a8d3c6 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c | |||
@@ -153,7 +153,7 @@ static void amdgpu_memory_alloc(void) | |||
153 | CU_ASSERT_EQUAL(r, 0); | 153 | CU_ASSERT_EQUAL(r, 0); |
154 | } | 154 | } |
155 | 155 | ||
156 | static void amdgpu_command_submission_gfx(void) | 156 | static void amdgpu_command_submission_gfx_separate_ibs(void) |
157 | { | 157 | { |
158 | amdgpu_context_handle context_handle; | 158 | amdgpu_context_handle context_handle; |
159 | struct amdgpu_cs_ib_alloc_result ib_result = {0}; | 159 | struct amdgpu_cs_ib_alloc_result ib_result = {0}; |
@@ -214,6 +214,70 @@ static void amdgpu_command_submission_gfx(void) | |||
214 | CU_ASSERT_EQUAL(r, 0); | 214 | CU_ASSERT_EQUAL(r, 0); |
215 | } | 215 | } |
216 | 216 | ||
217 | static void amdgpu_command_submission_gfx_shared_ib(void) | ||
218 | { | ||
219 | amdgpu_context_handle context_handle; | ||
220 | struct amdgpu_cs_ib_alloc_result ib_result = {0}; | ||
221 | struct amdgpu_cs_request ibs_request = {0}; | ||
222 | struct amdgpu_cs_ib_info ib_info[2]; | ||
223 | struct amdgpu_cs_query_fence fence_status = {0}; | ||
224 | uint32_t *ptr; | ||
225 | uint32_t expired; | ||
226 | int r; | ||
227 | |||
228 | r = amdgpu_cs_ctx_create(device_handle, &context_handle); | ||
229 | CU_ASSERT_EQUAL(r, 0); | ||
230 | |||
231 | r = amdgpu_cs_alloc_ib(context_handle, | ||
232 | amdgpu_cs_ib_size_4K, &ib_result); | ||
233 | CU_ASSERT_EQUAL(r, 0); | ||
234 | |||
235 | memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); | ||
236 | |||
237 | /* IT_SET_CE_DE_COUNTERS */ | ||
238 | ptr = ib_result.cpu; | ||
239 | ptr[0] = 0xc0008900; | ||
240 | ptr[1] = 0; | ||
241 | ptr[2] = 0xc0008400; | ||
242 | ptr[3] = 1; | ||
243 | ib_info[0].ib_handle = ib_result.handle; | ||
244 | ib_info[0].size = 4; | ||
245 | ib_info[0].flags = AMDGPU_IB_FLAG_CE; | ||
246 | |||
247 | ptr = (uint32_t *)ib_result.cpu + 4; | ||
248 | ptr[0] = 0xc0008600; | ||
249 | ptr[1] = 0x00000001; | ||
250 | ib_info[1].ib_handle = ib_result.handle; | ||
251 | ib_info[1].size = 2; | ||
252 | ib_info[1].offset_dw = 4; | ||
253 | |||
254 | ibs_request.ip_type = AMDGPU_HW_IP_GFX; | ||
255 | ibs_request.number_of_ibs = 2; | ||
256 | ibs_request.ibs = ib_info; | ||
257 | |||
258 | r = amdgpu_cs_submit(context_handle, 0, | ||
259 | &ibs_request, 1, &fence_status.fence); | ||
260 | CU_ASSERT_EQUAL(r, 0); | ||
261 | |||
262 | fence_status.context = context_handle; | ||
263 | fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE; | ||
264 | fence_status.ip_type = AMDGPU_HW_IP_GFX; | ||
265 | |||
266 | r = amdgpu_cs_query_fence_status(&fence_status, &expired); | ||
267 | CU_ASSERT_EQUAL(r, 0); | ||
268 | |||
269 | r = amdgpu_cs_ctx_free(context_handle); | ||
270 | CU_ASSERT_EQUAL(r, 0); | ||
271 | } | ||
272 | |||
273 | static void amdgpu_command_submission_gfx(void) | ||
274 | { | ||
275 | /* separate IB buffers for multi-IB submission */ | ||
276 | amdgpu_command_submission_gfx_separate_ibs(); | ||
277 | /* shared IB buffer for multi-IB submission */ | ||
278 | amdgpu_command_submission_gfx_shared_ib(); | ||
279 | } | ||
280 | |||
217 | static void amdgpu_command_submission_compute(void) | 281 | static void amdgpu_command_submission_compute(void) |
218 | { | 282 | { |
219 | amdgpu_context_handle context_handle; | 283 | amdgpu_context_handle context_handle; |