diff options
Diffstat (limited to 'amdgpu/amdgpu_bo.c')
-rw-r--r-- | amdgpu/amdgpu_bo.c | 97 |
1 files changed, 57 insertions, 40 deletions
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index d30fd1e7..9e37b149 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c | |||
@@ -22,10 +22,6 @@ | |||
22 | * | 22 | * |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifdef HAVE_CONFIG_H | ||
26 | #include "config.h" | ||
27 | #endif | ||
28 | |||
29 | #include <stdlib.h> | 25 | #include <stdlib.h> |
30 | #include <stdio.h> | 26 | #include <stdio.h> |
31 | #include <stdint.h> | 27 | #include <stdint.h> |
@@ -53,29 +49,6 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev, | |||
53 | drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args); | 49 | drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args); |
54 | } | 50 | } |
55 | 51 | ||
56 | drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo) | ||
57 | { | ||
58 | /* Remove the buffer from the hash tables. */ | ||
59 | pthread_mutex_lock(&bo->dev->bo_table_mutex); | ||
60 | util_hash_table_remove(bo->dev->bo_handles, | ||
61 | (void*)(uintptr_t)bo->handle); | ||
62 | if (bo->flink_name) { | ||
63 | util_hash_table_remove(bo->dev->bo_flink_names, | ||
64 | (void*)(uintptr_t)bo->flink_name); | ||
65 | } | ||
66 | pthread_mutex_unlock(&bo->dev->bo_table_mutex); | ||
67 | |||
68 | /* Release CPU access. */ | ||
69 | if (bo->cpu_map_count > 0) { | ||
70 | bo->cpu_map_count = 1; | ||
71 | amdgpu_bo_cpu_unmap(bo); | ||
72 | } | ||
73 | |||
74 | amdgpu_close_kms_handle(bo->dev, bo->handle); | ||
75 | pthread_mutex_destroy(&bo->cpu_access_mutex); | ||
76 | free(bo); | ||
77 | } | ||
78 | |||
79 | int amdgpu_bo_alloc(amdgpu_device_handle dev, | 52 | int amdgpu_bo_alloc(amdgpu_device_handle dev, |
80 | struct amdgpu_bo_alloc_request *alloc_buffer, | 53 | struct amdgpu_bo_alloc_request *alloc_buffer, |
81 | amdgpu_bo_handle *buf_handle) | 54 | amdgpu_bo_handle *buf_handle) |
@@ -273,8 +246,9 @@ int amdgpu_bo_export(amdgpu_bo_handle bo, | |||
273 | 246 | ||
274 | case amdgpu_bo_handle_type_dma_buf_fd: | 247 | case amdgpu_bo_handle_type_dma_buf_fd: |
275 | amdgpu_add_handle_to_table(bo); | 248 | amdgpu_add_handle_to_table(bo); |
276 | return drmPrimeHandleToFD(bo->dev->fd, bo->handle, DRM_CLOEXEC, | 249 | return drmPrimeHandleToFD(bo->dev->fd, bo->handle, |
277 | (int*)shared_handle); | 250 | DRM_CLOEXEC | DRM_RDWR, |
251 | (int*)shared_handle); | ||
278 | } | 252 | } |
279 | return -EINVAL; | 253 | return -EINVAL; |
280 | } | 254 | } |
@@ -302,6 +276,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev, | |||
302 | /* Get a KMS handle. */ | 276 | /* Get a KMS handle. */ |
303 | r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle); | 277 | r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle); |
304 | if (r) { | 278 | if (r) { |
279 | pthread_mutex_unlock(&dev->bo_table_mutex); | ||
305 | return r; | 280 | return r; |
306 | } | 281 | } |
307 | 282 | ||
@@ -341,10 +316,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev, | |||
341 | } | 316 | } |
342 | 317 | ||
343 | if (bo) { | 318 | if (bo) { |
344 | pthread_mutex_unlock(&dev->bo_table_mutex); | ||
345 | |||
346 | /* The buffer already exists, just bump the refcount. */ | 319 | /* The buffer already exists, just bump the refcount. */ |
347 | atomic_inc(&bo->refcount); | 320 | atomic_inc(&bo->refcount); |
321 | pthread_mutex_unlock(&dev->bo_table_mutex); | ||
348 | 322 | ||
349 | output->buf_handle = bo; | 323 | output->buf_handle = bo; |
350 | output->alloc_size = bo->alloc_size; | 324 | output->alloc_size = bo->alloc_size; |
@@ -419,8 +393,35 @@ int amdgpu_bo_import(amdgpu_device_handle dev, | |||
419 | 393 | ||
420 | int amdgpu_bo_free(amdgpu_bo_handle buf_handle) | 394 | int amdgpu_bo_free(amdgpu_bo_handle buf_handle) |
421 | { | 395 | { |
422 | /* Just drop the reference. */ | 396 | struct amdgpu_device *dev; |
423 | amdgpu_bo_reference(&buf_handle, NULL); | 397 | struct amdgpu_bo *bo = buf_handle; |
398 | |||
399 | assert(bo != NULL); | ||
400 | dev = bo->dev; | ||
401 | pthread_mutex_lock(&dev->bo_table_mutex); | ||
402 | |||
403 | if (update_references(&bo->refcount, NULL)) { | ||
404 | /* Remove the buffer from the hash tables. */ | ||
405 | util_hash_table_remove(dev->bo_handles, | ||
406 | (void*)(uintptr_t)bo->handle); | ||
407 | |||
408 | if (bo->flink_name) { | ||
409 | util_hash_table_remove(dev->bo_flink_names, | ||
410 | (void*)(uintptr_t)bo->flink_name); | ||
411 | } | ||
412 | |||
413 | /* Release CPU access. */ | ||
414 | if (bo->cpu_map_count > 0) { | ||
415 | bo->cpu_map_count = 1; | ||
416 | amdgpu_bo_cpu_unmap(bo); | ||
417 | } | ||
418 | |||
419 | amdgpu_close_kms_handle(dev, bo->handle); | ||
420 | pthread_mutex_destroy(&bo->cpu_access_mutex); | ||
421 | free(bo); | ||
422 | } | ||
423 | |||
424 | pthread_mutex_unlock(&dev->bo_table_mutex); | ||
424 | return 0; | 425 | return 0; |
425 | } | 426 | } |
426 | 427 | ||
@@ -652,7 +653,7 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, | |||
652 | return -EINVAL; | 653 | return -EINVAL; |
653 | 654 | ||
654 | list = malloc(number_of_resources * sizeof(struct drm_amdgpu_bo_list_entry)); | 655 | list = malloc(number_of_resources * sizeof(struct drm_amdgpu_bo_list_entry)); |
655 | if (list == NULL) | 656 | if (!list) |
656 | return -ENOMEM; | 657 | return -ENOMEM; |
657 | 658 | ||
658 | args.in.operation = AMDGPU_BO_LIST_OP_UPDATE; | 659 | args.in.operation = AMDGPU_BO_LIST_OP_UPDATE; |
@@ -683,21 +684,37 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, | |||
683 | uint32_t ops) | 684 | uint32_t ops) |
684 | { | 685 | { |
685 | amdgpu_device_handle dev = bo->dev; | 686 | amdgpu_device_handle dev = bo->dev; |
687 | |||
688 | size = ALIGN(size, getpagesize()); | ||
689 | |||
690 | return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr, | ||
691 | AMDGPU_VM_PAGE_READABLE | | ||
692 | AMDGPU_VM_PAGE_WRITEABLE | | ||
693 | AMDGPU_VM_PAGE_EXECUTABLE, ops); | ||
694 | } | ||
695 | |||
696 | int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, | ||
697 | amdgpu_bo_handle bo, | ||
698 | uint64_t offset, | ||
699 | uint64_t size, | ||
700 | uint64_t addr, | ||
701 | uint64_t flags, | ||
702 | uint32_t ops) | ||
703 | { | ||
686 | struct drm_amdgpu_gem_va va; | 704 | struct drm_amdgpu_gem_va va; |
687 | int r; | 705 | int r; |
688 | 706 | ||
689 | if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP) | 707 | if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP && |
708 | ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR) | ||
690 | return -EINVAL; | 709 | return -EINVAL; |
691 | 710 | ||
692 | memset(&va, 0, sizeof(va)); | 711 | memset(&va, 0, sizeof(va)); |
693 | va.handle = bo->handle; | 712 | va.handle = bo ? bo->handle : 0; |
694 | va.operation = ops; | 713 | va.operation = ops; |
695 | va.flags = AMDGPU_VM_PAGE_READABLE | | 714 | va.flags = flags; |
696 | AMDGPU_VM_PAGE_WRITEABLE | | ||
697 | AMDGPU_VM_PAGE_EXECUTABLE; | ||
698 | va.va_address = addr; | 715 | va.va_address = addr; |
699 | va.offset_in_bo = offset; | 716 | va.offset_in_bo = offset; |
700 | va.map_size = ALIGN(size, getpagesize()); | 717 | va.map_size = size; |
701 | 718 | ||
702 | r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va)); | 719 | r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va)); |
703 | 720 | ||