1 files changed, 55 insertions, 39 deletions

diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 66c7e0e1..b68e1c4f 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -22,10 +22,6 @@
  *
  */
 
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
 #include <errno.h>
 #include <string.h>
 
@@ -169,53 +165,57 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
         dev->info.vce_harvest_config = dev->dev_info.vce_harvest_config;
         dev->info.pci_rev_id = dev->dev_info.pci_rev;
 
-        for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
-                unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
-                                    (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
-                                     AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
+        if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+                for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
+                        unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
+                                            (AMDGPU_INFO_MMR_SH_INDEX_MASK <<
+                                             AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
 
-                r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
-                                             &dev->info.backend_disable[i]);
-                if (r)
-                        return r;
-                /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
-                dev->info.backend_disable[i] =
-                        (dev->info.backend_disable[i] >> 16) & 0xff;
-
-                r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
-                                             &dev->info.pa_sc_raster_cfg[i]);
-                if (r)
-                        return r;
+                        r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
+                                                     &dev->info.backend_disable[i]);
+                        if (r)
+                                return r;
+                        /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
+                        dev->info.backend_disable[i] =
+                                (dev->info.backend_disable[i] >> 16) & 0xff;
 
-                if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
-                        r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
-                                             &dev->info.pa_sc_raster_cfg1[i]);
+                        r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
+                                                     &dev->info.pa_sc_raster_cfg[i]);
                         if (r)
                                 return r;
+
+                        if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+                                r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
+                                                     &dev->info.pa_sc_raster_cfg1[i]);
+                                if (r)
+                                        return r;
+                        }
                 }
         }
 
-        r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
-                                     dev->info.gb_tile_mode);
+        r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
+                                             &dev->info.gb_addr_cfg);
         if (r)
                 return r;
 
-        if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
-                r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
-                                             dev->info.gb_macro_tile_mode);
+        if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+                r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
+                                             dev->info.gb_tile_mode);
                 if (r)
                         return r;
-        }
 
-        r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
-                                     &dev->info.gb_addr_cfg);
-        if (r)
-                return r;
+                if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+                        r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
+                                                     dev->info.gb_macro_tile_mode);
+                        if (r)
+                                return r;
+                }
 
-        r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
-                                     &dev->info.mc_arb_ramcfg);
-        if (r)
-                return r;
+                r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
+                                             &dev->info.mc_arb_ramcfg);
+                if (r)
+                        return r;
+        }
 
         dev->info.cu_active_number = dev->dev_info.cu_active_number;
         dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
@@ -230,8 +230,9 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
                         struct amdgpu_gpu_info *info)
 {
-        if ((dev == NULL) || (info == NULL))
+        if (!dev || !info)
                 return -EINVAL;
+
         /* Get ASIC info*/
         *info = dev->info;
 
@@ -296,7 +297,7 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev,
         struct drm_amdgpu_info_gds gds_config = {};
         int r;
 
-        if (gds_info == NULL)
+        if (!gds_info)
                 return -EINVAL;
 
         r = amdgpu_query_info(dev, AMDGPU_INFO_GDS_CONFIG,
@@ -314,3 +315,18 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev,
 
         return 0;
 }
+
+int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
+                             unsigned size, void *value)
+{
+        struct drm_amdgpu_info request;
+
+        memset(&request, 0, sizeof(request));
+        request.return_pointer = (uintptr_t)value;
+        request.return_size = size;
+        request.query = AMDGPU_INFO_SENSOR;
+        request.sensor_info.type = sensor_type;
+
+        return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
+                               sizeof(struct drm_amdgpu_info));
+}