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Diffstat (limited to 'include/drm/amdgpu_drm.h')
-rw-r--r--include/drm/amdgpu_drm.h592
1 files changed, 442 insertions, 150 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d8f24976..c363b67f 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -50,6 +50,10 @@ extern "C" {
50#define DRM_AMDGPU_WAIT_CS 0x09 50#define DRM_AMDGPU_WAIT_CS 0x09
51#define DRM_AMDGPU_GEM_OP 0x10 51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11 52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13
55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56#define DRM_AMDGPU_SCHED 0x15
53 57
54#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 58#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
55#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 59#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -63,6 +67,10 @@ extern "C" {
63#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 67#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
64#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 68#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
65#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 69#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
66 74
67#define AMDGPU_GEM_DOMAIN_CPU 0x1 75#define AMDGPU_GEM_DOMAIN_CPU 0x1
68#define AMDGPU_GEM_DOMAIN_GTT 0x2 76#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -79,22 +87,30 @@ extern "C" {
79#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 87#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
80/* Flag that the memory should be in VRAM and cleared */ 88/* Flag that the memory should be in VRAM and cleared */
81#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 89#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
90/* Flag that create shadow bo(GTT) while allocating vram bo */
91#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
92/* Flag that allocating the BO should use linear VRAM */
93#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
94/* Flag that BO is always valid in this VM */
95#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
96/* Flag that BO sharing will be explicitly synchronized */
97#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
82 98
83struct drm_amdgpu_gem_create_in { 99struct drm_amdgpu_gem_create_in {
84 /** the requested memory size */ 100 /** the requested memory size */
85 uint64_t bo_size; 101 __u64 bo_size;
86 /** physical start_addr alignment in bytes for some HW requirements */ 102 /** physical start_addr alignment in bytes for some HW requirements */
87 uint64_t alignment; 103 __u64 alignment;
88 /** the requested memory domains */ 104 /** the requested memory domains */
89 uint64_t domains; 105 __u64 domains;
90 /** allocation flags */ 106 /** allocation flags */
91 uint64_t domain_flags; 107 __u64 domain_flags;
92}; 108};
93 109
94struct drm_amdgpu_gem_create_out { 110struct drm_amdgpu_gem_create_out {
95 /** returned GEM object handle */ 111 /** returned GEM object handle */
96 uint32_t handle; 112 __u32 handle;
97 uint32_t _pad; 113 __u32 _pad;
98}; 114};
99 115
100union drm_amdgpu_gem_create { 116union drm_amdgpu_gem_create {
@@ -111,28 +127,28 @@ union drm_amdgpu_gem_create {
111 127
112struct drm_amdgpu_bo_list_in { 128struct drm_amdgpu_bo_list_in {
113 /** Type of operation */ 129 /** Type of operation */
114 uint32_t operation; 130 __u32 operation;
115 /** Handle of list or 0 if we want to create one */ 131 /** Handle of list or 0 if we want to create one */
116 uint32_t list_handle; 132 __u32 list_handle;
117 /** Number of BOs in list */ 133 /** Number of BOs in list */
118 uint32_t bo_number; 134 __u32 bo_number;
119 /** Size of each element describing BO */ 135 /** Size of each element describing BO */
120 uint32_t bo_info_size; 136 __u32 bo_info_size;
121 /** Pointer to array describing BOs */ 137 /** Pointer to array describing BOs */
122 uint64_t bo_info_ptr; 138 __u64 bo_info_ptr;
123}; 139};
124 140
125struct drm_amdgpu_bo_list_entry { 141struct drm_amdgpu_bo_list_entry {
126 /** Handle of BO */ 142 /** Handle of BO */
127 uint32_t bo_handle; 143 __u32 bo_handle;
128 /** New (if specified) BO priority to be used during migration */ 144 /** New (if specified) BO priority to be used during migration */
129 uint32_t bo_priority; 145 __u32 bo_priority;
130}; 146};
131 147
132struct drm_amdgpu_bo_list_out { 148struct drm_amdgpu_bo_list_out {
133 /** Handle of resource list */ 149 /** Handle of resource list */
134 uint32_t list_handle; 150 __u32 list_handle;
135 uint32_t _pad; 151 __u32 _pad;
136}; 152};
137 153
138union drm_amdgpu_bo_list { 154union drm_amdgpu_bo_list {
@@ -144,6 +160,7 @@ union drm_amdgpu_bo_list {
144#define AMDGPU_CTX_OP_ALLOC_CTX 1 160#define AMDGPU_CTX_OP_ALLOC_CTX 1
145#define AMDGPU_CTX_OP_FREE_CTX 2 161#define AMDGPU_CTX_OP_FREE_CTX 2
146#define AMDGPU_CTX_OP_QUERY_STATE 3 162#define AMDGPU_CTX_OP_QUERY_STATE 3
163#define AMDGPU_CTX_OP_QUERY_STATE2 4
147 164
148/* GPU reset status */ 165/* GPU reset status */
149#define AMDGPU_CTX_NO_RESET 0 166#define AMDGPU_CTX_NO_RESET 0
@@ -154,28 +171,44 @@ union drm_amdgpu_bo_list {
154/* unknown cause */ 171/* unknown cause */
155#define AMDGPU_CTX_UNKNOWN_RESET 3 172#define AMDGPU_CTX_UNKNOWN_RESET 3
156 173
174/* indicate gpu reset occured after ctx created */
175#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
176/* indicate vram lost occured after ctx created */
177#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
178/* indicate some job from this context once cause gpu hang */
179#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
180
181/* Context priority level */
182#define AMDGPU_CTX_PRIORITY_UNSET -2048
183#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
184#define AMDGPU_CTX_PRIORITY_LOW -512
185#define AMDGPU_CTX_PRIORITY_NORMAL 0
186/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
187#define AMDGPU_CTX_PRIORITY_HIGH 512
188#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
189
157struct drm_amdgpu_ctx_in { 190struct drm_amdgpu_ctx_in {
158 /** AMDGPU_CTX_OP_* */ 191 /** AMDGPU_CTX_OP_* */
159 uint32_t op; 192 __u32 op;
160 /** For future use, no flags defined so far */ 193 /** For future use, no flags defined so far */
161 uint32_t flags; 194 __u32 flags;
162 uint32_t ctx_id; 195 __u32 ctx_id;
163 uint32_t _pad; 196 __s32 priority;
164}; 197};
165 198
166union drm_amdgpu_ctx_out { 199union drm_amdgpu_ctx_out {
167 struct { 200 struct {
168 uint32_t ctx_id; 201 __u32 ctx_id;
169 uint32_t _pad; 202 __u32 _pad;
170 } alloc; 203 } alloc;
171 204
172 struct { 205 struct {
173 /** For future use, no flags defined so far */ 206 /** For future use, no flags defined so far */
174 uint64_t flags; 207 __u64 flags;
175 /** Number of resets caused by this context so far. */ 208 /** Number of resets caused by this context so far. */
176 uint32_t hangs; 209 __u32 hangs;
177 /** Reset status since the last call of the ioctl. */ 210 /** Reset status since the last call of the ioctl. */
178 uint32_t reset_status; 211 __u32 reset_status;
179 } state; 212 } state;
180}; 213};
181 214
@@ -184,6 +217,41 @@ union drm_amdgpu_ctx {
184 union drm_amdgpu_ctx_out out; 217 union drm_amdgpu_ctx_out out;
185}; 218};
186 219
220/* vm ioctl */
221#define AMDGPU_VM_OP_RESERVE_VMID 1
222#define AMDGPU_VM_OP_UNRESERVE_VMID 2
223
224struct drm_amdgpu_vm_in {
225 /** AMDGPU_VM_OP_* */
226 __u32 op;
227 __u32 flags;
228};
229
230struct drm_amdgpu_vm_out {
231 /** For future use, no flags defined so far */
232 __u64 flags;
233};
234
235union drm_amdgpu_vm {
236 struct drm_amdgpu_vm_in in;
237 struct drm_amdgpu_vm_out out;
238};
239
240/* sched ioctl */
241#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
242
243struct drm_amdgpu_sched_in {
244 /* AMDGPU_SCHED_OP_* */
245 __u32 op;
246 __u32 fd;
247 __s32 priority;
248 __u32 flags;
249};
250
251union drm_amdgpu_sched {
252 struct drm_amdgpu_sched_in in;
253};
254
187/* 255/*
188 * This is not a reliable API and you should expect it to fail for any 256 * This is not a reliable API and you should expect it to fail for any
189 * number of reasons and have fallback path that do not use userptr to 257 * number of reasons and have fallback path that do not use userptr to
@@ -195,14 +263,15 @@ union drm_amdgpu_ctx {
195#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 263#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
196 264
197struct drm_amdgpu_gem_userptr { 265struct drm_amdgpu_gem_userptr {
198 uint64_t addr; 266 __u64 addr;
199 uint64_t size; 267 __u64 size;
200 /* AMDGPU_GEM_USERPTR_* */ 268 /* AMDGPU_GEM_USERPTR_* */
201 uint32_t flags; 269 __u32 flags;
202 /* Resulting GEM handle */ 270 /* Resulting GEM handle */
203 uint32_t handle; 271 __u32 handle;
204}; 272};
205 273
274/* SI-CI-VI: */
206/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 275/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
207#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 276#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
208#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 277#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
@@ -221,10 +290,15 @@ struct drm_amdgpu_gem_userptr {
221#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 290#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
222#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 291#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
223 292
293/* GFX9 and later: */
294#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
295#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
296
297/* Set/Get helpers for tiling flags. */
224#define AMDGPU_TILING_SET(field, value) \ 298#define AMDGPU_TILING_SET(field, value) \
225 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 299 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
226#define AMDGPU_TILING_GET(value, field) \ 300#define AMDGPU_TILING_GET(value, field) \
227 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 301 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
228 302
229#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 303#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
230#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 304#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
@@ -232,28 +306,28 @@ struct drm_amdgpu_gem_userptr {
232/** The same structure is shared for input/output */ 306/** The same structure is shared for input/output */
233struct drm_amdgpu_gem_metadata { 307struct drm_amdgpu_gem_metadata {
234 /** GEM Object handle */ 308 /** GEM Object handle */
235 uint32_t handle; 309 __u32 handle;
236 /** Do we want get or set metadata */ 310 /** Do we want get or set metadata */
237 uint32_t op; 311 __u32 op;
238 struct { 312 struct {
239 /** For future use, no flags defined so far */ 313 /** For future use, no flags defined so far */
240 uint64_t flags; 314 __u64 flags;
241 /** family specific tiling info */ 315 /** family specific tiling info */
242 uint64_t tiling_info; 316 __u64 tiling_info;
243 uint32_t data_size_bytes; 317 __u32 data_size_bytes;
244 uint32_t data[64]; 318 __u32 data[64];
245 } data; 319 } data;
246}; 320};
247 321
248struct drm_amdgpu_gem_mmap_in { 322struct drm_amdgpu_gem_mmap_in {
249 /** the GEM object handle */ 323 /** the GEM object handle */
250 uint32_t handle; 324 __u32 handle;
251 uint32_t _pad; 325 __u32 _pad;
252}; 326};
253 327
254struct drm_amdgpu_gem_mmap_out { 328struct drm_amdgpu_gem_mmap_out {
255 /** mmap offset from the vma offset manager */ 329 /** mmap offset from the vma offset manager */
256 uint64_t addr_ptr; 330 __u64 addr_ptr;
257}; 331};
258 332
259union drm_amdgpu_gem_mmap { 333union drm_amdgpu_gem_mmap {
@@ -263,18 +337,18 @@ union drm_amdgpu_gem_mmap {
263 337
264struct drm_amdgpu_gem_wait_idle_in { 338struct drm_amdgpu_gem_wait_idle_in {
265 /** GEM object handle */ 339 /** GEM object handle */
266 uint32_t handle; 340 __u32 handle;
267 /** For future use, no flags defined so far */ 341 /** For future use, no flags defined so far */
268 uint32_t flags; 342 __u32 flags;
269 /** Absolute timeout to wait */ 343 /** Absolute timeout to wait */
270 uint64_t timeout; 344 __u64 timeout;
271}; 345};
272 346
273struct drm_amdgpu_gem_wait_idle_out { 347struct drm_amdgpu_gem_wait_idle_out {
274 /** BO status: 0 - BO is idle, 1 - BO is busy */ 348 /** BO status: 0 - BO is idle, 1 - BO is busy */
275 uint32_t status; 349 __u32 status;
276 /** Returned current memory domain */ 350 /** Returned current memory domain */
277 uint32_t domain; 351 __u32 domain;
278}; 352};
279 353
280union drm_amdgpu_gem_wait_idle { 354union drm_amdgpu_gem_wait_idle {
@@ -283,19 +357,22 @@ union drm_amdgpu_gem_wait_idle {
283}; 357};
284 358
285struct drm_amdgpu_wait_cs_in { 359struct drm_amdgpu_wait_cs_in {
286 /** Command submission handle */ 360 /* Command submission handle
287 uint64_t handle; 361 * handle equals 0 means none to wait for
362 * handle equals ~0ull means wait for the latest sequence number
363 */
364 __u64 handle;
288 /** Absolute timeout to wait */ 365 /** Absolute timeout to wait */
289 uint64_t timeout; 366 __u64 timeout;
290 uint32_t ip_type; 367 __u32 ip_type;
291 uint32_t ip_instance; 368 __u32 ip_instance;
292 uint32_t ring; 369 __u32 ring;
293 uint32_t ctx_id; 370 __u32 ctx_id;
294}; 371};
295 372
296struct drm_amdgpu_wait_cs_out { 373struct drm_amdgpu_wait_cs_out {
297 /** CS status: 0 - CS completed, 1 - CS still busy */ 374 /** CS status: 0 - CS completed, 1 - CS still busy */
298 uint64_t status; 375 __u64 status;
299}; 376};
300 377
301union drm_amdgpu_wait_cs { 378union drm_amdgpu_wait_cs {
@@ -303,21 +380,49 @@ union drm_amdgpu_wait_cs {
303 struct drm_amdgpu_wait_cs_out out; 380 struct drm_amdgpu_wait_cs_out out;
304}; 381};
305 382
383struct drm_amdgpu_fence {
384 __u32 ctx_id;
385 __u32 ip_type;
386 __u32 ip_instance;
387 __u32 ring;
388 __u64 seq_no;
389};
390
391struct drm_amdgpu_wait_fences_in {
392 /** This points to uint64_t * which points to fences */
393 __u64 fences;
394 __u32 fence_count;
395 __u32 wait_all;
396 __u64 timeout_ns;
397};
398
399struct drm_amdgpu_wait_fences_out {
400 __u32 status;
401 __u32 first_signaled;
402};
403
404union drm_amdgpu_wait_fences {
405 struct drm_amdgpu_wait_fences_in in;
406 struct drm_amdgpu_wait_fences_out out;
407};
408
306#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 409#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
307#define AMDGPU_GEM_OP_SET_PLACEMENT 1 410#define AMDGPU_GEM_OP_SET_PLACEMENT 1
308 411
309/* Sets or returns a value associated with a buffer. */ 412/* Sets or returns a value associated with a buffer. */
310struct drm_amdgpu_gem_op { 413struct drm_amdgpu_gem_op {
311 /** GEM object handle */ 414 /** GEM object handle */
312 uint32_t handle; 415 __u32 handle;
313 /** AMDGPU_GEM_OP_* */ 416 /** AMDGPU_GEM_OP_* */
314 uint32_t op; 417 __u32 op;
315 /** Input or return value */ 418 /** Input or return value */
316 uint64_t value; 419 __u64 value;
317}; 420};
318 421
319#define AMDGPU_VA_OP_MAP 1 422#define AMDGPU_VA_OP_MAP 1
320#define AMDGPU_VA_OP_UNMAP 2 423#define AMDGPU_VA_OP_UNMAP 2
424#define AMDGPU_VA_OP_CLEAR 3
425#define AMDGPU_VA_OP_REPLACE 4
321 426
322/* Delay the page table update till the next CS */ 427/* Delay the page table update till the next CS */
323#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 428#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
@@ -329,21 +434,35 @@ struct drm_amdgpu_gem_op {
329#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 434#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
330/* executable mapping, new for VI */ 435/* executable mapping, new for VI */
331#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 436#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
437/* partially resident texture */
438#define AMDGPU_VM_PAGE_PRT (1 << 4)
439/* MTYPE flags use bit 5 to 8 */
440#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
441/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
442#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
443/* Use NC MTYPE instead of default MTYPE */
444#define AMDGPU_VM_MTYPE_NC (1 << 5)
445/* Use WC MTYPE instead of default MTYPE */
446#define AMDGPU_VM_MTYPE_WC (2 << 5)
447/* Use CC MTYPE instead of default MTYPE */
448#define AMDGPU_VM_MTYPE_CC (3 << 5)
449/* Use UC MTYPE instead of default MTYPE */
450#define AMDGPU_VM_MTYPE_UC (4 << 5)
332 451
333struct drm_amdgpu_gem_va { 452struct drm_amdgpu_gem_va {
334 /** GEM object handle */ 453 /** GEM object handle */
335 uint32_t handle; 454 __u32 handle;
336 uint32_t _pad; 455 __u32 _pad;
337 /** AMDGPU_VA_OP_* */ 456 /** AMDGPU_VA_OP_* */
338 uint32_t operation; 457 __u32 operation;
339 /** AMDGPU_VM_PAGE_* */ 458 /** AMDGPU_VM_PAGE_* */
340 uint32_t flags; 459 __u32 flags;
341 /** va address to assign . Must be correctly aligned.*/ 460 /** va address to assign . Must be correctly aligned.*/
342 uint64_t va_address; 461 __u64 va_address;
343 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 462 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
344 uint64_t offset_in_bo; 463 __u64 offset_in_bo;
345 /** Specify mapping size. Must be correctly aligned. */ 464 /** Specify mapping size. Must be correctly aligned. */
346 uint64_t map_size; 465 __u64 map_size;
347}; 466};
348 467
349#define AMDGPU_HW_IP_GFX 0 468#define AMDGPU_HW_IP_GFX 0
@@ -351,33 +470,38 @@ struct drm_amdgpu_gem_va {
351#define AMDGPU_HW_IP_DMA 2 470#define AMDGPU_HW_IP_DMA 2
352#define AMDGPU_HW_IP_UVD 3 471#define AMDGPU_HW_IP_UVD 3
353#define AMDGPU_HW_IP_VCE 4 472#define AMDGPU_HW_IP_VCE 4
354#define AMDGPU_HW_IP_NUM 5 473#define AMDGPU_HW_IP_UVD_ENC 5
474#define AMDGPU_HW_IP_VCN_DEC 6
475#define AMDGPU_HW_IP_VCN_ENC 7
476#define AMDGPU_HW_IP_NUM 8
355 477
356#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 478#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
357 479
358#define AMDGPU_CHUNK_ID_IB 0x01 480#define AMDGPU_CHUNK_ID_IB 0x01
359#define AMDGPU_CHUNK_ID_FENCE 0x02 481#define AMDGPU_CHUNK_ID_FENCE 0x02
360#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 482#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
483#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
484#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
361 485
362struct drm_amdgpu_cs_chunk { 486struct drm_amdgpu_cs_chunk {
363 uint32_t chunk_id; 487 __u32 chunk_id;
364 uint32_t length_dw; 488 __u32 length_dw;
365 uint64_t chunk_data; 489 __u64 chunk_data;
366}; 490};
367 491
368struct drm_amdgpu_cs_in { 492struct drm_amdgpu_cs_in {
369 /** Rendering context id */ 493 /** Rendering context id */
370 uint32_t ctx_id; 494 __u32 ctx_id;
371 /** Handle of resource list associated with CS */ 495 /** Handle of resource list associated with CS */
372 uint32_t bo_list_handle; 496 __u32 bo_list_handle;
373 uint32_t num_chunks; 497 __u32 num_chunks;
374 uint32_t _pad; 498 __u32 _pad;
375 /** this points to uint64_t * which point to cs chunks */ 499 /** this points to __u64 * which point to cs chunks */
376 uint64_t chunks; 500 __u64 chunks;
377}; 501};
378 502
379struct drm_amdgpu_cs_out { 503struct drm_amdgpu_cs_out {
380 uint64_t handle; 504 __u64 handle;
381}; 505};
382 506
383union drm_amdgpu_cs { 507union drm_amdgpu_cs {
@@ -390,36 +514,58 @@ union drm_amdgpu_cs {
390/* This IB should be submitted to CE */ 514/* This IB should be submitted to CE */
391#define AMDGPU_IB_FLAG_CE (1<<0) 515#define AMDGPU_IB_FLAG_CE (1<<0)
392 516
393/* CE Preamble */ 517/* Preamble flag, which means the IB could be dropped if no context switch */
394#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 518#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
395 519
520/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
521#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
522
396struct drm_amdgpu_cs_chunk_ib { 523struct drm_amdgpu_cs_chunk_ib {
397 uint32_t _pad; 524 __u32 _pad;
398 /** AMDGPU_IB_FLAG_* */ 525 /** AMDGPU_IB_FLAG_* */
399 uint32_t flags; 526 __u32 flags;
400 /** Virtual address to begin IB execution */ 527 /** Virtual address to begin IB execution */
401 uint64_t va_start; 528 __u64 va_start;
402 /** Size of submission */ 529 /** Size of submission */
403 uint32_t ib_bytes; 530 __u32 ib_bytes;
404 /** HW IP to submit to */ 531 /** HW IP to submit to */
405 uint32_t ip_type; 532 __u32 ip_type;
406 /** HW IP index of the same type to submit to */ 533 /** HW IP index of the same type to submit to */
407 uint32_t ip_instance; 534 __u32 ip_instance;
408 /** Ring index to submit to */ 535 /** Ring index to submit to */
409 uint32_t ring; 536 __u32 ring;
410}; 537};
411 538
412struct drm_amdgpu_cs_chunk_dep { 539struct drm_amdgpu_cs_chunk_dep {
413 uint32_t ip_type; 540 __u32 ip_type;
414 uint32_t ip_instance; 541 __u32 ip_instance;
415 uint32_t ring; 542 __u32 ring;
416 uint32_t ctx_id; 543 __u32 ctx_id;
417 uint64_t handle; 544 __u64 handle;
418}; 545};
419 546
420struct drm_amdgpu_cs_chunk_fence { 547struct drm_amdgpu_cs_chunk_fence {
421 uint32_t handle; 548 __u32 handle;
422 uint32_t offset; 549 __u32 offset;
550};
551
552struct drm_amdgpu_cs_chunk_sem {
553 __u32 handle;
554};
555
556#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
557#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
558#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
559
560union drm_amdgpu_fence_to_handle {
561 struct {
562 struct drm_amdgpu_fence fence;
563 __u32 what;
564 __u32 pad;
565 } in;
566 struct {
567 __u32 handle;
568 } out;
423}; 569};
424 570
425struct drm_amdgpu_cs_chunk_data { 571struct drm_amdgpu_cs_chunk_data {
@@ -434,6 +580,7 @@ struct drm_amdgpu_cs_chunk_data {
434 * 580 *
435 */ 581 */
436#define AMDGPU_IDS_FLAGS_FUSION 0x1 582#define AMDGPU_IDS_FLAGS_FUSION 0x1
583#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
437 584
438/* indicate if acceleration can be working */ 585/* indicate if acceleration can be working */
439#define AMDGPU_INFO_ACCEL_WORKING 0x00 586#define AMDGPU_INFO_ACCEL_WORKING 0x00
@@ -467,6 +614,12 @@ struct drm_amdgpu_cs_chunk_data {
467 #define AMDGPU_INFO_FW_SMC 0x0a 614 #define AMDGPU_INFO_FW_SMC 0x0a
468 /* Subquery id: Query SDMA firmware version */ 615 /* Subquery id: Query SDMA firmware version */
469 #define AMDGPU_INFO_FW_SDMA 0x0b 616 #define AMDGPU_INFO_FW_SDMA 0x0b
617 /* Subquery id: Query PSP SOS firmware version */
618 #define AMDGPU_INFO_FW_SOS 0x0c
619 /* Subquery id: Query PSP ASD firmware version */
620 #define AMDGPU_INFO_FW_ASD 0x0d
621 /* Subquery id: Query VCN firmware version */
622 #define AMDGPU_INFO_FW_VCN 0x0e
470/* number of bytes moved for TTM migration */ 623/* number of bytes moved for TTM migration */
471#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 624#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
472/* the used VRAM size */ 625/* the used VRAM size */
@@ -483,6 +636,43 @@ struct drm_amdgpu_cs_chunk_data {
483#define AMDGPU_INFO_DEV_INFO 0x16 636#define AMDGPU_INFO_DEV_INFO 0x16
484/* visible vram usage */ 637/* visible vram usage */
485#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 638#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
639/* number of TTM buffer evictions */
640#define AMDGPU_INFO_NUM_EVICTIONS 0x18
641/* Query memory about VRAM and GTT domains */
642#define AMDGPU_INFO_MEMORY 0x19
643/* Query vce clock table */
644#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
645/* Query vbios related information */
646#define AMDGPU_INFO_VBIOS 0x1B
647 /* Subquery id: Query vbios size */
648 #define AMDGPU_INFO_VBIOS_SIZE 0x1
649 /* Subquery id: Query vbios image */
650 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
651/* Query UVD handles */
652#define AMDGPU_INFO_NUM_HANDLES 0x1C
653/* Query sensor related information */
654#define AMDGPU_INFO_SENSOR 0x1D
655 /* Subquery id: Query GPU shader clock */
656 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
657 /* Subquery id: Query GPU memory clock */
658 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
659 /* Subquery id: Query GPU temperature */
660 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
661 /* Subquery id: Query GPU load */
662 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
663 /* Subquery id: Query average GPU power */
664 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
665 /* Subquery id: Query northbridge voltage */
666 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
667 /* Subquery id: Query graphics voltage */
668 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
669 /* Subquery id: Query GPU stable pstate shader clock */
670 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
671 /* Subquery id: Query GPU stable pstate memory clock */
672 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
673/* Number of VRAM page faults on CPU access. */
674#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
675#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
486 676
487#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 677#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
488#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 678#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -491,86 +681,123 @@ struct drm_amdgpu_cs_chunk_data {
491 681
492struct drm_amdgpu_query_fw { 682struct drm_amdgpu_query_fw {
493 /** AMDGPU_INFO_FW_* */ 683 /** AMDGPU_INFO_FW_* */
494 uint32_t fw_type; 684 __u32 fw_type;
495 /** 685 /**
496 * Index of the IP if there are more IPs of 686 * Index of the IP if there are more IPs of
497 * the same type. 687 * the same type.
498 */ 688 */
499 uint32_t ip_instance; 689 __u32 ip_instance;
500 /** 690 /**
501 * Index of the engine. Whether this is used depends 691 * Index of the engine. Whether this is used depends
502 * on the firmware type. (e.g. MEC, SDMA) 692 * on the firmware type. (e.g. MEC, SDMA)
503 */ 693 */
504 uint32_t index; 694 __u32 index;
505 uint32_t _pad; 695 __u32 _pad;
506}; 696};
507 697
508/* Input structure for the INFO ioctl */ 698/* Input structure for the INFO ioctl */
509struct drm_amdgpu_info { 699struct drm_amdgpu_info {
510 /* Where the return value will be stored */ 700 /* Where the return value will be stored */
511 uint64_t return_pointer; 701 __u64 return_pointer;
512 /* The size of the return value. Just like "size" in "snprintf", 702 /* The size of the return value. Just like "size" in "snprintf",
513 * it limits how many bytes the kernel can write. */ 703 * it limits how many bytes the kernel can write. */
514 uint32_t return_size; 704 __u32 return_size;
515 /* The query request id. */ 705 /* The query request id. */
516 uint32_t query; 706 __u32 query;
517 707
518 union { 708 union {
519 struct { 709 struct {
520 uint32_t id; 710 __u32 id;
521 uint32_t _pad; 711 __u32 _pad;
522 } mode_crtc; 712 } mode_crtc;
523 713
524 struct { 714 struct {
525 /** AMDGPU_HW_IP_* */ 715 /** AMDGPU_HW_IP_* */
526 uint32_t type; 716 __u32 type;
527 /** 717 /**
528 * Index of the IP if there are more IPs of the same 718 * Index of the IP if there are more IPs of the same
529 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 719 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
530 */ 720 */
531 uint32_t ip_instance; 721 __u32 ip_instance;
532 } query_hw_ip; 722 } query_hw_ip;
533 723
534 struct { 724 struct {
535 uint32_t dword_offset; 725 __u32 dword_offset;
536 /** number of registers to read */ 726 /** number of registers to read */
537 uint32_t count; 727 __u32 count;
538 uint32_t instance; 728 __u32 instance;
539 /** For future use, no flags defined so far */ 729 /** For future use, no flags defined so far */
540 uint32_t flags; 730 __u32 flags;
541 } read_mmr_reg; 731 } read_mmr_reg;
542 732
543 struct drm_amdgpu_query_fw query_fw; 733 struct drm_amdgpu_query_fw query_fw;
734
735 struct {
736 __u32 type;
737 __u32 offset;
738 } vbios_info;
739
740 struct {
741 __u32 type;
742 } sensor_info;
544 }; 743 };
545}; 744};
546 745
547struct drm_amdgpu_info_gds { 746struct drm_amdgpu_info_gds {
548 /** GDS GFX partition size */ 747 /** GDS GFX partition size */
549 uint32_t gds_gfx_partition_size; 748 __u32 gds_gfx_partition_size;
550 /** GDS compute partition size */ 749 /** GDS compute partition size */
551 uint32_t compute_partition_size; 750 __u32 compute_partition_size;
552 /** total GDS memory size */ 751 /** total GDS memory size */
553 uint32_t gds_total_size; 752 __u32 gds_total_size;
554 /** GWS size per GFX partition */ 753 /** GWS size per GFX partition */
555 uint32_t gws_per_gfx_partition; 754 __u32 gws_per_gfx_partition;
556 /** GSW size per compute partition */ 755 /** GSW size per compute partition */
557 uint32_t gws_per_compute_partition; 756 __u32 gws_per_compute_partition;
558 /** OA size per GFX partition */ 757 /** OA size per GFX partition */
559 uint32_t oa_per_gfx_partition; 758 __u32 oa_per_gfx_partition;
560 /** OA size per compute partition */ 759 /** OA size per compute partition */
561 uint32_t oa_per_compute_partition; 760 __u32 oa_per_compute_partition;
562 uint32_t _pad; 761 __u32 _pad;
563}; 762};
564 763
565struct drm_amdgpu_info_vram_gtt { 764struct drm_amdgpu_info_vram_gtt {
566 uint64_t vram_size; 765 __u64 vram_size;
567 uint64_t vram_cpu_accessible_size; 766 __u64 vram_cpu_accessible_size;
568 uint64_t gtt_size; 767 __u64 gtt_size;
768};
769
770struct drm_amdgpu_heap_info {
771 /** max. physical memory */
772 __u64 total_heap_size;
773
774 /** Theoretical max. available memory in the given heap */
775 __u64 usable_heap_size;
776
777 /**
778 * Number of bytes allocated in the heap. This includes all processes
779 * and private allocations in the kernel. It changes when new buffers
780 * are allocated, freed, and moved. It cannot be larger than
781 * heap_size.
782 */
783 __u64 heap_usage;
784
785 /**
786 * Theoretical possible max. size of buffer which
787 * could be allocated in the given heap
788 */
789 __u64 max_allocation;
790};
791
792struct drm_amdgpu_memory_info {
793 struct drm_amdgpu_heap_info vram;
794 struct drm_amdgpu_heap_info cpu_accessible_vram;
795 struct drm_amdgpu_heap_info gtt;
569}; 796};
570 797
571struct drm_amdgpu_info_firmware { 798struct drm_amdgpu_info_firmware {
572 uint32_t ver; 799 __u32 ver;
573 uint32_t feature; 800 __u32 feature;
574}; 801};
575 802
576#define AMDGPU_VRAM_TYPE_UNKNOWN 0 803#define AMDGPU_VRAM_TYPE_UNKNOWN 0
@@ -581,74 +808,139 @@ struct drm_amdgpu_info_firmware {
581#define AMDGPU_VRAM_TYPE_GDDR5 5 808#define AMDGPU_VRAM_TYPE_GDDR5 5
582#define AMDGPU_VRAM_TYPE_HBM 6 809#define AMDGPU_VRAM_TYPE_HBM 6
583#define AMDGPU_VRAM_TYPE_DDR3 7 810#define AMDGPU_VRAM_TYPE_DDR3 7
811#define AMDGPU_VRAM_TYPE_DDR4 8
584 812
585struct drm_amdgpu_info_device { 813struct drm_amdgpu_info_device {
586 /** PCI Device ID */ 814 /** PCI Device ID */
587 uint32_t device_id; 815 __u32 device_id;
588 /** Internal chip revision: A0, A1, etc.) */ 816 /** Internal chip revision: A0, A1, etc.) */
589 uint32_t chip_rev; 817 __u32 chip_rev;
590 uint32_t external_rev; 818 __u32 external_rev;
591 /** Revision id in PCI Config space */ 819 /** Revision id in PCI Config space */
592 uint32_t pci_rev; 820 __u32 pci_rev;
593 uint32_t family; 821 __u32 family;
594 uint32_t num_shader_engines; 822 __u32 num_shader_engines;
595 uint32_t num_shader_arrays_per_engine; 823 __u32 num_shader_arrays_per_engine;
596 /* in KHz */ 824 /* in KHz */
597 uint32_t gpu_counter_freq; 825 __u32 gpu_counter_freq;
598 uint64_t max_engine_clock; 826 __u64 max_engine_clock;
599 uint64_t max_memory_clock; 827 __u64 max_memory_clock;
600 /* cu information */ 828 /* cu information */
601 uint32_t cu_active_number; 829 __u32 cu_active_number;
602 uint32_t cu_ao_mask; 830 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
603 uint32_t cu_bitmap[4][4]; 831 __u32 cu_ao_mask;
832 __u32 cu_bitmap[4][4];
604 /** Render backend pipe mask. One render backend is CB+DB. */ 833 /** Render backend pipe mask. One render backend is CB+DB. */
605 uint32_t enabled_rb_pipes_mask; 834 __u32 enabled_rb_pipes_mask;
606 uint32_t num_rb_pipes; 835 __u32 num_rb_pipes;
607 uint32_t num_hw_gfx_contexts; 836 __u32 num_hw_gfx_contexts;
608 uint32_t _pad; 837 __u32 _pad;
609 uint64_t ids_flags; 838 __u64 ids_flags;
610 /** Starting virtual address for UMDs. */ 839 /** Starting virtual address for UMDs. */
611 uint64_t virtual_address_offset; 840 __u64 virtual_address_offset;
612 /** The maximum virtual address */ 841 /** The maximum virtual address */
613 uint64_t virtual_address_max; 842 __u64 virtual_address_max;
614 /** Required alignment of virtual addresses. */ 843 /** Required alignment of virtual addresses. */
615 uint32_t virtual_address_alignment; 844 __u32 virtual_address_alignment;
616 /** Page table entry - fragment size */ 845 /** Page table entry - fragment size */
617 uint32_t pte_fragment_size; 846 __u32 pte_fragment_size;
618 uint32_t gart_page_size; 847 __u32 gart_page_size;
619 /** constant engine ram size*/ 848 /** constant engine ram size*/
620 uint32_t ce_ram_size; 849 __u32 ce_ram_size;
621 /** video memory type info*/ 850 /** video memory type info*/
622 uint32_t vram_type; 851 __u32 vram_type;
623 /** video memory bit width*/ 852 /** video memory bit width*/
624 uint32_t vram_bit_width; 853 __u32 vram_bit_width;
625 /* vce harvesting instance */ 854 /* vce harvesting instance */
626 uint32_t vce_harvest_config; 855 __u32 vce_harvest_config;
856 /* gfx double offchip LDS buffers */
857 __u32 gc_double_offchip_lds_buf;
858 /* NGG Primitive Buffer */
859 __u64 prim_buf_gpu_addr;
860 /* NGG Position Buffer */
861 __u64 pos_buf_gpu_addr;
862 /* NGG Control Sideband */
863 __u64 cntl_sb_buf_gpu_addr;
864 /* NGG Parameter Cache */
865 __u64 param_buf_gpu_addr;
866 __u32 prim_buf_size;
867 __u32 pos_buf_size;
868 __u32 cntl_sb_buf_size;
869 __u32 param_buf_size;
870 /* wavefront size*/
871 __u32 wave_front_size;
872 /* shader visible vgprs*/
873 __u32 num_shader_visible_vgprs;
874 /* CU per shader array*/
875 __u32 num_cu_per_sh;
876 /* number of tcc blocks*/
877 __u32 num_tcc_blocks;
878 /* gs vgt table depth*/
879 __u32 gs_vgt_table_depth;
880 /* gs primitive buffer depth*/
881 __u32 gs_prim_buffer_depth;
882 /* max gs wavefront per vgt*/
883 __u32 max_gs_waves_per_vgt;
884 __u32 _pad1;
885 /* always on cu bitmap */
886 __u32 cu_ao_bitmap[4][4];
887 /** Starting high virtual address for UMDs. */
888 __u64 high_va_offset;
889 /** The maximum high virtual address */
890 __u64 high_va_max;
627}; 891};
628 892
629struct drm_amdgpu_info_hw_ip { 893struct drm_amdgpu_info_hw_ip {
630 /** Version of h/w IP */ 894 /** Version of h/w IP */
631 uint32_t hw_ip_version_major; 895 __u32 hw_ip_version_major;
632 uint32_t hw_ip_version_minor; 896 __u32 hw_ip_version_minor;
633 /** Capabilities */ 897 /** Capabilities */
634 uint64_t capabilities_flags; 898 __u64 capabilities_flags;
635 /** command buffer address start alignment*/ 899 /** command buffer address start alignment*/
636 uint32_t ib_start_alignment; 900 __u32 ib_start_alignment;
637 /** command buffer size alignment*/ 901 /** command buffer size alignment*/
638 uint32_t ib_size_alignment; 902 __u32 ib_size_alignment;
639 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 903 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
640 uint32_t available_rings; 904 __u32 available_rings;
641 uint32_t _pad; 905 __u32 _pad;
906};
907
908struct drm_amdgpu_info_num_handles {
909 /** Max handles as supported by firmware for UVD */
910 __u32 uvd_max_handles;
911 /** Handles currently in use for UVD */
912 __u32 uvd_used_handles;
913};
914
915#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
916
917struct drm_amdgpu_info_vce_clock_table_entry {
918 /** System clock */
919 __u32 sclk;
920 /** Memory clock */
921 __u32 mclk;
922 /** VCE clock */
923 __u32 eclk;
924 __u32 pad;
925};
926
927struct drm_amdgpu_info_vce_clock_table {
928 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
929 __u32 num_valid_entries;
930 __u32 pad;
642}; 931};
643 932
644/* 933/*
645 * Supported GPU families 934 * Supported GPU families
646 */ 935 */
647#define AMDGPU_FAMILY_UNKNOWN 0 936#define AMDGPU_FAMILY_UNKNOWN 0
937#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
648#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 938#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
649#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 939#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
650#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 940#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
651#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 941#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
942#define AMDGPU_FAMILY_AI 141 /* Vega10 */
943#define AMDGPU_FAMILY_RV 142 /* Raven */
652 944
653#if defined(__cplusplus) 945#if defined(__cplusplus)
654} 946}