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authorChris Wilson2010-10-29 04:49:54 -0500
committerChris Wilson2010-10-29 04:49:54 -0500
commit362457715faacd3101929e5f0d8ae250d0ad09df (patch)
tree5e6570b972e10adda463aabe1a9f34ad883f9092
parent0a1ff35c70730160973715b82112cd97c62ac13e (diff)
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intel: enable relaxed fence allocation for i915
The kernel has always allowed userspace to underallocate objects supplied for fencing. However, the kernel only allocated the object size for the fence in the GTT and so caused tiling corruption. More recently the kernel does allocate the full fence region in the GTT for an under-sized object and so advertises that clients may finally make use of this feature. The biggest benefit is for texture-heavy GL games on i945 such as World of Padman which go from needing over 1GiB of RAM to play to fitting in the GTT! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--include/drm/i915_drm.h1
-rw-r--r--intel/intel_bufmgr_gem.c15
2 files changed, 13 insertions, 3 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index bd930614..19da2c04 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -278,6 +278,7 @@ typedef struct drm_i915_irq_wait {
278#define I915_PARAM_HAS_EXECBUF2 9 278#define I915_PARAM_HAS_EXECBUF2 9
279#define I915_PARAM_HAS_BSD 10 279#define I915_PARAM_HAS_BSD 10
280#define I915_PARAM_HAS_BLT 11 280#define I915_PARAM_HAS_BLT 11
281#define I915_PARAM_HAS_RELAXED_FENCING 12
281 282
282typedef struct drm_i915_getparam { 283typedef struct drm_i915_getparam {
283 int param; 284 int param;
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c5847a8a..37a3691c 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -99,9 +99,10 @@ typedef struct _drm_intel_bufmgr_gem {
99 int available_fences; 99 int available_fences;
100 int pci_device; 100 int pci_device;
101 int gen; 101 int gen;
102 char has_bsd; 102 unsigned int has_bsd : 1;
103 char has_blt; 103 unsigned int has_blt : 1;
104 char bo_reuse; 104 unsigned int has_relaxed_fencing : 1;
105 unsigned int bo_reuse : 1;
105 char fenced_relocs; 106 char fenced_relocs;
106} drm_intel_bufmgr_gem; 107} drm_intel_bufmgr_gem;
107 108
@@ -243,6 +244,10 @@ drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
243 return size; 244 return size;
244 } 245 }
245 246
247 /* Do we need to allocate every page for the fence? */
248 if (bufmgr_gem->has_relaxed_fencing)
249 return ROUND_UP_TO(size, 4096);
250
246 for (i = min_size; i < size; i <<= 1) 251 for (i = min_size; i < size; i <<= 1)
247 ; 252 ;
248 253
@@ -2128,6 +2133,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
2128 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 2133 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2129 bufmgr_gem->has_blt = ret == 0; 2134 bufmgr_gem->has_blt = ret == 0;
2130 2135
2136 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2137 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2138 bufmgr_gem->has_relaxed_fencing = ret == 0;
2139
2131 if (bufmgr_gem->gen < 4) { 2140 if (bufmgr_gem->gen < 4) {
2132 gp.param = I915_PARAM_NUM_FENCES_AVAIL; 2141 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2133 gp.value = &bufmgr_gem->available_fences; 2142 gp.value = &bufmgr_gem->available_fences;