diff options
author | Eric Anholt | 2016-01-25 12:16:56 -0600 |
---|---|---|
committer | Eric Anholt | 2016-02-03 13:29:52 -0600 |
commit | 3c717f61f885240980bfc4273dbd1fc837edc391 (patch) | |
tree | df61d1686c4d466251b059c6c576ee22a50a9439 | |
parent | 0ad32e7ff48e106d654acca79445389651ed6909 (diff) | |
download | external-libgbm-3c717f61f885240980bfc4273dbd1fc837edc391.tar.gz external-libgbm-3c717f61f885240980bfc4273dbd1fc837edc391.tar.xz external-libgbm-3c717f61f885240980bfc4273dbd1fc837edc391.zip |
vc4: Add headers and .pc files for VC4 userspace development.
The headers were originally written in Mesa, imported to the kernel,
and improved upon in vc4-gpu-tools. These come from the v-g-t copies
and will replace the Mesa and v-g-t copies, and hopefully be used from
new tests in igt, as well.
v2: Fix linking against libdrm_intel instead of libdrm.
v3: Drop Libs and Cflags since they'll be inherited from libdrm.
v4: Switch to Requires.private. I was wrong about standard practice,
apparently only Intel was doing plain Requires (sorry to all
involved).
Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r-- | Makefile.am | 6 | ||||
-rw-r--r-- | configure.ac | 19 | ||||
-rw-r--r-- | vc4/Makefile.am | 34 | ||||
-rw-r--r-- | vc4/Makefile.sources | 3 | ||||
-rw-r--r-- | vc4/libdrm_vc4.pc.in | 9 | ||||
-rw-r--r-- | vc4/vc4_packet.h | 397 | ||||
-rw-r--r-- | vc4/vc4_qpu_defines.h | 274 |
7 files changed, 742 insertions, 0 deletions
diff --git a/Makefile.am b/Makefile.am index ca415089..feecba72 100644 --- a/Makefile.am +++ b/Makefile.am | |||
@@ -29,6 +29,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \ | |||
29 | --enable-radeon \ | 29 | --enable-radeon \ |
30 | --enable-amdgpu \ | 30 | --enable-amdgpu \ |
31 | --enable-nouveau \ | 31 | --enable-nouveau \ |
32 | --enable-vc4 \ | ||
32 | --enable-vmwgfx \ | 33 | --enable-vmwgfx \ |
33 | --enable-omap-experimental-api \ | 34 | --enable-omap-experimental-api \ |
34 | --enable-exynos-experimental-api \ | 35 | --enable-exynos-experimental-api \ |
@@ -79,6 +80,10 @@ if HAVE_TEGRA | |||
79 | TEGRA_SUBDIR = tegra | 80 | TEGRA_SUBDIR = tegra |
80 | endif | 81 | endif |
81 | 82 | ||
83 | if HAVE_VC4 | ||
84 | VC4_SUBDIR = vc4 | ||
85 | endif | ||
86 | |||
82 | if BUILD_MANPAGES | 87 | if BUILD_MANPAGES |
83 | if HAVE_MANPAGES_STYLESHEET | 88 | if HAVE_MANPAGES_STYLESHEET |
84 | MAN_SUBDIR = man | 89 | MAN_SUBDIR = man |
@@ -96,6 +101,7 @@ SUBDIRS = \ | |||
96 | $(EXYNOS_SUBDIR) \ | 101 | $(EXYNOS_SUBDIR) \ |
97 | $(FREEDRENO_SUBDIR) \ | 102 | $(FREEDRENO_SUBDIR) \ |
98 | $(TEGRA_SUBDIR) \ | 103 | $(TEGRA_SUBDIR) \ |
104 | $(VC4_SUBDIR) \ | ||
99 | tests \ | 105 | tests \ |
100 | $(MAN_SUBDIR) | 106 | $(MAN_SUBDIR) |
101 | 107 | ||
diff --git a/configure.ac b/configure.ac index 4635d182..4eeebfba 100644 --- a/configure.ac +++ b/configure.ac | |||
@@ -126,6 +126,11 @@ AC_ARG_ENABLE(tegra-experimental-api, | |||
126 | [Enable support for Tegra's experimental API (default: disabled)]), | 126 | [Enable support for Tegra's experimental API (default: disabled)]), |
127 | [TEGRA=$enableval], [TEGRA=no]) | 127 | [TEGRA=$enableval], [TEGRA=no]) |
128 | 128 | ||
129 | AC_ARG_ENABLE(vc4, | ||
130 | AS_HELP_STRING([--disable-vc4], | ||
131 | [Enable support for vc4's API (default: auto, enabled on arm)]), | ||
132 | [VC4=$enableval], [VC4=auto]) | ||
133 | |||
129 | AC_ARG_ENABLE(install-test-programs, | 134 | AC_ARG_ENABLE(install-test-programs, |
130 | AS_HELP_STRING([--enable-install-test-programs], | 135 | AS_HELP_STRING([--enable-install-test-programs], |
131 | [Install test programs (default: no)]), | 136 | [Install test programs (default: no)]), |
@@ -290,6 +295,12 @@ else | |||
290 | *) FREEDRENO=no ;; | 295 | *) FREEDRENO=no ;; |
291 | esac | 296 | esac |
292 | fi | 297 | fi |
298 | if test "x$VC4" = xauto; then | ||
299 | case $host_cpu in | ||
300 | arm*|aarch64) VC4=yes ;; | ||
301 | *) VC4=no ;; | ||
302 | esac | ||
303 | fi | ||
293 | fi | 304 | fi |
294 | 305 | ||
295 | if test "x$INTEL" != "xno"; then | 306 | if test "x$INTEL" != "xno"; then |
@@ -396,6 +407,11 @@ if test "x$TEGRA" = xyes; then | |||
396 | AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support]) | 407 | AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support]) |
397 | fi | 408 | fi |
398 | 409 | ||
410 | AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) | ||
411 | if test "x$VC4" = xyes; then | ||
412 | AC_DEFINE(HAVE_VC4, 1, [Have VC4 support]) | ||
413 | fi | ||
414 | |||
399 | AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) | 415 | AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) |
400 | if test "x$INSTALL_TESTS" = xyes; then | 416 | if test "x$INSTALL_TESTS" = xyes; then |
401 | AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs]) | 417 | AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs]) |
@@ -505,6 +521,8 @@ AC_CONFIG_FILES([ | |||
505 | freedreno/libdrm_freedreno.pc | 521 | freedreno/libdrm_freedreno.pc |
506 | tegra/Makefile | 522 | tegra/Makefile |
507 | tegra/libdrm_tegra.pc | 523 | tegra/libdrm_tegra.pc |
524 | vc4/Makefile | ||
525 | vc4/libdrm_vc4.pc | ||
508 | tests/Makefile | 526 | tests/Makefile |
509 | tests/modeprint/Makefile | 527 | tests/modeprint/Makefile |
510 | tests/modetest/Makefile | 528 | tests/modetest/Makefile |
@@ -535,4 +553,5 @@ echo " OMAP API $OMAP" | |||
535 | echo " EXYNOS API $EXYNOS" | 553 | echo " EXYNOS API $EXYNOS" |
536 | echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)" | 554 | echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)" |
537 | echo " Tegra API $TEGRA" | 555 | echo " Tegra API $TEGRA" |
556 | echo " VC4 API $VC4" | ||
538 | echo "" | 557 | echo "" |
diff --git a/vc4/Makefile.am b/vc4/Makefile.am new file mode 100644 index 00000000..7e486b4d --- /dev/null +++ b/vc4/Makefile.am | |||
@@ -0,0 +1,34 @@ | |||
1 | # Copyright © 2016 Broadcom | ||
2 | # | ||
3 | # Permission is hereby granted, free of charge, to any person obtaining a | ||
4 | # copy of this software and associated documentation files (the "Software"), | ||
5 | # to deal in the Software without restriction, including without limitation | ||
6 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
7 | # and/or sell copies of the Software, and to permit persons to whom the | ||
8 | # Software is furnished to do so, subject to the following conditions: | ||
9 | # | ||
10 | # The above copyright notice and this permission notice (including the next | ||
11 | # paragraph) shall be included in all copies or substantial portions of the | ||
12 | # Software. | ||
13 | # | ||
14 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | ||
20 | # IN THE SOFTWARE. | ||
21 | |||
22 | include Makefile.sources | ||
23 | |||
24 | AM_CFLAGS = \ | ||
25 | $(WARN_CFLAGS) \ | ||
26 | -I$(top_srcdir) \ | ||
27 | $(PTHREADSTUBS_CFLAGS) \ | ||
28 | $(VALGRIND_CFLAGS) \ | ||
29 | -I$(top_srcdir)/include/drm | ||
30 | |||
31 | libdrm_vc4includedir = ${includedir}/libdrm | ||
32 | libdrm_vc4include_HEADERS = $(LIBDRM_VC4_H_FILES) | ||
33 | |||
34 | pkgconfig_DATA = libdrm_vc4.pc | ||
diff --git a/vc4/Makefile.sources b/vc4/Makefile.sources new file mode 100644 index 00000000..8bf97ff1 --- /dev/null +++ b/vc4/Makefile.sources | |||
@@ -0,0 +1,3 @@ | |||
1 | LIBDRM_VC4_H_FILES := \ | ||
2 | vc4_packet.h \ | ||
3 | vc4_qpu_defines.h | ||
diff --git a/vc4/libdrm_vc4.pc.in b/vc4/libdrm_vc4.pc.in new file mode 100644 index 00000000..a92678ed --- /dev/null +++ b/vc4/libdrm_vc4.pc.in | |||
@@ -0,0 +1,9 @@ | |||
1 | prefix=@prefix@ | ||
2 | exec_prefix=@exec_prefix@ | ||
3 | libdir=@libdir@ | ||
4 | includedir=@includedir@ | ||
5 | |||
6 | Name: libdrm_vc4 | ||
7 | Description: Userspace interface to vc4 kernel DRM services | ||
8 | Version: @PACKAGE_VERSION@ | ||
9 | Requires.private: libdrm | ||
diff --git a/vc4/vc4_packet.h b/vc4/vc4_packet.h new file mode 100644 index 00000000..e18e0bdf --- /dev/null +++ b/vc4/vc4_packet.h | |||
@@ -0,0 +1,397 @@ | |||
1 | /* | ||
2 | * Copyright © 2014 Broadcom | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice (including the next | ||
12 | * paragraph) shall be included in all copies or substantial portions of the | ||
13 | * Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | ||
21 | * IN THE SOFTWARE. | ||
22 | */ | ||
23 | |||
24 | #ifndef VC4_PACKET_H | ||
25 | #define VC4_PACKET_H | ||
26 | |||
27 | enum vc4_packet { | ||
28 | VC4_PACKET_HALT = 0, | ||
29 | VC4_PACKET_NOP = 1, | ||
30 | |||
31 | VC4_PACKET_FLUSH = 4, | ||
32 | VC4_PACKET_FLUSH_ALL = 5, | ||
33 | VC4_PACKET_START_TILE_BINNING = 6, | ||
34 | VC4_PACKET_INCREMENT_SEMAPHORE = 7, | ||
35 | VC4_PACKET_WAIT_ON_SEMAPHORE = 8, | ||
36 | |||
37 | VC4_PACKET_BRANCH = 16, | ||
38 | VC4_PACKET_BRANCH_TO_SUB_LIST = 17, | ||
39 | VC4_PACKET_RETURN_FROM_SUB_LIST = 18, | ||
40 | |||
41 | VC4_PACKET_STORE_MS_TILE_BUFFER = 24, | ||
42 | VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, | ||
43 | VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, | ||
44 | VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, | ||
45 | VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, | ||
46 | VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, | ||
47 | |||
48 | VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, | ||
49 | VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, | ||
50 | |||
51 | VC4_PACKET_COMPRESSED_PRIMITIVE = 48, | ||
52 | VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, | ||
53 | |||
54 | VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, | ||
55 | |||
56 | VC4_PACKET_GL_SHADER_STATE = 64, | ||
57 | VC4_PACKET_NV_SHADER_STATE = 65, | ||
58 | VC4_PACKET_VG_SHADER_STATE = 66, | ||
59 | |||
60 | VC4_PACKET_CONFIGURATION_BITS = 96, | ||
61 | VC4_PACKET_FLAT_SHADE_FLAGS = 97, | ||
62 | VC4_PACKET_POINT_SIZE = 98, | ||
63 | VC4_PACKET_LINE_WIDTH = 99, | ||
64 | VC4_PACKET_RHT_X_BOUNDARY = 100, | ||
65 | VC4_PACKET_DEPTH_OFFSET = 101, | ||
66 | VC4_PACKET_CLIP_WINDOW = 102, | ||
67 | VC4_PACKET_VIEWPORT_OFFSET = 103, | ||
68 | VC4_PACKET_Z_CLIPPING = 104, | ||
69 | VC4_PACKET_CLIPPER_XY_SCALING = 105, | ||
70 | VC4_PACKET_CLIPPER_Z_SCALING = 106, | ||
71 | |||
72 | VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, | ||
73 | VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, | ||
74 | VC4_PACKET_CLEAR_COLORS = 114, | ||
75 | VC4_PACKET_TILE_COORDINATES = 115, | ||
76 | |||
77 | /* Not an actual hardware packet -- this is what we use to put | ||
78 | * references to GEM bos in the command stream, since we need the u32 | ||
79 | * int the actual address packet in order to store the offset from the | ||
80 | * start of the BO. | ||
81 | */ | ||
82 | VC4_PACKET_GEM_HANDLES = 254, | ||
83 | } __attribute__ ((__packed__)); | ||
84 | |||
85 | #define VC4_PACKET_HALT_SIZE 1 | ||
86 | #define VC4_PACKET_NOP_SIZE 1 | ||
87 | #define VC4_PACKET_FLUSH_SIZE 1 | ||
88 | #define VC4_PACKET_FLUSH_ALL_SIZE 1 | ||
89 | #define VC4_PACKET_START_TILE_BINNING_SIZE 1 | ||
90 | #define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE 1 | ||
91 | #define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE 1 | ||
92 | #define VC4_PACKET_BRANCH_SIZE 5 | ||
93 | #define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 5 | ||
94 | #define VC4_PACKET_RETURN_FROM_SUB_LIST_SIZE 1 | ||
95 | #define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE 1 | ||
96 | #define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE 1 | ||
97 | #define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 5 | ||
98 | #define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 5 | ||
99 | #define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE 7 | ||
100 | #define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE 7 | ||
101 | #define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE 14 | ||
102 | #define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE 10 | ||
103 | #define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE 1 | ||
104 | #define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE 1 | ||
105 | #define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE 2 | ||
106 | #define VC4_PACKET_GL_SHADER_STATE_SIZE 5 | ||
107 | #define VC4_PACKET_NV_SHADER_STATE_SIZE 5 | ||
108 | #define VC4_PACKET_VG_SHADER_STATE_SIZE 5 | ||
109 | #define VC4_PACKET_CONFIGURATION_BITS_SIZE 4 | ||
110 | #define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5 | ||
111 | #define VC4_PACKET_POINT_SIZE_SIZE 5 | ||
112 | #define VC4_PACKET_LINE_WIDTH_SIZE 5 | ||
113 | #define VC4_PACKET_RHT_X_BOUNDARY_SIZE 3 | ||
114 | #define VC4_PACKET_DEPTH_OFFSET_SIZE 5 | ||
115 | #define VC4_PACKET_CLIP_WINDOW_SIZE 9 | ||
116 | #define VC4_PACKET_VIEWPORT_OFFSET_SIZE 5 | ||
117 | #define VC4_PACKET_Z_CLIPPING_SIZE 9 | ||
118 | #define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9 | ||
119 | #define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9 | ||
120 | #define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE 16 | ||
121 | #define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE 11 | ||
122 | #define VC4_PACKET_CLEAR_COLORS_SIZE 14 | ||
123 | #define VC4_PACKET_TILE_COORDINATES_SIZE 3 | ||
124 | #define VC4_PACKET_GEM_HANDLES_SIZE 9 | ||
125 | |||
126 | #define VC4_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) | ||
127 | /* Using the GNU statement expression extension */ | ||
128 | #define VC4_SET_FIELD(value, field) \ | ||
129 | ({ \ | ||
130 | uint32_t fieldval = (value) << field ## _SHIFT; \ | ||
131 | assert((fieldval & ~ field ## _MASK) == 0); \ | ||
132 | fieldval & field ## _MASK; \ | ||
133 | }) | ||
134 | |||
135 | #define VC4_GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) | ||
136 | |||
137 | /** @{ | ||
138 | * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and | ||
139 | * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. | ||
140 | */ | ||
141 | #define VC4_TILING_FORMAT_LINEAR 0 | ||
142 | #define VC4_TILING_FORMAT_T 1 | ||
143 | #define VC4_TILING_FORMAT_LT 2 | ||
144 | /** @} */ | ||
145 | |||
146 | /** @{ | ||
147 | * | ||
148 | * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and | ||
149 | * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. | ||
150 | */ | ||
151 | #define VC4_LOADSTORE_FULL_RES_EOF (1 << 3) | ||
152 | #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2) | ||
153 | #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1) | ||
154 | #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0) | ||
155 | |||
156 | /** @{ | ||
157 | * | ||
158 | * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and | ||
159 | * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) | ||
160 | */ | ||
161 | |||
162 | #define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3) | ||
163 | #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2) | ||
164 | #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1) | ||
165 | #define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0) | ||
166 | |||
167 | /** @} */ | ||
168 | |||
169 | /** @{ | ||
170 | * | ||
171 | * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and | ||
172 | * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL | ||
173 | */ | ||
174 | #define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15) | ||
175 | #define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14) | ||
176 | #define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13) | ||
177 | #define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12) | ||
178 | |||
179 | #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) | ||
180 | #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 | ||
181 | #define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0 | ||
182 | #define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1 | ||
183 | #define VC4_LOADSTORE_TILE_BUFFER_BGR565 2 | ||
184 | /** @} */ | ||
185 | |||
186 | /** @{ | ||
187 | * | ||
188 | * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and | ||
189 | * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL | ||
190 | */ | ||
191 | #define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6) | ||
192 | #define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6 | ||
193 | #define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6) | ||
194 | #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6) | ||
195 | #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6) | ||
196 | |||
197 | /** The values of the field are VC4_TILING_FORMAT_* */ | ||
198 | #define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4) | ||
199 | #define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4 | ||
200 | |||
201 | #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0) | ||
202 | #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0 | ||
203 | #define VC4_LOADSTORE_TILE_BUFFER_NONE 0 | ||
204 | #define VC4_LOADSTORE_TILE_BUFFER_COLOR 1 | ||
205 | #define VC4_LOADSTORE_TILE_BUFFER_ZS 2 | ||
206 | #define VC4_LOADSTORE_TILE_BUFFER_Z 3 | ||
207 | #define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4 | ||
208 | #define VC4_LOADSTORE_TILE_BUFFER_FULL 5 | ||
209 | /** @} */ | ||
210 | |||
211 | #define VC4_INDEX_BUFFER_U8 (0 << 4) | ||
212 | #define VC4_INDEX_BUFFER_U16 (1 << 4) | ||
213 | |||
214 | /* This flag is only present in NV shader state. */ | ||
215 | #define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3) | ||
216 | #define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2) | ||
217 | #define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1) | ||
218 | #define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0) | ||
219 | |||
220 | /** @{ byte 2 of config bits. */ | ||
221 | #define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1) | ||
222 | #define VC4_CONFIG_BITS_EARLY_Z (1 << 0) | ||
223 | /** @} */ | ||
224 | |||
225 | /** @{ byte 1 of config bits. */ | ||
226 | #define VC4_CONFIG_BITS_Z_UPDATE (1 << 7) | ||
227 | /** same values in this 3-bit field as PIPE_FUNC_* */ | ||
228 | #define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 | ||
229 | #define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3) | ||
230 | |||
231 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) | ||
232 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) | ||
233 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) | ||
234 | #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) | ||
235 | |||
236 | #define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0) | ||
237 | /** @} */ | ||
238 | |||
239 | /** @{ byte 0 of config bits. */ | ||
240 | #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6) | ||
241 | #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) | ||
242 | #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) | ||
243 | #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_MASK (3 << 6) | ||
244 | |||
245 | #define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4) | ||
246 | #define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3) | ||
247 | #define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2) | ||
248 | #define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1) | ||
249 | #define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0) | ||
250 | /** @} */ | ||
251 | |||
252 | /** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ | ||
253 | #define VC4_BIN_CONFIG_DB_NON_MS (1 << 7) | ||
254 | |||
255 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) | ||
256 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 | ||
257 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 0 | ||
258 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64 1 | ||
259 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128 2 | ||
260 | #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256 3 | ||
261 | |||
262 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3) | ||
263 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3 | ||
264 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32 0 | ||
265 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64 1 | ||
266 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 | ||
267 | #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 | ||
268 | |||
269 | #define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2) | ||
270 | #define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1) | ||
271 | #define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0) | ||
272 | /** @} */ | ||
273 | |||
274 | /** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ | ||
275 | #define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12) | ||
276 | #define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11) | ||
277 | #define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10) | ||
278 | #define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9) | ||
279 | #define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8) | ||
280 | |||
281 | /** The values of the field are VC4_TILING_FORMAT_* */ | ||
282 | #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) | ||
283 | #define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6 | ||
284 | |||
285 | #define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4) | ||
286 | #define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4) | ||
287 | #define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4) | ||
288 | #define VC4_RENDER_CONFIG_DECIMATE_MODE_MASK (3 << 4) | ||
289 | |||
290 | #define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2) | ||
291 | #define VC4_RENDER_CONFIG_FORMAT_SHIFT 2 | ||
292 | #define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0 | ||
293 | #define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 | ||
294 | #define VC4_RENDER_CONFIG_FORMAT_BGR565 2 | ||
295 | |||
296 | #define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1) | ||
297 | #define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0) | ||
298 | |||
299 | #define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) | ||
300 | #define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) | ||
301 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS (0 << 0) | ||
302 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES (1 << 0) | ||
303 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES (2 << 0) | ||
304 | #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) | ||
305 | |||
306 | enum vc4_texture_data_type { | ||
307 | VC4_TEXTURE_TYPE_RGBA8888 = 0, | ||
308 | VC4_TEXTURE_TYPE_RGBX8888 = 1, | ||
309 | VC4_TEXTURE_TYPE_RGBA4444 = 2, | ||
310 | VC4_TEXTURE_TYPE_RGBA5551 = 3, | ||
311 | VC4_TEXTURE_TYPE_RGB565 = 4, | ||
312 | VC4_TEXTURE_TYPE_LUMINANCE = 5, | ||
313 | VC4_TEXTURE_TYPE_ALPHA = 6, | ||
314 | VC4_TEXTURE_TYPE_LUMALPHA = 7, | ||
315 | VC4_TEXTURE_TYPE_ETC1 = 8, | ||
316 | VC4_TEXTURE_TYPE_S16F = 9, | ||
317 | VC4_TEXTURE_TYPE_S8 = 10, | ||
318 | VC4_TEXTURE_TYPE_S16 = 11, | ||
319 | VC4_TEXTURE_TYPE_BW1 = 12, | ||
320 | VC4_TEXTURE_TYPE_A4 = 13, | ||
321 | VC4_TEXTURE_TYPE_A1 = 14, | ||
322 | VC4_TEXTURE_TYPE_RGBA64 = 15, | ||
323 | VC4_TEXTURE_TYPE_RGBA32R = 16, | ||
324 | VC4_TEXTURE_TYPE_YUV422R = 17, | ||
325 | }; | ||
326 | |||
327 | #define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) | ||
328 | #define VC4_TEX_P0_OFFSET_SHIFT 12 | ||
329 | #define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10) | ||
330 | #define VC4_TEX_P0_CSWIZ_SHIFT 10 | ||
331 | #define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9) | ||
332 | #define VC4_TEX_P0_CMMODE_SHIFT 9 | ||
333 | #define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8) | ||
334 | #define VC4_TEX_P0_FLIPY_SHIFT 8 | ||
335 | #define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4) | ||
336 | #define VC4_TEX_P0_TYPE_SHIFT 4 | ||
337 | #define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0) | ||
338 | #define VC4_TEX_P0_MIPLVLS_SHIFT 0 | ||
339 | |||
340 | #define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31) | ||
341 | #define VC4_TEX_P1_TYPE4_SHIFT 31 | ||
342 | #define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20) | ||
343 | #define VC4_TEX_P1_HEIGHT_SHIFT 20 | ||
344 | #define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19) | ||
345 | #define VC4_TEX_P1_ETCFLIP_SHIFT 19 | ||
346 | #define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8) | ||
347 | #define VC4_TEX_P1_WIDTH_SHIFT 8 | ||
348 | |||
349 | #define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7) | ||
350 | #define VC4_TEX_P1_MAGFILT_SHIFT 7 | ||
351 | # define VC4_TEX_P1_MAGFILT_LINEAR 0 | ||
352 | # define VC4_TEX_P1_MAGFILT_NEAREST 1 | ||
353 | |||
354 | #define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4) | ||
355 | #define VC4_TEX_P1_MINFILT_SHIFT 4 | ||
356 | # define VC4_TEX_P1_MINFILT_LINEAR 0 | ||
357 | # define VC4_TEX_P1_MINFILT_NEAREST 1 | ||
358 | # define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR 2 | ||
359 | # define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN 3 | ||
360 | # define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR 4 | ||
361 | # define VC4_TEX_P1_MINFILT_LIN_MIP_LIN 5 | ||
362 | |||
363 | #define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2) | ||
364 | #define VC4_TEX_P1_WRAP_T_SHIFT 2 | ||
365 | #define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0) | ||
366 | #define VC4_TEX_P1_WRAP_S_SHIFT 0 | ||
367 | # define VC4_TEX_P1_WRAP_REPEAT 0 | ||
368 | # define VC4_TEX_P1_WRAP_CLAMP 1 | ||
369 | # define VC4_TEX_P1_WRAP_MIRROR 2 | ||
370 | # define VC4_TEX_P1_WRAP_BORDER 3 | ||
371 | |||
372 | #define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30) | ||
373 | #define VC4_TEX_P2_PTYPE_SHIFT 30 | ||
374 | # define VC4_TEX_P2_PTYPE_IGNORED 0 | ||
375 | # define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE 1 | ||
376 | # define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS 2 | ||
377 | # define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS 3 | ||
378 | |||
379 | /* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */ | ||
380 | #define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12) | ||
381 | #define VC4_TEX_P2_CMST_SHIFT 12 | ||
382 | #define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0) | ||
383 | #define VC4_TEX_P2_BSLOD_SHIFT 0 | ||
384 | |||
385 | /* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */ | ||
386 | #define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12) | ||
387 | #define VC4_TEX_P2_CHEIGHT_SHIFT 12 | ||
388 | #define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0) | ||
389 | #define VC4_TEX_P2_CWIDTH_SHIFT 0 | ||
390 | |||
391 | /* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */ | ||
392 | #define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12) | ||
393 | #define VC4_TEX_P2_CYOFF_SHIFT 12 | ||
394 | #define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0) | ||
395 | #define VC4_TEX_P2_CXOFF_SHIFT 0 | ||
396 | |||
397 | #endif /* VC4_PACKET_H */ | ||
diff --git a/vc4/vc4_qpu_defines.h b/vc4/vc4_qpu_defines.h new file mode 100644 index 00000000..26fcf505 --- /dev/null +++ b/vc4/vc4_qpu_defines.h | |||
@@ -0,0 +1,274 @@ | |||
1 | /* | ||
2 | * Copyright © 2014 Broadcom | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice (including the next | ||
12 | * paragraph) shall be included in all copies or substantial portions of the | ||
13 | * Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | ||
21 | * IN THE SOFTWARE. | ||
22 | */ | ||
23 | |||
24 | #ifndef VC4_QPU_DEFINES_H | ||
25 | #define VC4_QPU_DEFINES_H | ||
26 | |||
27 | enum qpu_op_add { | ||
28 | QPU_A_NOP, | ||
29 | QPU_A_FADD, | ||
30 | QPU_A_FSUB, | ||
31 | QPU_A_FMIN, | ||
32 | QPU_A_FMAX, | ||
33 | QPU_A_FMINABS, | ||
34 | QPU_A_FMAXABS, | ||
35 | QPU_A_FTOI, | ||
36 | QPU_A_ITOF, | ||
37 | QPU_A_ADD = 12, | ||
38 | QPU_A_SUB, | ||
39 | QPU_A_SHR, | ||
40 | QPU_A_ASR, | ||
41 | QPU_A_ROR, | ||
42 | QPU_A_SHL, | ||
43 | QPU_A_MIN, | ||
44 | QPU_A_MAX, | ||
45 | QPU_A_AND, | ||
46 | QPU_A_OR, | ||
47 | QPU_A_XOR, | ||
48 | QPU_A_NOT, | ||
49 | QPU_A_CLZ, | ||
50 | QPU_A_V8ADDS = 30, | ||
51 | QPU_A_V8SUBS = 31, | ||
52 | }; | ||
53 | |||
54 | enum qpu_op_mul { | ||
55 | QPU_M_NOP, | ||
56 | QPU_M_FMUL, | ||
57 | QPU_M_MUL24, | ||
58 | QPU_M_V8MULD, | ||
59 | QPU_M_V8MIN, | ||
60 | QPU_M_V8MAX, | ||
61 | QPU_M_V8ADDS, | ||
62 | QPU_M_V8SUBS, | ||
63 | }; | ||
64 | |||
65 | enum qpu_raddr { | ||
66 | QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ | ||
67 | /* 0-31 are the plain regfile a or b fields */ | ||
68 | QPU_R_UNIF = 32, | ||
69 | QPU_R_VARY = 35, | ||
70 | QPU_R_ELEM_QPU = 38, | ||
71 | QPU_R_NOP, | ||
72 | QPU_R_XY_PIXEL_COORD = 41, | ||
73 | QPU_R_MS_REV_FLAGS = 42, | ||
74 | QPU_R_VPM = 48, | ||
75 | QPU_R_VPM_LD_BUSY, | ||
76 | QPU_R_VPM_LD_WAIT, | ||
77 | QPU_R_MUTEX_ACQUIRE, | ||
78 | }; | ||
79 | |||
80 | enum qpu_waddr { | ||
81 | /* 0-31 are the plain regfile a or b fields */ | ||
82 | QPU_W_ACC0 = 32, /* aka r0 */ | ||
83 | QPU_W_ACC1, | ||
84 | QPU_W_ACC2, | ||
85 | QPU_W_ACC3, | ||
86 | QPU_W_TMU_NOSWAP, | ||
87 | QPU_W_ACC5, | ||
88 | QPU_W_HOST_INT, | ||
89 | QPU_W_NOP, | ||
90 | QPU_W_UNIFORMS_ADDRESS, | ||
91 | QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ | ||
92 | QPU_W_MS_FLAGS = 42, | ||
93 | QPU_W_REV_FLAG = 42, | ||
94 | QPU_W_TLB_STENCIL_SETUP = 43, | ||
95 | QPU_W_TLB_Z, | ||
96 | QPU_W_TLB_COLOR_MS, | ||
97 | QPU_W_TLB_COLOR_ALL, | ||
98 | QPU_W_TLB_ALPHA_MASK, | ||
99 | QPU_W_VPM, | ||
100 | QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ | ||
101 | QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ | ||
102 | QPU_W_MUTEX_RELEASE, | ||
103 | QPU_W_SFU_RECIP, | ||
104 | QPU_W_SFU_RECIPSQRT, | ||
105 | QPU_W_SFU_EXP, | ||
106 | QPU_W_SFU_LOG, | ||
107 | QPU_W_TMU0_S, | ||
108 | QPU_W_TMU0_T, | ||
109 | QPU_W_TMU0_R, | ||
110 | QPU_W_TMU0_B, | ||
111 | QPU_W_TMU1_S, | ||
112 | QPU_W_TMU1_T, | ||
113 | QPU_W_TMU1_R, | ||
114 | QPU_W_TMU1_B, | ||
115 | }; | ||
116 | |||
117 | enum qpu_sig_bits { | ||
118 | QPU_SIG_SW_BREAKPOINT, | ||
119 | QPU_SIG_NONE, | ||
120 | QPU_SIG_THREAD_SWITCH, | ||
121 | QPU_SIG_PROG_END, | ||
122 | QPU_SIG_WAIT_FOR_SCOREBOARD, | ||
123 | QPU_SIG_SCOREBOARD_UNLOCK, | ||
124 | QPU_SIG_LAST_THREAD_SWITCH, | ||
125 | QPU_SIG_COVERAGE_LOAD, | ||
126 | QPU_SIG_COLOR_LOAD, | ||
127 | QPU_SIG_COLOR_LOAD_END, | ||
128 | QPU_SIG_LOAD_TMU0, | ||
129 | QPU_SIG_LOAD_TMU1, | ||
130 | QPU_SIG_ALPHA_MASK_LOAD, | ||
131 | QPU_SIG_SMALL_IMM, | ||
132 | QPU_SIG_LOAD_IMM, | ||
133 | QPU_SIG_BRANCH | ||
134 | }; | ||
135 | |||
136 | enum qpu_mux { | ||
137 | /* hardware mux values */ | ||
138 | QPU_MUX_R0, | ||
139 | QPU_MUX_R1, | ||
140 | QPU_MUX_R2, | ||
141 | QPU_MUX_R3, | ||
142 | QPU_MUX_R4, | ||
143 | QPU_MUX_R5, | ||
144 | QPU_MUX_A, | ||
145 | QPU_MUX_B, | ||
146 | |||
147 | /** | ||
148 | * Non-hardware mux value, stores a small immediate field to be | ||
149 | * programmed into raddr_b in the qpu_reg.index. | ||
150 | */ | ||
151 | QPU_MUX_SMALL_IMM, | ||
152 | }; | ||
153 | |||
154 | enum qpu_cond { | ||
155 | QPU_COND_NEVER, | ||
156 | QPU_COND_ALWAYS, | ||
157 | QPU_COND_ZS, | ||
158 | QPU_COND_ZC, | ||
159 | QPU_COND_NS, | ||
160 | QPU_COND_NC, | ||
161 | QPU_COND_CS, | ||
162 | QPU_COND_CC, | ||
163 | }; | ||
164 | |||
165 | enum qpu_pack_mul { | ||
166 | QPU_PACK_MUL_NOP, | ||
167 | QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */ | ||
168 | QPU_PACK_MUL_8A, | ||
169 | QPU_PACK_MUL_8B, | ||
170 | QPU_PACK_MUL_8C, | ||
171 | QPU_PACK_MUL_8D, | ||
172 | }; | ||
173 | |||
174 | enum qpu_pack_a { | ||
175 | QPU_PACK_A_NOP, | ||
176 | /* convert to 16 bit float if float input, or to int16. */ | ||
177 | QPU_PACK_A_16A, | ||
178 | QPU_PACK_A_16B, | ||
179 | /* replicated to each 8 bits of the 32-bit dst. */ | ||
180 | QPU_PACK_A_8888, | ||
181 | /* Convert to 8-bit unsigned int. */ | ||
182 | QPU_PACK_A_8A, | ||
183 | QPU_PACK_A_8B, | ||
184 | QPU_PACK_A_8C, | ||
185 | QPU_PACK_A_8D, | ||
186 | |||
187 | /* Saturating variants of the previous instructions. */ | ||
188 | QPU_PACK_A_32_SAT, /* int-only */ | ||
189 | QPU_PACK_A_16A_SAT, /* int or float */ | ||
190 | QPU_PACK_A_16B_SAT, | ||
191 | QPU_PACK_A_8888_SAT, | ||
192 | QPU_PACK_A_8A_SAT, | ||
193 | QPU_PACK_A_8B_SAT, | ||
194 | QPU_PACK_A_8C_SAT, | ||
195 | QPU_PACK_A_8D_SAT, | ||
196 | }; | ||
197 | |||
198 | enum qpu_unpack { | ||
199 | QPU_UNPACK_NOP, | ||
200 | QPU_UNPACK_16A, | ||
201 | QPU_UNPACK_16B, | ||
202 | QPU_UNPACK_8D_REP, | ||
203 | QPU_UNPACK_8A, | ||
204 | QPU_UNPACK_8B, | ||
205 | QPU_UNPACK_8C, | ||
206 | QPU_UNPACK_8D, | ||
207 | }; | ||
208 | |||
209 | #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) | ||
210 | /* Using the GNU statement expression extension */ | ||
211 | #define QPU_SET_FIELD(value, field) \ | ||
212 | ({ \ | ||
213 | uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ | ||
214 | assert((fieldval & ~ field ## _MASK) == 0); \ | ||
215 | fieldval & field ## _MASK; \ | ||
216 | }) | ||
217 | |||
218 | #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) | ||
219 | |||
220 | #define QPU_UPDATE_FIELD(inst, value, field) \ | ||
221 | (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field)) | ||
222 | |||
223 | #define QPU_SIG_SHIFT 60 | ||
224 | #define QPU_SIG_MASK QPU_MASK(63, 60) | ||
225 | |||
226 | #define QPU_UNPACK_SHIFT 57 | ||
227 | #define QPU_UNPACK_MASK QPU_MASK(59, 57) | ||
228 | |||
229 | /** | ||
230 | * If set, the pack field means PACK_MUL or R4 packing, instead of normal | ||
231 | * regfile a packing. | ||
232 | */ | ||
233 | #define QPU_PM ((uint64_t)1 << 56) | ||
234 | |||
235 | #define QPU_PACK_SHIFT 52 | ||
236 | #define QPU_PACK_MASK QPU_MASK(55, 52) | ||
237 | |||
238 | #define QPU_COND_ADD_SHIFT 49 | ||
239 | #define QPU_COND_ADD_MASK QPU_MASK(51, 49) | ||
240 | #define QPU_COND_MUL_SHIFT 46 | ||
241 | #define QPU_COND_MUL_MASK QPU_MASK(48, 46) | ||
242 | |||
243 | #define QPU_SF ((uint64_t)1 << 45) | ||
244 | |||
245 | #define QPU_WADDR_ADD_SHIFT 38 | ||
246 | #define QPU_WADDR_ADD_MASK QPU_MASK(43, 38) | ||
247 | #define QPU_WADDR_MUL_SHIFT 32 | ||
248 | #define QPU_WADDR_MUL_MASK QPU_MASK(37, 32) | ||
249 | |||
250 | #define QPU_OP_MUL_SHIFT 29 | ||
251 | #define QPU_OP_MUL_MASK QPU_MASK(31, 29) | ||
252 | |||
253 | #define QPU_RADDR_A_SHIFT 18 | ||
254 | #define QPU_RADDR_A_MASK QPU_MASK(23, 18) | ||
255 | #define QPU_RADDR_B_SHIFT 12 | ||
256 | #define QPU_RADDR_B_MASK QPU_MASK(17, 12) | ||
257 | #define QPU_SMALL_IMM_SHIFT 12 | ||
258 | #define QPU_SMALL_IMM_MASK QPU_MASK(17, 12) | ||
259 | |||
260 | #define QPU_ADD_A_SHIFT 9 | ||
261 | #define QPU_ADD_A_MASK QPU_MASK(11, 9) | ||
262 | #define QPU_ADD_B_SHIFT 6 | ||
263 | #define QPU_ADD_B_MASK QPU_MASK(8, 6) | ||
264 | #define QPU_MUL_A_SHIFT 3 | ||
265 | #define QPU_MUL_A_MASK QPU_MASK(5, 3) | ||
266 | #define QPU_MUL_B_SHIFT 0 | ||
267 | #define QPU_MUL_B_MASK QPU_MASK(2, 0) | ||
268 | |||
269 | #define QPU_WS ((uint64_t)1 << 44) | ||
270 | |||
271 | #define QPU_OP_ADD_SHIFT 24 | ||
272 | #define QPU_OP_ADD_MASK QPU_MASK(28, 24) | ||
273 | |||
274 | #endif /* VC4_QPU_DEFINES_H */ | ||