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authorIan Romanick2013-11-15 12:24:43 -0600
committerIan Romanick2013-11-15 13:31:49 -0600
commit5a41b025042c42788977e67aea8d1bf3b59baae4 (patch)
tree1abd805a37014e5dcda2c5d75d7c989c46f66998
parent1a84eea45bf9d3915698a04199c594a63fcca4a2 (diff)
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intel: Add support for GPU reset status query ioctl
I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. This ioctl is in the drm-intel-next tree as b635991. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. v4: Import the actual changes from the kernel i915_drm.h. Only comments on some fields of drm_i915_reset_stats differed. There are still some deltas between the kernel i915_drm.h and the one in libdrm, but those can be resolved in other patches. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3] Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--include/drm/i915_drm.h19
-rw-r--r--intel/intel_bufmgr.h5
-rw-r--r--intel/intel_bufmgr_gem.c34
3 files changed, 58 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index aa983f34..c1914d61 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -198,6 +198,7 @@ typedef struct _drm_i915_sarea {
198#define DRM_I915_GEM_SET_CACHEING 0x2f 198#define DRM_I915_GEM_SET_CACHEING 0x2f
199#define DRM_I915_GEM_GET_CACHEING 0x30 199#define DRM_I915_GEM_GET_CACHEING 0x30
200#define DRM_I915_REG_READ 0x31 200#define DRM_I915_REG_READ 0x31
201#define DRM_I915_GET_RESET_STATS 0x32
201 202
202#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 203#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
203#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 204#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -247,6 +248,7 @@ typedef struct _drm_i915_sarea {
247#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 248#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
248#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 249#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
249#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 250#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
251#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
250 252
251/* Allow drivers to submit batchbuffers directly to hardware, relying 253/* Allow drivers to submit batchbuffers directly to hardware, relying
252 * on the security mechanisms provided by hardware. 254 * on the security mechanisms provided by hardware.
@@ -943,4 +945,21 @@ struct drm_i915_reg_read {
943 __u64 offset; 945 __u64 offset;
944 __u64 val; /* Return value */ 946 __u64 val; /* Return value */
945}; 947};
948
949struct drm_i915_reset_stats {
950 __u32 ctx_id;
951 __u32 flags;
952
953 /* All resets since boot/module reload, for all contexts */
954 __u32 reset_count;
955
956 /* Number of batches lost when active in GPU, for this context */
957 __u32 batch_active;
958
959 /* Number of batches lost pending for execution, for this context */
960 __u32 batch_pending;
961
962 __u32 pad;
963};
964
946#endif /* _I915_DRM_H_ */ 965#endif /* _I915_DRM_H_ */
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 15f818e7..2eb9742b 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -248,6 +248,11 @@ int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
248 uint32_t offset, 248 uint32_t offset,
249 uint64_t *result); 249 uint64_t *result);
250 250
251int drm_intel_get_reset_stats(drm_intel_context *ctx,
252 uint32_t *reset_count,
253 uint32_t *active,
254 uint32_t *pending);
255
251/** @{ Compatibility defines to keep old code building despite the symbol rename 256/** @{ Compatibility defines to keep old code building despite the symbol rename
252 * from dri_* to drm_intel_* 257 * from dri_* to drm_intel_*
253 */ 258 */
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 029ca5d8..df6fcec4 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3021,6 +3021,40 @@ drm_intel_gem_context_destroy(drm_intel_context *ctx)
3021} 3021}
3022 3022
3023int 3023int
3024drm_intel_get_reset_stats(drm_intel_context *ctx,
3025 uint32_t *reset_count,
3026 uint32_t *active,
3027 uint32_t *pending)
3028{
3029 drm_intel_bufmgr_gem *bufmgr_gem;
3030 struct drm_i915_reset_stats stats;
3031 int ret;
3032
3033 if (ctx == NULL)
3034 return -EINVAL;
3035
3036 VG_CLEAR(stats);
3037
3038 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3039 stats.ctx_id = ctx->ctx_id;
3040 ret = drmIoctl(bufmgr_gem->fd,
3041 DRM_IOCTL_I915_GET_RESET_STATS,
3042 &stats);
3043 if (ret == 0) {
3044 if (reset_count != NULL)
3045 *reset_count = stats.reset_count;
3046
3047 if (active != NULL)
3048 *active = stats.batch_active;
3049
3050 if (pending != NULL)
3051 *pending = stats.batch_pending;
3052 }
3053
3054 return ret;
3055}
3056
3057int
3024drm_intel_reg_read(drm_intel_bufmgr *bufmgr, 3058drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3025 uint32_t offset, 3059 uint32_t offset,
3026 uint64_t *result) 3060 uint64_t *result)