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authorKristian Høgsberg2009-11-17 08:23:59 -0600
committerKristian Høgsberg2009-11-17 09:54:07 -0600
commit2b42af9a2fd8e35e920d61a212ce6b9c85354289 (patch)
tree8971e0bb76527e21ae1d37ea8dcf830155581230 /include/drm/i915_drm.h
parenta99680384ad3daaceee05b3b40dc492cf0e52a0f (diff)
downloadexternal-libgbm-2b42af9a2fd8e35e920d61a212ce6b9c85354289.tar.gz
external-libgbm-2b42af9a2fd8e35e920d61a212ce6b9c85354289.tar.xz
external-libgbm-2b42af9a2fd8e35e920d61a212ce6b9c85354289.zip
Copy headers from kernel v2.6.32-rc6-130-g5b8f0be
Diffstat (limited to 'include/drm/i915_drm.h')
-rw-r--r--include/drm/i915_drm.h760
1 files changed, 760 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
new file mode 100644
index 00000000..3f88d824
--- /dev/null
+++ b/include/drm/i915_drm.h
@@ -0,0 +1,760 @@
1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30/* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
32 */
33#include <linux/types.h>
34#include "drm.h"
35
36/* Each region is a minimum of 16k, and there are at most 255 of them.
37 */
38#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40#define I915_LOG_MIN_TEX_REGION_SIZE 14
41
42typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64} drm_i915_init_t;
65
66typedef struct _drm_i915_sarea {
67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
72 int texAge;
73 int pf_enabled; /* is pageflipping allowed? */
74 int pf_active;
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
77 int width, height; /* screen size in pixels */
78
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
82
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
86
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
90
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation; /* 0, 90, 180 or 270 */
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
101
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
107
108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
116
117 /* fill out some space for old userspace triple buffer */
118 drm_handle_t unused_handle;
119 __u32 unused1, unused2, unused3;
120
121 /* buffer object handles for static buffers. May change
122 * over the lifetime of the client.
123 */
124 __u32 front_bo_handle;
125 __u32 back_bo_handle;
126 __u32 unused_bo_handle;
127 __u32 depth_bo_handle;
128
129} drm_i915_sarea_t;
130
131/* due to userspace building against these headers we need some compat here */
132#define planeA_x pipeA_x
133#define planeA_y pipeA_y
134#define planeA_w pipeA_w
135#define planeA_h pipeA_h
136#define planeB_x pipeB_x
137#define planeB_y pipeB_y
138#define planeB_w pipeB_w
139#define planeB_h pipeB_h
140
141/* Flags for perf_boxes
142 */
143#define I915_BOX_RING_EMPTY 0x1
144#define I915_BOX_FLIP 0x2
145#define I915_BOX_WAIT 0x4
146#define I915_BOX_TEXTURE_LOAD 0x8
147#define I915_BOX_LOST_CONTEXT 0x10
148
149/* I915 specific ioctls
150 * The device specific ioctl range is 0x40 to 0x79.
151 */
152#define DRM_I915_INIT 0x00
153#define DRM_I915_FLUSH 0x01
154#define DRM_I915_FLIP 0x02
155#define DRM_I915_BATCHBUFFER 0x03
156#define DRM_I915_IRQ_EMIT 0x04
157#define DRM_I915_IRQ_WAIT 0x05
158#define DRM_I915_GETPARAM 0x06
159#define DRM_I915_SETPARAM 0x07
160#define DRM_I915_ALLOC 0x08
161#define DRM_I915_FREE 0x09
162#define DRM_I915_INIT_HEAP 0x0a
163#define DRM_I915_CMDBUFFER 0x0b
164#define DRM_I915_DESTROY_HEAP 0x0c
165#define DRM_I915_SET_VBLANK_PIPE 0x0d
166#define DRM_I915_GET_VBLANK_PIPE 0x0e
167#define DRM_I915_VBLANK_SWAP 0x0f
168#define DRM_I915_HWS_ADDR 0x11
169#define DRM_I915_GEM_INIT 0x13
170#define DRM_I915_GEM_EXECBUFFER 0x14
171#define DRM_I915_GEM_PIN 0x15
172#define DRM_I915_GEM_UNPIN 0x16
173#define DRM_I915_GEM_BUSY 0x17
174#define DRM_I915_GEM_THROTTLE 0x18
175#define DRM_I915_GEM_ENTERVT 0x19
176#define DRM_I915_GEM_LEAVEVT 0x1a
177#define DRM_I915_GEM_CREATE 0x1b
178#define DRM_I915_GEM_PREAD 0x1c
179#define DRM_I915_GEM_PWRITE 0x1d
180#define DRM_I915_GEM_MMAP 0x1e
181#define DRM_I915_GEM_SET_DOMAIN 0x1f
182#define DRM_I915_GEM_SW_FINISH 0x20
183#define DRM_I915_GEM_SET_TILING 0x21
184#define DRM_I915_GEM_GET_TILING 0x22
185#define DRM_I915_GEM_GET_APERTURE 0x23
186#define DRM_I915_GEM_MMAP_GTT 0x24
187#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
188#define DRM_I915_GEM_MADVISE 0x26
189#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
190#define DRM_I915_OVERLAY_ATTRS 0x28
191
192#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
193#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
194#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
195#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
196#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
197#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
198#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
199#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
200#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
201#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
202#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
203#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
204#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
205#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
206#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
207#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
208#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
209#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
210#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
211#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
212#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
213#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
214#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
215#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
216#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
217#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
218#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
219#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
220#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
221#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
222#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
223#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
224#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
225#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
226#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
227#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
228#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
229#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
230
231/* Allow drivers to submit batchbuffers directly to hardware, relying
232 * on the security mechanisms provided by hardware.
233 */
234typedef struct drm_i915_batchbuffer {
235 int start; /* agp offset */
236 int used; /* nr bytes in use */
237 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
238 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
239 int num_cliprects; /* mulitpass with multiple cliprects? */
240 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
241} drm_i915_batchbuffer_t;
242
243/* As above, but pass a pointer to userspace buffer which can be
244 * validated by the kernel prior to sending to hardware.
245 */
246typedef struct _drm_i915_cmdbuffer {
247 char *buf; /* pointer to userspace command buffer */
248 int sz; /* nr bytes in buf */
249 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
250 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
251 int num_cliprects; /* mulitpass with multiple cliprects? */
252 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
253} drm_i915_cmdbuffer_t;
254
255/* Userspace can request & wait on irq's:
256 */
257typedef struct drm_i915_irq_emit {
258 int *irq_seq;
259} drm_i915_irq_emit_t;
260
261typedef struct drm_i915_irq_wait {
262 int irq_seq;
263} drm_i915_irq_wait_t;
264
265/* Ioctl to query kernel params:
266 */
267#define I915_PARAM_IRQ_ACTIVE 1
268#define I915_PARAM_ALLOW_BATCHBUFFER 2
269#define I915_PARAM_LAST_DISPATCH 3
270#define I915_PARAM_CHIPSET_ID 4
271#define I915_PARAM_HAS_GEM 5
272#define I915_PARAM_NUM_FENCES_AVAIL 6
273#define I915_PARAM_HAS_OVERLAY 7
274
275typedef struct drm_i915_getparam {
276 int param;
277 int *value;
278} drm_i915_getparam_t;
279
280/* Ioctl to set kernel params:
281 */
282#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
283#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
284#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
285#define I915_SETPARAM_NUM_USED_FENCES 4
286
287typedef struct drm_i915_setparam {
288 int param;
289 int value;
290} drm_i915_setparam_t;
291
292/* A memory manager for regions of shared memory:
293 */
294#define I915_MEM_REGION_AGP 1
295
296typedef struct drm_i915_mem_alloc {
297 int region;
298 int alignment;
299 int size;
300 int *region_offset; /* offset from start of fb or agp */
301} drm_i915_mem_alloc_t;
302
303typedef struct drm_i915_mem_free {
304 int region;
305 int region_offset;
306} drm_i915_mem_free_t;
307
308typedef struct drm_i915_mem_init_heap {
309 int region;
310 int size;
311 int start;
312} drm_i915_mem_init_heap_t;
313
314/* Allow memory manager to be torn down and re-initialized (eg on
315 * rotate):
316 */
317typedef struct drm_i915_mem_destroy_heap {
318 int region;
319} drm_i915_mem_destroy_heap_t;
320
321/* Allow X server to configure which pipes to monitor for vblank signals
322 */
323#define DRM_I915_VBLANK_PIPE_A 1
324#define DRM_I915_VBLANK_PIPE_B 2
325
326typedef struct drm_i915_vblank_pipe {
327 int pipe;
328} drm_i915_vblank_pipe_t;
329
330/* Schedule buffer swap at given vertical blank:
331 */
332typedef struct drm_i915_vblank_swap {
333 drm_drawable_t drawable;
334 enum drm_vblank_seq_type seqtype;
335 unsigned int sequence;
336} drm_i915_vblank_swap_t;
337
338typedef struct drm_i915_hws_addr {
339 __u64 addr;
340} drm_i915_hws_addr_t;
341
342struct drm_i915_gem_init {
343 /**
344 * Beginning offset in the GTT to be managed by the DRM memory
345 * manager.
346 */
347 __u64 gtt_start;
348 /**
349 * Ending offset in the GTT to be managed by the DRM memory
350 * manager.
351 */
352 __u64 gtt_end;
353};
354
355struct drm_i915_gem_create {
356 /**
357 * Requested size for the object.
358 *
359 * The (page-aligned) allocated size for the object will be returned.
360 */
361 __u64 size;
362 /**
363 * Returned handle for the object.
364 *
365 * Object handles are nonzero.
366 */
367 __u32 handle;
368 __u32 pad;
369};
370
371struct drm_i915_gem_pread {
372 /** Handle for the object being read. */
373 __u32 handle;
374 __u32 pad;
375 /** Offset into the object to read from */
376 __u64 offset;
377 /** Length of data to read */
378 __u64 size;
379 /**
380 * Pointer to write the data into.
381 *
382 * This is a fixed-size type for 32/64 compatibility.
383 */
384 __u64 data_ptr;
385};
386
387struct drm_i915_gem_pwrite {
388 /** Handle for the object being written to. */
389 __u32 handle;
390 __u32 pad;
391 /** Offset into the object to write to */
392 __u64 offset;
393 /** Length of data to write */
394 __u64 size;
395 /**
396 * Pointer to read the data from.
397 *
398 * This is a fixed-size type for 32/64 compatibility.
399 */
400 __u64 data_ptr;
401};
402
403struct drm_i915_gem_mmap {
404 /** Handle for the object being mapped. */
405 __u32 handle;
406 __u32 pad;
407 /** Offset in the object to map. */
408 __u64 offset;
409 /**
410 * Length of data to map.
411 *
412 * The value will be page-aligned.
413 */
414 __u64 size;
415 /**
416 * Returned pointer the data was mapped at.
417 *
418 * This is a fixed-size type for 32/64 compatibility.
419 */
420 __u64 addr_ptr;
421};
422
423struct drm_i915_gem_mmap_gtt {
424 /** Handle for the object being mapped. */
425 __u32 handle;
426 __u32 pad;
427 /**
428 * Fake offset to use for subsequent mmap call
429 *
430 * This is a fixed-size type for 32/64 compatibility.
431 */
432 __u64 offset;
433};
434
435struct drm_i915_gem_set_domain {
436 /** Handle for the object */
437 __u32 handle;
438
439 /** New read domains */
440 __u32 read_domains;
441
442 /** New write domain */
443 __u32 write_domain;
444};
445
446struct drm_i915_gem_sw_finish {
447 /** Handle for the object */
448 __u32 handle;
449};
450
451struct drm_i915_gem_relocation_entry {
452 /**
453 * Handle of the buffer being pointed to by this relocation entry.
454 *
455 * It's appealing to make this be an index into the mm_validate_entry
456 * list to refer to the buffer, but this allows the driver to create
457 * a relocation list for state buffers and not re-write it per
458 * exec using the buffer.
459 */
460 __u32 target_handle;
461
462 /**
463 * Value to be added to the offset of the target buffer to make up
464 * the relocation entry.
465 */
466 __u32 delta;
467
468 /** Offset in the buffer the relocation entry will be written into */
469 __u64 offset;
470
471 /**
472 * Offset value of the target buffer that the relocation entry was last
473 * written as.
474 *
475 * If the buffer has the same offset as last time, we can skip syncing
476 * and writing the relocation. This value is written back out by
477 * the execbuffer ioctl when the relocation is written.
478 */
479 __u64 presumed_offset;
480
481 /**
482 * Target memory domains read by this operation.
483 */
484 __u32 read_domains;
485
486 /**
487 * Target memory domains written by this operation.
488 *
489 * Note that only one domain may be written by the whole
490 * execbuffer operation, so that where there are conflicts,
491 * the application will get -EINVAL back.
492 */
493 __u32 write_domain;
494};
495
496/** @{
497 * Intel memory domains
498 *
499 * Most of these just align with the various caches in
500 * the system and are used to flush and invalidate as
501 * objects end up cached in different domains.
502 */
503/** CPU cache */
504#define I915_GEM_DOMAIN_CPU 0x00000001
505/** Render cache, used by 2D and 3D drawing */
506#define I915_GEM_DOMAIN_RENDER 0x00000002
507/** Sampler cache, used by texture engine */
508#define I915_GEM_DOMAIN_SAMPLER 0x00000004
509/** Command queue, used to load batch buffers */
510#define I915_GEM_DOMAIN_COMMAND 0x00000008
511/** Instruction cache, used by shader programs */
512#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
513/** Vertex address cache */
514#define I915_GEM_DOMAIN_VERTEX 0x00000020
515/** GTT domain - aperture and scanout */
516#define I915_GEM_DOMAIN_GTT 0x00000040
517/** @} */
518
519struct drm_i915_gem_exec_object {
520 /**
521 * User's handle for a buffer to be bound into the GTT for this
522 * operation.
523 */
524 __u32 handle;
525
526 /** Number of relocations to be performed on this buffer */
527 __u32 relocation_count;
528 /**
529 * Pointer to array of struct drm_i915_gem_relocation_entry containing
530 * the relocations to be performed in this buffer.
531 */
532 __u64 relocs_ptr;
533
534 /** Required alignment in graphics aperture */
535 __u64 alignment;
536
537 /**
538 * Returned value of the updated offset of the object, for future
539 * presumed_offset writes.
540 */
541 __u64 offset;
542};
543
544struct drm_i915_gem_execbuffer {
545 /**
546 * List of buffers to be validated with their relocations to be
547 * performend on them.
548 *
549 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
550 *
551 * These buffers must be listed in an order such that all relocations
552 * a buffer is performing refer to buffers that have already appeared
553 * in the validate list.
554 */
555 __u64 buffers_ptr;
556 __u32 buffer_count;
557
558 /** Offset in the batchbuffer to start execution from. */
559 __u32 batch_start_offset;
560 /** Bytes used in batchbuffer from batch_start_offset */
561 __u32 batch_len;
562 __u32 DR1;
563 __u32 DR4;
564 __u32 num_cliprects;
565 /** This is a struct drm_clip_rect *cliprects */
566 __u64 cliprects_ptr;
567};
568
569struct drm_i915_gem_pin {
570 /** Handle of the buffer to be pinned. */
571 __u32 handle;
572 __u32 pad;
573
574 /** alignment required within the aperture */
575 __u64 alignment;
576
577 /** Returned GTT offset of the buffer. */
578 __u64 offset;
579};
580
581struct drm_i915_gem_unpin {
582 /** Handle of the buffer to be unpinned. */
583 __u32 handle;
584 __u32 pad;
585};
586
587struct drm_i915_gem_busy {
588 /** Handle of the buffer to check for busy */
589 __u32 handle;
590
591 /** Return busy status (1 if busy, 0 if idle) */
592 __u32 busy;
593};
594
595#define I915_TILING_NONE 0
596#define I915_TILING_X 1
597#define I915_TILING_Y 2
598
599#define I915_BIT_6_SWIZZLE_NONE 0
600#define I915_BIT_6_SWIZZLE_9 1
601#define I915_BIT_6_SWIZZLE_9_10 2
602#define I915_BIT_6_SWIZZLE_9_11 3
603#define I915_BIT_6_SWIZZLE_9_10_11 4
604/* Not seen by userland */
605#define I915_BIT_6_SWIZZLE_UNKNOWN 5
606/* Seen by userland. */
607#define I915_BIT_6_SWIZZLE_9_17 6
608#define I915_BIT_6_SWIZZLE_9_10_17 7
609
610struct drm_i915_gem_set_tiling {
611 /** Handle of the buffer to have its tiling state updated */
612 __u32 handle;
613
614 /**
615 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
616 * I915_TILING_Y).
617 *
618 * This value is to be set on request, and will be updated by the
619 * kernel on successful return with the actual chosen tiling layout.
620 *
621 * The tiling mode may be demoted to I915_TILING_NONE when the system
622 * has bit 6 swizzling that can't be managed correctly by GEM.
623 *
624 * Buffer contents become undefined when changing tiling_mode.
625 */
626 __u32 tiling_mode;
627
628 /**
629 * Stride in bytes for the object when in I915_TILING_X or
630 * I915_TILING_Y.
631 */
632 __u32 stride;
633
634 /**
635 * Returned address bit 6 swizzling required for CPU access through
636 * mmap mapping.
637 */
638 __u32 swizzle_mode;
639};
640
641struct drm_i915_gem_get_tiling {
642 /** Handle of the buffer to get tiling state for. */
643 __u32 handle;
644
645 /**
646 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
647 * I915_TILING_Y).
648 */
649 __u32 tiling_mode;
650
651 /**
652 * Returned address bit 6 swizzling required for CPU access through
653 * mmap mapping.
654 */
655 __u32 swizzle_mode;
656};
657
658struct drm_i915_gem_get_aperture {
659 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
660 __u64 aper_size;
661
662 /**
663 * Available space in the aperture used by i915_gem_execbuffer, in
664 * bytes
665 */
666 __u64 aper_available_size;
667};
668
669struct drm_i915_get_pipe_from_crtc_id {
670 /** ID of CRTC being requested **/
671 __u32 crtc_id;
672
673 /** pipe of requested CRTC **/
674 __u32 pipe;
675};
676
677#define I915_MADV_WILLNEED 0
678#define I915_MADV_DONTNEED 1
679#define __I915_MADV_PURGED 2 /* internal state */
680
681struct drm_i915_gem_madvise {
682 /** Handle of the buffer to change the backing store advice */
683 __u32 handle;
684
685 /* Advice: either the buffer will be needed again in the near future,
686 * or wont be and could be discarded under memory pressure.
687 */
688 __u32 madv;
689
690 /** Whether the backing store still exists. */
691 __u32 retained;
692};
693
694/* flags */
695#define I915_OVERLAY_TYPE_MASK 0xff
696#define I915_OVERLAY_YUV_PLANAR 0x01
697#define I915_OVERLAY_YUV_PACKED 0x02
698#define I915_OVERLAY_RGB 0x03
699
700#define I915_OVERLAY_DEPTH_MASK 0xff00
701#define I915_OVERLAY_RGB24 0x1000
702#define I915_OVERLAY_RGB16 0x2000
703#define I915_OVERLAY_RGB15 0x3000
704#define I915_OVERLAY_YUV422 0x0100
705#define I915_OVERLAY_YUV411 0x0200
706#define I915_OVERLAY_YUV420 0x0300
707#define I915_OVERLAY_YUV410 0x0400
708
709#define I915_OVERLAY_SWAP_MASK 0xff0000
710#define I915_OVERLAY_NO_SWAP 0x000000
711#define I915_OVERLAY_UV_SWAP 0x010000
712#define I915_OVERLAY_Y_SWAP 0x020000
713#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
714
715#define I915_OVERLAY_FLAGS_MASK 0xff000000
716#define I915_OVERLAY_ENABLE 0x01000000
717
718struct drm_intel_overlay_put_image {
719 /* various flags and src format description */
720 __u32 flags;
721 /* source picture description */
722 __u32 bo_handle;
723 /* stride values and offsets are in bytes, buffer relative */
724 __u16 stride_Y; /* stride for packed formats */
725 __u16 stride_UV;
726 __u32 offset_Y; /* offset for packet formats */
727 __u32 offset_U;
728 __u32 offset_V;
729 /* in pixels */
730 __u16 src_width;
731 __u16 src_height;
732 /* to compensate the scaling factors for partially covered surfaces */
733 __u16 src_scan_width;
734 __u16 src_scan_height;
735 /* output crtc description */
736 __u32 crtc_id;
737 __u16 dst_x;
738 __u16 dst_y;
739 __u16 dst_width;
740 __u16 dst_height;
741};
742
743/* flags */
744#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
745#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
746struct drm_intel_overlay_attrs {
747 __u32 flags;
748 __u32 color_key;
749 __s32 brightness;
750 __u32 contrast;
751 __u32 saturation;
752 __u32 gamma0;
753 __u32 gamma1;
754 __u32 gamma2;
755 __u32 gamma3;
756 __u32 gamma4;
757 __u32 gamma5;
758};
759
760#endif /* _I915_DRM_H_ */