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authorEric Anholt2012-08-01 18:38:19 -0500
committerEric Anholt2012-08-10 11:48:05 -0500
commit934ea3b32127ea2a4ba5bf14228af6c60d3437b6 (patch)
tree3ec412a0b1581862e5e08a1fe824b769fa2ff467 /include/drm/i915_drm.h
parent71ebcf4ea372927ba8af425a229c4fa75dc45dd1 (diff)
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intel: Import updated i915_drm.h.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'include/drm/i915_drm.h')
-rw-r--r--include/drm/i915_drm.h33
1 files changed, 32 insertions, 1 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 5c8fabe0..7e9e9bd0 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -195,6 +195,9 @@ typedef struct _drm_i915_sarea {
195#define DRM_I915_GEM_WAIT 0x2c 195#define DRM_I915_GEM_WAIT 0x2c
196#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 196#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
197#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 197#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
198#define DRM_I915_GEM_SET_CACHEING 0x2f
199#define DRM_I915_GEM_GET_CACHEING 0x30
200#define DRM_I915_REG_READ 0x31
198 201
199#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 202#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
200#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 203#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -219,6 +222,8 @@ typedef struct _drm_i915_sarea {
219#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 222#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
220#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 223#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
221#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 224#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
225#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing)
226#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing)
222#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 227#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
223#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 228#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
224#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 229#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
@@ -241,6 +246,7 @@ typedef struct _drm_i915_sarea {
241#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 246#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
242#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 247#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
243#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 248#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
249#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
244 250
245/* Allow drivers to submit batchbuffers directly to hardware, relying 251/* Allow drivers to submit batchbuffers directly to hardware, relying
246 * on the security mechanisms provided by hardware. 252 * on the security mechanisms provided by hardware.
@@ -690,10 +696,31 @@ struct drm_i915_gem_busy {
690 /** Handle of the buffer to check for busy */ 696 /** Handle of the buffer to check for busy */
691 __u32 handle; 697 __u32 handle;
692 698
693 /** Return busy status (1 if busy, 0 if idle) */ 699 /** Return busy status (1 if busy, 0 if idle).
700 * The high word is used to indicate on which rings the object
701 * currently resides:
702 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
703 */
694 __u32 busy; 704 __u32 busy;
695}; 705};
696 706
707#define I915_CACHEING_NONE 0
708#define I915_CACHEING_CACHED 1
709
710struct drm_i915_gem_cacheing {
711 /**
712 * Handle of the buffer to set/get the cacheing level of. */
713 __u32 handle;
714
715 /**
716 * Cacheing level to apply or return value
717 *
718 * bits0-15 are for generic cacheing control (i.e. the above defined
719 * values). bits16-31 are reserved for platform-specific variations
720 * (e.g. l3$ caching on gen7). */
721 __u32 cacheing;
722};
723
697#define I915_TILING_NONE 0 724#define I915_TILING_NONE 0
698#define I915_TILING_X 1 725#define I915_TILING_X 1
699#define I915_TILING_Y 2 726#define I915_TILING_Y 2
@@ -910,4 +937,8 @@ struct drm_i915_gem_context_destroy {
910 __u32 pad; 937 __u32 pad;
911}; 938};
912 939
940struct drm_i915_reg_read {
941 __u64 offset;
942 __u64 val; /* Return value */
943};
913#endif /* _I915_DRM_H_ */ 944#endif /* _I915_DRM_H_ */