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authorBen Widawsky2014-01-02 13:36:59 -0600
committerBen Widawsky2014-01-10 13:05:50 -0600
commita254cb50414a5def5c872a765c0dd1295a550c6b (patch)
treec10eb4b0009798fbf0b649cdad169f75a0abbe6f /include/drm/i915_drm.h
parent3d34fe24957576d77c88877ded22e8ab5d96ca4c (diff)
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intel: Merge latest i915_drm.h
This was not done as a straight copy because reset_stats IOCTL landed in libdrm before upstream kernel. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'include/drm/i915_drm.h')
-rw-r--r--include/drm/i915_drm.h113
1 files changed, 100 insertions, 13 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index c1914d61..2f4eb8ce 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,12 +27,36 @@
27#ifndef _I915_DRM_H_ 27#ifndef _I915_DRM_H_
28#define _I915_DRM_H_ 28#define _I915_DRM_H_
29 29
30#include "drm.h" 30#include <drm.h>
31 31
32/* Please note that modifications to all structs defined here are 32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints. 33 * subject to backwards-compatibility constraints.
34 */ 34 */
35 35
36/**
37 * DOC: uevents generated by i915 on it's device node
38 *
39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
40 * event from the gpu l3 cache. Additional information supplied is ROW,
41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
42 * track of these events and if a specific cache-line seems to have a
43 * persistent error remap it with the l3 remapping tool supplied in
44 * intel-gpu-tools. The value supplied with the event is always 1.
45 *
46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
47 * hangcheck. The error detection event is a good indicator of when things
48 * began to go badly. The value supplied with the event is a 1 upon error
49 * detection, and a 0 upon reset completion, signifying no more error
50 * exists. NOTE: Disabling hangcheck or reset via module parameter will
51 * cause the related events to not be seen.
52 *
53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
54 * the GPU. The value supplied with the event is always 1. NOTE: Disable
55 * reset via module parameter will cause this event to not be seen.
56 */
57#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
58#define I915_ERROR_UEVENT "ERROR"
59#define I915_RESET_UEVENT "RESET"
36 60
37/* Each region is a minimum of 16k, and there are at most 255 of them. 61/* Each region is a minimum of 16k, and there are at most 255 of them.
38 */ 62 */
@@ -195,8 +219,8 @@ typedef struct _drm_i915_sarea {
195#define DRM_I915_GEM_WAIT 0x2c 219#define DRM_I915_GEM_WAIT 0x2c
196#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 220#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
197#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 221#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
198#define DRM_I915_GEM_SET_CACHEING 0x2f 222#define DRM_I915_GEM_SET_CACHING 0x2f
199#define DRM_I915_GEM_GET_CACHEING 0x30 223#define DRM_I915_GEM_GET_CACHING 0x30
200#define DRM_I915_REG_READ 0x31 224#define DRM_I915_REG_READ 0x31
201#define DRM_I915_GET_RESET_STATS 0x32 225#define DRM_I915_GET_RESET_STATS 0x32
202 226
@@ -223,8 +247,8 @@ typedef struct _drm_i915_sarea {
223#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 247#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
224#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 248#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
225#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 249#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
226#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) 250#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
227#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) 251#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
228#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 252#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
229#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 253#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
230#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 254#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
@@ -305,7 +329,14 @@ typedef struct drm_i915_irq_wait {
305#define I915_PARAM_HAS_LLC 17 329#define I915_PARAM_HAS_LLC 17
306#define I915_PARAM_HAS_ALIASING_PPGTT 18 330#define I915_PARAM_HAS_ALIASING_PPGTT 18
307#define I915_PARAM_HAS_WAIT_TIMEOUT 19 331#define I915_PARAM_HAS_WAIT_TIMEOUT 19
308#define I915_PARAM_HAS_VEBOX 22 332#define I915_PARAM_HAS_SEMAPHORES 20
333#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
334#define I915_PARAM_HAS_VEBOX 22
335#define I915_PARAM_HAS_SECURE_BATCHES 23
336#define I915_PARAM_HAS_PINNED_BATCHES 24
337#define I915_PARAM_HAS_EXEC_NO_RELOC 25
338#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
339#define I915_PARAM_HAS_WT 27
309 340
310typedef struct drm_i915_getparam { 341typedef struct drm_i915_getparam {
311 int param; 342 int param;
@@ -626,7 +657,11 @@ struct drm_i915_gem_exec_object2 {
626 __u64 offset; 657 __u64 offset;
627 658
628#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 659#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
660#define EXEC_OBJECT_NEEDS_GTT (1<<1)
661#define EXEC_OBJECT_WRITE (1<<2)
662#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
629 __u64 flags; 663 __u64 flags;
664
630 __u64 rsvd1; 665 __u64 rsvd1;
631 __u64 rsvd2; 666 __u64 rsvd2;
632}; 667};
@@ -672,6 +707,34 @@ struct drm_i915_gem_execbuffer2 {
672/** Resets the SO write offset registers for transform feedback on gen7. */ 707/** Resets the SO write offset registers for transform feedback on gen7. */
673#define I915_EXEC_GEN7_SOL_RESET (1<<8) 708#define I915_EXEC_GEN7_SOL_RESET (1<<8)
674 709
710/** Request a privileged ("secure") batch buffer. Note only available for
711 * DRM_ROOT_ONLY | DRM_MASTER processes.
712 */
713#define I915_EXEC_SECURE (1<<9)
714
715/** Inform the kernel that the batch is and will always be pinned. This
716 * negates the requirement for a workaround to be performed to avoid
717 * an incoherent CS (such as can be found on 830/845). If this flag is
718 * not passed, the kernel will endeavour to make sure the batch is
719 * coherent with the CS before execution. If this flag is passed,
720 * userspace assumes the responsibility for ensuring the same.
721 */
722#define I915_EXEC_IS_PINNED (1<<10)
723
724/** Provide a hint to the kernel that the command stream and auxilliary
725 * state buffers already holds the correct presumed addresses and so the
726 * relocation process may be skipped if no buffers need to be moved in
727 * preparation for the execbuffer.
728 */
729#define I915_EXEC_NO_RELOC (1<<11)
730
731/** Use the reloc.handle as an index into the exec object array rather
732 * than as the per-file handle.
733 */
734#define I915_EXEC_HANDLE_LUT (1<<12)
735
736#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
737
675#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 738#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
676#define i915_execbuffer2_set_context_id(eb2, context) \ 739#define i915_execbuffer2_set_context_id(eb2, context) \
677 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 740 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
@@ -708,21 +771,45 @@ struct drm_i915_gem_busy {
708 __u32 busy; 771 __u32 busy;
709}; 772};
710 773
711#define I915_CACHEING_NONE 0 774/**
712#define I915_CACHEING_CACHED 1 775 * I915_CACHING_NONE
776 *
777 * GPU access is not coherent with cpu caches. Default for machines without an
778 * LLC.
779 */
780#define I915_CACHING_NONE 0
781/**
782 * I915_CACHING_CACHED
783 *
784 * GPU access is coherent with cpu caches and furthermore the data is cached in
785 * last-level caches shared between cpu cores and the gpu GT. Default on
786 * machines with HAS_LLC.
787 */
788#define I915_CACHING_CACHED 1
789/**
790 * I915_CACHING_DISPLAY
791 *
792 * Special GPU caching mode which is coherent with the scanout engines.
793 * Transparently falls back to I915_CACHING_NONE on platforms where no special
794 * cache mode (like write-through or gfdt flushing) is available. The kernel
795 * automatically sets this mode when using a buffer as a scanout target.
796 * Userspace can manually set this mode to avoid a costly stall and clflush in
797 * the hotpath of drawing the first frame.
798 */
799#define I915_CACHING_DISPLAY 2
713 800
714struct drm_i915_gem_cacheing { 801struct drm_i915_gem_caching {
715 /** 802 /**
716 * Handle of the buffer to set/get the cacheing level of. */ 803 * Handle of the buffer to set/get the caching level of. */
717 __u32 handle; 804 __u32 handle;
718 805
719 /** 806 /**
720 * Cacheing level to apply or return value 807 * Cacheing level to apply or return value
721 * 808 *
722 * bits0-15 are for generic cacheing control (i.e. the above defined 809 * bits0-15 are for generic caching control (i.e. the above defined
723 * values). bits16-31 are reserved for platform-specific variations 810 * values). bits16-31 are reserved for platform-specific variations
724 * (e.g. l3$ caching on gen7). */ 811 * (e.g. l3$ caching on gen7). */
725 __u32 cacheing; 812 __u32 caching;
726}; 813};
727 814
728#define I915_TILING_NONE 0 815#define I915_TILING_NONE 0
@@ -962,4 +1049,4 @@ struct drm_i915_reset_stats {
962 __u32 pad; 1049 __u32 pad;
963}; 1050};
964 1051
965#endif /* _I915_DRM_H_ */ 1052#endif /* _I915_DRM_H_ */