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authorChris Wilson2017-01-27 04:39:10 -0600
committerChris Wilson2017-01-27 14:00:38 -0600
commita3d715ee14b29d2680ceaf44955679205795140c (patch)
tree071dca797598c729046013c5337469c07c2b2f63 /include/drm/i915_drm.h
parent8a89d5f620967a9086495d15825415ac27bf061a (diff)
downloadexternal-libgbm-a3d715ee14b29d2680ceaf44955679205795140c.tar.gz
external-libgbm-a3d715ee14b29d2680ceaf44955679205795140c.tar.xz
external-libgbm-a3d715ee14b29d2680ceaf44955679205795140c.zip
Import uapi/i915_drm.h from v4.10-rc5-950-g152d5750dda9
To sync with "drm/i915: Support explicit fencing for execbuf"
Diffstat (limited to 'include/drm/i915_drm.h')
-rw-r--r--include/drm/i915_drm.h276
1 files changed, 266 insertions, 10 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index eb611a7a..5ebe0462 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -29,6 +29,10 @@
29 29
30#include "drm.h" 30#include "drm.h"
31 31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
32/* Please note that modifications to all structs defined here are 36/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints. 37 * subject to backwards-compatibility constraints.
34 */ 38 */
@@ -58,6 +62,30 @@
58#define I915_ERROR_UEVENT "ERROR" 62#define I915_ERROR_UEVENT "ERROR"
59#define I915_RESET_UEVENT "RESET" 63#define I915_RESET_UEVENT "RESET"
60 64
65/*
66 * MOCS indexes used for GPU surfaces, defining the cacheability of the
67 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
68 */
69enum i915_mocs_table_index {
70 /*
71 * Not cached anywhere, coherency between CPU and GPU accesses is
72 * guaranteed.
73 */
74 I915_MOCS_UNCACHED,
75 /*
76 * Cacheability and coherency controlled by the kernel automatically
77 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
78 * usage of the surface (used for display scanout or not).
79 */
80 I915_MOCS_PTE,
81 /*
82 * Cached in all GPU caches available on the platform.
83 * Coherency between CPU and GPU accesses to the surface is not
84 * guaranteed without extra synchronization.
85 */
86 I915_MOCS_CACHED,
87};
88
61/* Each region is a minimum of 16k, and there are at most 255 of them. 89/* Each region is a minimum of 16k, and there are at most 255 of them.
62 */ 90 */
63#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 91#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
@@ -218,6 +246,7 @@ typedef struct _drm_i915_sarea {
218#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 246#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
219#define DRM_I915_OVERLAY_ATTRS 0x28 247#define DRM_I915_OVERLAY_ATTRS 0x28
220#define DRM_I915_GEM_EXECBUFFER2 0x29 248#define DRM_I915_GEM_EXECBUFFER2 0x29
249#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
221#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 250#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
222#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 251#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
223#define DRM_I915_GEM_WAIT 0x2c 252#define DRM_I915_GEM_WAIT 0x2c
@@ -230,6 +259,7 @@ typedef struct _drm_i915_sarea {
230#define DRM_I915_GEM_USERPTR 0x33 259#define DRM_I915_GEM_USERPTR 0x33
231#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 260#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
232#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 261#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
262#define DRM_I915_PERF_OPEN 0x36
233 263
234#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 264#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
235#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 265#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -251,6 +281,7 @@ typedef struct _drm_i915_sarea {
251#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 281#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
252#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 282#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
253#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 283#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
284#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
254#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 285#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
255#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 286#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
256#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 287#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
@@ -283,6 +314,7 @@ typedef struct _drm_i915_sarea {
283#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 314#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
284#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 315#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
285#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 316#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
317#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
286 318
287/* Allow drivers to submit batchbuffers directly to hardware, relying 319/* Allow drivers to submit batchbuffers directly to hardware, relying
288 * on the security mechanisms provided by hardware. 320 * on the security mechanisms provided by hardware.
@@ -357,8 +389,28 @@ typedef struct drm_i915_irq_wait {
357#define I915_PARAM_HAS_GPU_RESET 35 389#define I915_PARAM_HAS_GPU_RESET 35
358#define I915_PARAM_HAS_RESOURCE_STREAMER 36 390#define I915_PARAM_HAS_RESOURCE_STREAMER 36
359#define I915_PARAM_HAS_EXEC_SOFTPIN 37 391#define I915_PARAM_HAS_EXEC_SOFTPIN 37
360#define I915_PARAM_HAS_POOLED_EU 38 392#define I915_PARAM_HAS_POOLED_EU 38
361#define I915_PARAM_MIN_EU_IN_POOL 39 393#define I915_PARAM_MIN_EU_IN_POOL 39
394#define I915_PARAM_MMAP_GTT_VERSION 40
395
396/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
397 * priorities and the driver will attempt to execute batches in priority order.
398 */
399#define I915_PARAM_HAS_SCHEDULER 41
400#define I915_PARAM_HUC_STATUS 42
401
402/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
403 * synchronisation with implicit fencing on individual objects.
404 * See EXEC_OBJECT_ASYNC.
405 */
406#define I915_PARAM_HAS_EXEC_ASYNC 43
407
408/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
409 * both being able to pass in a sync_file fd to wait upon before executing,
410 * and being able to return a new sync_file fd that is signaled when the
411 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
412 */
413#define I915_PARAM_HAS_EXEC_FENCE 44
362 414
363typedef struct drm_i915_getparam { 415typedef struct drm_i915_getparam {
364 __s32 param; 416 __s32 param;
@@ -694,15 +746,41 @@ struct drm_i915_gem_exec_object2 {
694 */ 746 */
695 __u64 offset; 747 __u64 offset;
696 748
697#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 749#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
698#define EXEC_OBJECT_NEEDS_GTT (1<<1) 750#define EXEC_OBJECT_NEEDS_GTT (1<<1)
699#define EXEC_OBJECT_WRITE (1<<2) 751#define EXEC_OBJECT_WRITE (1<<2)
700#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 752#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
701#define EXEC_OBJECT_PINNED (1<<4) 753#define EXEC_OBJECT_PINNED (1<<4)
702#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) 754#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
755/* The kernel implicitly tracks GPU activity on all GEM objects, and
756 * synchronises operations with outstanding rendering. This includes
757 * rendering on other devices if exported via dma-buf. However, sometimes
758 * this tracking is too coarse and the user knows better. For example,
759 * if the object is split into non-overlapping ranges shared between different
760 * clients or engines (i.e. suballocating objects), the implicit tracking
761 * by kernel assumes that each operation affects the whole object rather
762 * than an individual range, causing needless synchronisation between clients.
763 * The kernel will also forgo any CPU cache flushes prior to rendering from
764 * the object as the client is expected to be also handling such domain
765 * tracking.
766 *
767 * The kernel maintains the implicit tracking in order to manage resources
768 * used by the GPU - this flag only disables the synchronisation prior to
769 * rendering with this object in this execbuf.
770 *
771 * Opting out of implicit synhronisation requires the user to do its own
772 * explicit tracking to avoid rendering corruption. See, for example,
773 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
774 */
775#define EXEC_OBJECT_ASYNC (1<<6)
776/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
777#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1)
703 __u64 flags; 778 __u64 flags;
704 779
705 __u64 rsvd1; 780 union {
781 __u64 rsvd1;
782 __u64 pad_to_size;
783 };
706 __u64 rsvd2; 784 __u64 rsvd2;
707}; 785};
708 786
@@ -786,7 +864,32 @@ struct drm_i915_gem_execbuffer2 {
786 */ 864 */
787#define I915_EXEC_RESOURCE_STREAMER (1<<15) 865#define I915_EXEC_RESOURCE_STREAMER (1<<15)
788 866
789#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) 867/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
868 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
869 * the batch.
870 *
871 * Returns -EINVAL if the sync_file fd cannot be found.
872 */
873#define I915_EXEC_FENCE_IN (1<<16)
874
875/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
876 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
877 * to the caller, and it should be close() after use. (The fd is a regular
878 * file descriptor and will be cleaned up on process termination. It holds
879 * a reference to the request, but nothing else.)
880 *
881 * The sync_file fd can be combined with other sync_file and passed either
882 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
883 * will only occur after this request completes), or to other devices.
884 *
885 * Using I915_EXEC_FENCE_OUT requires use of
886 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
887 * back to userspace. Failure to do so will cause the out-fence to always
888 * be reported as zero, and the real fence fd to be leaked.
889 */
890#define I915_EXEC_FENCE_OUT (1<<17)
891
892#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
790 893
791#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 894#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
792#define i915_execbuffer2_set_context_id(eb2, context) \ 895#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -822,7 +925,16 @@ struct drm_i915_gem_busy {
822 * having flushed any pending activity), and a non-zero return that 925 * having flushed any pending activity), and a non-zero return that
823 * the object is still in-flight on the GPU. (The GPU has not yet 926 * the object is still in-flight on the GPU. (The GPU has not yet
824 * signaled completion for all pending requests that reference the 927 * signaled completion for all pending requests that reference the
825 * object.) 928 * object.) An object is guaranteed to become idle eventually (so
929 * long as no new GPU commands are executed upon it). Due to the
930 * asynchronous nature of the hardware, an object reported
931 * as busy may become idle before the ioctl is completed.
932 *
933 * Furthermore, if the object is busy, which engine is busy is only
934 * provided as a guide. There are race conditions which prevent the
935 * report of which engines are busy from being always accurate.
936 * However, the converse is not true. If the object is idle, the
937 * result of the ioctl, that all engines are idle, is accurate.
826 * 938 *
827 * The returned dword is split into two fields to indicate both 939 * The returned dword is split into two fields to indicate both
828 * the engines on which the object is being read, and the 940 * the engines on which the object is being read, and the
@@ -845,6 +957,11 @@ struct drm_i915_gem_busy {
845 * execution engines, e.g. multiple media engines, which are 957 * execution engines, e.g. multiple media engines, which are
846 * mapped to the same identifier in the EXECBUFFER2 ioctl and 958 * mapped to the same identifier in the EXECBUFFER2 ioctl and
847 * so are not separately reported for busyness. 959 * so are not separately reported for busyness.
960 *
961 * Caveat emptor:
962 * Only the boolean result of this query is reliable; that is whether
963 * the object is idle or busy. The report of which engines are busy
964 * should be only used as a heuristic.
848 */ 965 */
849 __u32 busy; 966 __u32 busy;
850}; 967};
@@ -893,6 +1010,7 @@ struct drm_i915_gem_caching {
893#define I915_TILING_NONE 0 1010#define I915_TILING_NONE 0
894#define I915_TILING_X 1 1011#define I915_TILING_X 1
895#define I915_TILING_Y 2 1012#define I915_TILING_Y 2
1013#define I915_TILING_LAST I915_TILING_Y
896 1014
897#define I915_BIT_6_SWIZZLE_NONE 0 1015#define I915_BIT_6_SWIZZLE_NONE 0
898#define I915_BIT_6_SWIZZLE_9 1 1016#define I915_BIT_6_SWIZZLE_9 1
@@ -1169,7 +1287,145 @@ struct drm_i915_gem_context_param {
1169#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1287#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1170#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1288#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1171#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1289#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1290#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1291#define I915_CONTEXT_PARAM_BANNABLE 0x5
1172 __u64 value; 1292 __u64 value;
1173}; 1293};
1174 1294
1295enum drm_i915_oa_format {
1296 I915_OA_FORMAT_A13 = 1,
1297 I915_OA_FORMAT_A29,
1298 I915_OA_FORMAT_A13_B8_C8,
1299 I915_OA_FORMAT_B4_C8,
1300 I915_OA_FORMAT_A45_B8_C8,
1301 I915_OA_FORMAT_B4_C8_A16,
1302 I915_OA_FORMAT_C4_B8,
1303
1304 I915_OA_FORMAT_MAX /* non-ABI */
1305};
1306
1307enum drm_i915_perf_property_id {
1308 /**
1309 * Open the stream for a specific context handle (as used with
1310 * execbuffer2). A stream opened for a specific context this way
1311 * won't typically require root privileges.
1312 */
1313 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1314
1315 /**
1316 * A value of 1 requests the inclusion of raw OA unit reports as
1317 * part of stream samples.
1318 */
1319 DRM_I915_PERF_PROP_SAMPLE_OA,
1320
1321 /**
1322 * The value specifies which set of OA unit metrics should be
1323 * be configured, defining the contents of any OA unit reports.
1324 */
1325 DRM_I915_PERF_PROP_OA_METRICS_SET,
1326
1327 /**
1328 * The value specifies the size and layout of OA unit reports.
1329 */
1330 DRM_I915_PERF_PROP_OA_FORMAT,
1331
1332 /**
1333 * Specifying this property implicitly requests periodic OA unit
1334 * sampling and (at least on Haswell) the sampling frequency is derived
1335 * from this exponent as follows:
1336 *
1337 * 80ns * 2^(period_exponent + 1)
1338 */
1339 DRM_I915_PERF_PROP_OA_EXPONENT,
1340
1341 DRM_I915_PERF_PROP_MAX /* non-ABI */
1342};
1343
1344struct drm_i915_perf_open_param {
1345 __u32 flags;
1346#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1347#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1348#define I915_PERF_FLAG_DISABLED (1<<2)
1349
1350 /** The number of u64 (id, value) pairs */
1351 __u32 num_properties;
1352
1353 /**
1354 * Pointer to array of u64 (id, value) pairs configuring the stream
1355 * to open.
1356 */
1357 __u64 properties_ptr;
1358};
1359
1360/**
1361 * Enable data capture for a stream that was either opened in a disabled state
1362 * via I915_PERF_FLAG_DISABLED or was later disabled via
1363 * I915_PERF_IOCTL_DISABLE.
1364 *
1365 * It is intended to be cheaper to disable and enable a stream than it may be
1366 * to close and re-open a stream with the same configuration.
1367 *
1368 * It's undefined whether any pending data for the stream will be lost.
1369 */
1370#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1371
1372/**
1373 * Disable data capture for a stream.
1374 *
1375 * It is an error to try and read a stream that is disabled.
1376 */
1377#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1378
1379/**
1380 * Common to all i915 perf records
1381 */
1382struct drm_i915_perf_record_header {
1383 __u32 type;
1384 __u16 pad;
1385 __u16 size;
1386};
1387
1388enum drm_i915_perf_record_type {
1389
1390 /**
1391 * Samples are the work horse record type whose contents are extensible
1392 * and defined when opening an i915 perf stream based on the given
1393 * properties.
1394 *
1395 * Boolean properties following the naming convention
1396 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1397 * every sample.
1398 *
1399 * The order of these sample properties given by userspace has no
1400 * affect on the ordering of data within a sample. The order is
1401 * documented here.
1402 *
1403 * struct {
1404 * struct drm_i915_perf_record_header header;
1405 *
1406 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1407 * };
1408 */
1409 DRM_I915_PERF_RECORD_SAMPLE = 1,
1410
1411 /*
1412 * Indicates that one or more OA reports were not written by the
1413 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1414 * command collides with periodic sampling - which would be more likely
1415 * at higher sampling frequencies.
1416 */
1417 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1418
1419 /**
1420 * An error occurred that resulted in all pending OA reports being lost.
1421 */
1422 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1423
1424 DRM_I915_PERF_RECORD_MAX /* non-ABI */
1425};
1426
1427#if defined(__cplusplus)
1428}
1429#endif
1430
1175#endif /* _I915_DRM_H_ */ 1431#endif /* _I915_DRM_H_ */