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authorEric Engestrom2017-05-31 07:48:53 -0500
committerEric Engestrom2017-06-03 17:39:12 -0500
commit1b8db1777983b917384c2ed78ed5a2ab653d9e55 (patch)
treee14a70aef0c75263bf19fff1706a64fa7a3d5814 /include
parentce9e3ba6e2cc65e1e9e6e05a5f326c4dd25ab2c4 (diff)
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headers: sync drm_fourcc.h with airlied/drm-next
This adds a bunch of modifiers stuff, as well as a few new formats. Includes the following changes: ebbb0e5cfd2ceb1150b1 drm: add extern C guard for the UAPI headers b9fb2a21ac8058965a6b drm_fourcc: Document linear modifier af913418261d6d3e7a29 drm_fourcc: Fix DRM_FORMAT_MOD_LINEAR #define fd056f05b9fcba35b77e drm: add fourcc codes for 16bit R and RG 73f1a5858bf82f3bf232 drm/fourcc: add vivante tiled layout format modifiers ba2b5277dc52cc96944d drm: add RGB formats with separate alpha plane 5e91144dd702d068b22a drm/tegra: Add tiling FB modifiers Generated using `make headers_install` from airlied/drm-next at commit 2a1720376adda5ecf8e636fbfb05339c7dad1c55 Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/drm_fourcc.h126
1 files changed, 126 insertions, 0 deletions
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 4d8da699..55e30104 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -26,6 +26,10 @@
26 26
27#include "drm.h" 27#include "drm.h"
28 28
29#if defined(__cplusplus)
30extern "C" {
31#endif
32
29#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 33#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
30 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 34 ((__u32)(c) << 16) | ((__u32)(d) << 24))
31 35
@@ -37,10 +41,17 @@
37/* 8 bpp Red */ 41/* 8 bpp Red */
38#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 42#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
39 43
44/* 16 bpp Red */
45#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
46
40/* 16 bpp RG */ 47/* 16 bpp RG */
41#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 48#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
42#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 49#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
43 50
51/* 32 bpp RG */
52#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
53#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
54
44/* 8 bpp RGB */ 55/* 8 bpp RGB */
45#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 56#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
46#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 57#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
@@ -103,6 +114,20 @@
103#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 114#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
104 115
105/* 116/*
117 * 2 plane RGB + A
118 * index 0 = RGB plane, same format as the corresponding non _A8 format has
119 * index 1 = A plane, [7:0] A
120 */
121#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
122#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
123#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
124#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
125#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
126#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
127#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
128#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
129
130/*
106 * 2 plane YCbCr 131 * 2 plane YCbCr
107 * index 0 = Y plane, [7:0] Y 132 * index 0 = Y plane, [7:0] Y
108 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 133 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
@@ -150,11 +175,13 @@
150 175
151/* Vendor Ids: */ 176/* Vendor Ids: */
152#define DRM_FORMAT_MOD_NONE 0 177#define DRM_FORMAT_MOD_NONE 0
178#define DRM_FORMAT_MOD_VENDOR_NONE 0
153#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 179#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
154#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 180#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
155#define DRM_FORMAT_MOD_VENDOR_NV 0x03 181#define DRM_FORMAT_MOD_VENDOR_NV 0x03
156#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 182#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
157#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 183#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
184#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
158/* add more to the end as needed */ 185/* add more to the end as needed */
159 186
160#define fourcc_mod_code(vendor, val) \ 187#define fourcc_mod_code(vendor, val) \
@@ -168,6 +195,16 @@
168 * authoritative source for all of these. 195 * authoritative source for all of these.
169 */ 196 */
170 197
198/*
199 * Linear Layout
200 *
201 * Just plain linear layout. Note that this is different from no specifying any
202 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
203 * which tells the driver to also take driver-internal information into account
204 * and so might actually result in a tiled framebuffer.
205 */
206#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
207
171/* Intel framebuffer modifiers */ 208/* Intel framebuffer modifiers */
172 209
173/* 210/*
@@ -229,4 +266,93 @@
229 */ 266 */
230#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 267#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
231 268
269/* Vivante framebuffer modifiers */
270
271/*
272 * Vivante 4x4 tiling layout
273 *
274 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
275 * layout.
276 */
277#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
278
279/*
280 * Vivante 64x64 super-tiling layout
281 *
282 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
283 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
284 * major layout.
285 *
286 * For more information: see
287 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
288 */
289#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
290
291/*
292 * Vivante 4x4 tiling layout for dual-pipe
293 *
294 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
295 * different base address. Offsets from the base addresses are therefore halved
296 * compared to the non-split tiled layout.
297 */
298#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
299
300/*
301 * Vivante 64x64 super-tiling layout for dual-pipe
302 *
303 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
304 * starts at a different base address. Offsets from the base addresses are
305 * therefore halved compared to the non-split super-tiled layout.
306 */
307#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
308
309
310/* NVIDIA Tegra frame buffer modifiers */
311
312/*
313 * Some modifiers take parameters, for example the number of vertical GOBs in
314 * a block. Reserve the lower 32 bits for parameters
315 */
316#define __fourcc_mod_tegra_mode_shift 32
317#define fourcc_mod_tegra_code(val, params) \
318 fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
319#define fourcc_mod_tegra_mod(m) \
320 (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
321#define fourcc_mod_tegra_param(m) \
322 (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
323
324/*
325 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
326 *
327 * Pixels are arranged in simple tiles of 16 x 16 bytes.
328 */
329#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
330
331/*
332 * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
333 *
334 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
335 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
336 *
337 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
338 *
339 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
340 * Valid values are:
341 *
342 * 0 == ONE_GOB
343 * 1 == TWO_GOBS
344 * 2 == FOUR_GOBS
345 * 3 == EIGHT_GOBS
346 * 4 == SIXTEEN_GOBS
347 * 5 == THIRTYTWO_GOBS
348 *
349 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
350 * in full detail.
351 */
352#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
353
354#if defined(__cplusplus)
355}
356#endif
357
232#endif /* DRM_FOURCC_H */ 358#endif /* DRM_FOURCC_H */