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authorMarek Olšák2016-08-19 09:07:50 -0500
committerMarek Olšák2016-09-05 08:43:22 -0500
commit39fff5996227692cf8b6a75771a28a8d624f16ef (patch)
tree1c21ecba11282641d28492b57bb60a0566c152f0 /include
parent4462303700fd982eb5fdd266ee04d0543f4f6bf0 (diff)
downloadexternal-libgbm-39fff5996227692cf8b6a75771a28a8d624f16ef.tar.gz
external-libgbm-39fff5996227692cf8b6a75771a28a8d624f16ef.tar.xz
external-libgbm-39fff5996227692cf8b6a75771a28a8d624f16ef.zip
radeon: sync radeon_drm.h with the kernel
the CIK tile mode definitions are moved out, userspace doesn't use them Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Diffstat (limited to 'include')
-rw-r--r--include/drm/radeon_drm.h51
1 files changed, 42 insertions, 9 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index cd31794f..f09cc04c 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -35,6 +35,10 @@
35 35
36#include "drm.h" 36#include "drm.h"
37 37
38#if defined(__cplusplus)
39extern "C" {
40#endif
41
38/* WARNING: If you change any of these defines, make sure to change the 42/* WARNING: If you change any of these defines, make sure to change the
39 * defines in the X server file (radeon_sarea.h) 43 * defines in the X server file (radeon_sarea.h)
40 */ 44 */
@@ -511,6 +515,7 @@ typedef struct {
511#define DRM_RADEON_GEM_BUSY 0x2a 515#define DRM_RADEON_GEM_BUSY 0x2a
512#define DRM_RADEON_GEM_VA 0x2b 516#define DRM_RADEON_GEM_VA 0x2b
513#define DRM_RADEON_GEM_OP 0x2c 517#define DRM_RADEON_GEM_OP 0x2c
518#define DRM_RADEON_GEM_USERPTR 0x2d
514 519
515#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 520#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
516#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 521#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@@ -554,6 +559,7 @@ typedef struct {
554#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 559#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
555#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 560#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
556#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) 561#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
562#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
557 563
558typedef struct drm_radeon_init { 564typedef struct drm_radeon_init {
559 enum { 565 enum {
@@ -796,7 +802,13 @@ struct drm_radeon_gem_info {
796 uint64_t vram_visible; 802 uint64_t vram_visible;
797}; 803};
798 804
799#define RADEON_GEM_NO_BACKING_STORE 1 805#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
806#define RADEON_GEM_GTT_UC (1 << 1)
807#define RADEON_GEM_GTT_WC (1 << 2)
808/* BO is expected to be accessed by the CPU */
809#define RADEON_GEM_CPU_ACCESS (1 << 3)
810/* CPU access is not expected to work for this BO */
811#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
800 812
801struct drm_radeon_gem_create { 813struct drm_radeon_gem_create {
802 uint64_t size; 814 uint64_t size;
@@ -806,6 +818,23 @@ struct drm_radeon_gem_create {
806 uint32_t flags; 818 uint32_t flags;
807}; 819};
808 820
821/*
822 * This is not a reliable API and you should expect it to fail for any
823 * number of reasons and have fallback path that do not use userptr to
824 * perform any operation.
825 */
826#define RADEON_GEM_USERPTR_READONLY (1 << 0)
827#define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
828#define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
829#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
830
831struct drm_radeon_gem_userptr {
832 uint64_t addr;
833 uint64_t size;
834 uint32_t flags;
835 uint32_t handle;
836};
837
809#define RADEON_TILING_MACRO 0x1 838#define RADEON_TILING_MACRO 0x1
810#define RADEON_TILING_MICRO 0x2 839#define RADEON_TILING_MICRO 0x2
811#define RADEON_TILING_SWAP_16BIT 0x4 840#define RADEON_TILING_SWAP_16BIT 0x4
@@ -943,6 +972,7 @@ struct drm_radeon_cs_chunk {
943}; 972};
944 973
945/* drm_radeon_cs_reloc.flags */ 974/* drm_radeon_cs_reloc.flags */
975#define RADEON_RELOC_PRIO_MASK (0xf << 0)
946 976
947struct drm_radeon_cs_reloc { 977struct drm_radeon_cs_reloc {
948 uint32_t handle; 978 uint32_t handle;
@@ -1008,7 +1038,13 @@ struct drm_radeon_cs {
1008#define RADEON_INFO_NUM_BYTES_MOVED 0x1d 1038#define RADEON_INFO_NUM_BYTES_MOVED 0x1d
1009#define RADEON_INFO_VRAM_USAGE 0x1e 1039#define RADEON_INFO_VRAM_USAGE 0x1e
1010#define RADEON_INFO_GTT_USAGE 0x1f 1040#define RADEON_INFO_GTT_USAGE 0x1f
1011 1041#define RADEON_INFO_ACTIVE_CU_COUNT 0x20
1042#define RADEON_INFO_CURRENT_GPU_TEMP 0x21
1043#define RADEON_INFO_CURRENT_GPU_SCLK 0x22
1044#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
1045#define RADEON_INFO_READ_REG 0x24
1046#define RADEON_INFO_VA_UNMAP_WORKING 0x25
1047#define RADEON_INFO_GPU_RESET_COUNTER 0x26
1012 1048
1013struct drm_radeon_info { 1049struct drm_radeon_info {
1014 uint32_t request; 1050 uint32_t request;
@@ -1034,13 +1070,10 @@ struct drm_radeon_info {
1034#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 1070#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
1035#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 1071#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
1036 1072
1037#define CIK_TILE_MODE_COLOR_2D 14
1038#define CIK_TILE_MODE_COLOR_2D_SCANOUT 10
1039#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0
1040#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1
1041#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2
1042#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3
1043#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4
1044#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 1073#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
1045 1074
1075#if defined(__cplusplus)
1076}
1077#endif
1078
1046#endif 1079#endif