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author | Kristian Høgsberg Kristensen | 2015-12-14 13:27:53 -0600 |
---|---|---|
committer | Kristian Høgsberg Kristensen | 2015-12-14 13:30:10 -0600 |
commit | 7d74a83d22e694b2cd71e40992fd5a970d227e32 (patch) | |
tree | 46a0c1e67fcbdf77a27a816f549b9daab724a1ce /include | |
parent | 42f2f92059dca568e896aee93126b8bef2a332a1 (diff) | |
download | external-libgbm-7d74a83d22e694b2cd71e40992fd5a970d227e32.tar.gz external-libgbm-7d74a83d22e694b2cd71e40992fd5a970d227e32.tar.xz external-libgbm-7d74a83d22e694b2cd71e40992fd5a970d227e32.zip |
intel: Update i915_drm.h
Copy from drm-intel-nightly a307a3a81c2bf2883457e03abcf5c9520cf452c1.
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/drm/i915_drm.h | 59 |
1 files changed, 49 insertions, 10 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index ded43b1c..0e51d421 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h | |||
@@ -27,7 +27,7 @@ | |||
27 | #ifndef _I915_DRM_H_ | 27 | #ifndef _I915_DRM_H_ |
28 | #define _I915_DRM_H_ | 28 | #define _I915_DRM_H_ |
29 | 29 | ||
30 | #include <drm.h> | 30 | #include "drm.h" |
31 | 31 | ||
32 | /* Please note that modifications to all structs defined here are | 32 | /* Please note that modifications to all structs defined here are |
33 | * subject to backwards-compatibility constraints. | 33 | * subject to backwards-compatibility constraints. |
@@ -171,8 +171,12 @@ typedef struct _drm_i915_sarea { | |||
171 | #define I915_BOX_TEXTURE_LOAD 0x8 | 171 | #define I915_BOX_TEXTURE_LOAD 0x8 |
172 | #define I915_BOX_LOST_CONTEXT 0x10 | 172 | #define I915_BOX_LOST_CONTEXT 0x10 |
173 | 173 | ||
174 | /* I915 specific ioctls | 174 | /* |
175 | * The device specific ioctl range is 0x40 to 0x79. | 175 | * i915 specific ioctls. |
176 | * | ||
177 | * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie | ||
178 | * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset | ||
179 | * against DRM_COMMAND_BASE and should be between [0x0, 0x60). | ||
176 | */ | 180 | */ |
177 | #define DRM_I915_INIT 0x00 | 181 | #define DRM_I915_INIT 0x00 |
178 | #define DRM_I915_FLUSH 0x01 | 182 | #define DRM_I915_FLUSH 0x01 |
@@ -270,7 +274,7 @@ typedef struct _drm_i915_sarea { | |||
270 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) | 274 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) |
271 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) | 275 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) |
272 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) | 276 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
273 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) | 277 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
274 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) | 278 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
275 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) | 279 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
276 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) | 280 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
@@ -350,9 +354,16 @@ typedef struct drm_i915_irq_wait { | |||
350 | #define I915_PARAM_REVISION 32 | 354 | #define I915_PARAM_REVISION 32 |
351 | #define I915_PARAM_SUBSLICE_TOTAL 33 | 355 | #define I915_PARAM_SUBSLICE_TOTAL 33 |
352 | #define I915_PARAM_EU_TOTAL 34 | 356 | #define I915_PARAM_EU_TOTAL 34 |
357 | #define I915_PARAM_HAS_GPU_RESET 35 | ||
358 | #define I915_PARAM_HAS_RESOURCE_STREAMER 36 | ||
359 | #define I915_PARAM_HAS_EXEC_SOFTPIN 37 | ||
353 | 360 | ||
354 | typedef struct drm_i915_getparam { | 361 | typedef struct drm_i915_getparam { |
355 | int param; | 362 | __s32 param; |
363 | /* | ||
364 | * WARNING: Using pointers instead of fixed-size u64 means we need to write | ||
365 | * compat32 code. Don't repeat this mistake. | ||
366 | */ | ||
356 | int *value; | 367 | int *value; |
357 | } drm_i915_getparam_t; | 368 | } drm_i915_getparam_t; |
358 | 369 | ||
@@ -672,15 +683,21 @@ struct drm_i915_gem_exec_object2 { | |||
672 | __u64 alignment; | 683 | __u64 alignment; |
673 | 684 | ||
674 | /** | 685 | /** |
675 | * Returned value of the updated offset of the object, for future | 686 | * When the EXEC_OBJECT_PINNED flag is specified this is populated by |
676 | * presumed_offset writes. | 687 | * the user with the GTT offset at which this object will be pinned. |
688 | * When the I915_EXEC_NO_RELOC flag is specified this must contain the | ||
689 | * presumed_offset of the object. | ||
690 | * During execbuffer2 the kernel populates it with the value of the | ||
691 | * current GTT offset of the object, for future presumed_offset writes. | ||
677 | */ | 692 | */ |
678 | __u64 offset; | 693 | __u64 offset; |
679 | 694 | ||
680 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) | 695 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
681 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) | 696 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) |
682 | #define EXEC_OBJECT_WRITE (1<<2) | 697 | #define EXEC_OBJECT_WRITE (1<<2) |
683 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) | 698 | #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
699 | #define EXEC_OBJECT_PINNED (1<<4) | ||
700 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) | ||
684 | __u64 flags; | 701 | __u64 flags; |
685 | 702 | ||
686 | __u64 rsvd1; | 703 | __u64 rsvd1; |
@@ -760,7 +777,12 @@ struct drm_i915_gem_execbuffer2 { | |||
760 | #define I915_EXEC_BSD_RING1 (1<<13) | 777 | #define I915_EXEC_BSD_RING1 (1<<13) |
761 | #define I915_EXEC_BSD_RING2 (2<<13) | 778 | #define I915_EXEC_BSD_RING2 (2<<13) |
762 | 779 | ||
763 | #define __I915_EXEC_UNKNOWN_FLAGS -(1<<15) | 780 | /** Tell the kernel that the batchbuffer is processed by |
781 | * the resource streamer. | ||
782 | */ | ||
783 | #define I915_EXEC_RESOURCE_STREAMER (1<<15) | ||
784 | |||
785 | #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) | ||
764 | 786 | ||
765 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) | 787 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
766 | #define i915_execbuffer2_set_context_id(eb2, context) \ | 788 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
@@ -996,6 +1018,7 @@ struct drm_intel_overlay_put_image { | |||
996 | /* flags */ | 1018 | /* flags */ |
997 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) | 1019 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
998 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) | 1020 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
1021 | #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) | ||
999 | struct drm_intel_overlay_attrs { | 1022 | struct drm_intel_overlay_attrs { |
1000 | __u32 flags; | 1023 | __u32 flags; |
1001 | __u32 color_key; | 1024 | __u32 color_key; |
@@ -1062,9 +1085,23 @@ struct drm_i915_gem_context_destroy { | |||
1062 | }; | 1085 | }; |
1063 | 1086 | ||
1064 | struct drm_i915_reg_read { | 1087 | struct drm_i915_reg_read { |
1088 | /* | ||
1089 | * Register offset. | ||
1090 | * For 64bit wide registers where the upper 32bits don't immediately | ||
1091 | * follow the lower 32bits, the offset of the lower 32bits must | ||
1092 | * be specified | ||
1093 | */ | ||
1065 | __u64 offset; | 1094 | __u64 offset; |
1066 | __u64 val; /* Return value */ | 1095 | __u64 val; /* Return value */ |
1067 | }; | 1096 | }; |
1097 | /* Known registers: | ||
1098 | * | ||
1099 | * Render engine timestamp - 0x2358 + 64bit - gen7+ | ||
1100 | * - Note this register returns an invalid value if using the default | ||
1101 | * single instruction 8byte read, in order to workaround that use | ||
1102 | * offset (0x2538 | 1) instead. | ||
1103 | * | ||
1104 | */ | ||
1068 | 1105 | ||
1069 | struct drm_i915_reset_stats { | 1106 | struct drm_i915_reset_stats { |
1070 | __u32 ctx_id; | 1107 | __u32 ctx_id; |
@@ -1100,7 +1137,9 @@ struct drm_i915_gem_context_param { | |||
1100 | __u32 ctx_id; | 1137 | __u32 ctx_id; |
1101 | __u32 size; | 1138 | __u32 size; |
1102 | __u64 param; | 1139 | __u64 param; |
1103 | #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 | 1140 | #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
1141 | #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 | ||
1142 | #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 | ||
1104 | __u64 value; | 1143 | __u64 value; |
1105 | }; | 1144 | }; |
1106 | 1145 | ||