aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDave Airlie2017-06-26 21:56:25 -0500
committerDave Airlie2017-06-26 22:08:39 -0500
commit92b5b308ca2fec356dd29bb2f27d88a5aff61798 (patch)
tree9de0632aee18e6c92fa46ef6c4e7d7a9965841e9 /include
parentb9549c954e190010a79e6691983b6ae16eac83d5 (diff)
downloadexternal-libgbm-92b5b308ca2fec356dd29bb2f27d88a5aff61798.tar.gz
external-libgbm-92b5b308ca2fec356dd29bb2f27d88a5aff61798.tar.xz
external-libgbm-92b5b308ca2fec356dd29bb2f27d88a5aff61798.zip
amdgpu: sync amdgpu_drm with kernel.
This syncs the amdgpu_drm header with my drm-next branch as of 6d61e70ccc21606ffb8a0a03bd3aba24f659502b. It brings over the VM and semaphore API changes. Generated using make headers_install. Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/amdgpu_drm.h54
1 files changed, 53 insertions, 1 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 8cfe68c5..d9aa4a33 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -51,6 +51,7 @@ extern "C" {
51#define DRM_AMDGPU_GEM_OP 0x10 51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11 52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12 53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13
54 55
55#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 56#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
56#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 57#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -65,6 +66,7 @@ extern "C" {
65#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 66#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
66#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 67#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
67#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 68#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
69#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
68 70
69#define AMDGPU_GEM_DOMAIN_CPU 0x1 71#define AMDGPU_GEM_DOMAIN_CPU 0x1
70#define AMDGPU_GEM_DOMAIN_GTT 0x2 72#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -190,6 +192,26 @@ union drm_amdgpu_ctx {
190 union drm_amdgpu_ctx_out out; 192 union drm_amdgpu_ctx_out out;
191}; 193};
192 194
195/* vm ioctl */
196#define AMDGPU_VM_OP_RESERVE_VMID 1
197#define AMDGPU_VM_OP_UNRESERVE_VMID 2
198
199struct drm_amdgpu_vm_in {
200 /** AMDGPU_VM_OP_* */
201 __u32 op;
202 __u32 flags;
203};
204
205struct drm_amdgpu_vm_out {
206 /** For future use, no flags defined so far */
207 __u64 flags;
208};
209
210union drm_amdgpu_vm {
211 struct drm_amdgpu_vm_in in;
212 struct drm_amdgpu_vm_out out;
213};
214
193/* 215/*
194 * This is not a reliable API and you should expect it to fail for any 216 * This is not a reliable API and you should expect it to fail for any
195 * number of reasons and have fallback path that do not use userptr to 217 * number of reasons and have fallback path that do not use userptr to
@@ -295,7 +317,10 @@ union drm_amdgpu_gem_wait_idle {
295}; 317};
296 318
297struct drm_amdgpu_wait_cs_in { 319struct drm_amdgpu_wait_cs_in {
298 /** Command submission handle */ 320 /* Command submission handle
321 * handle equals 0 means none to wait for
322 * handle equals ~0ull means wait for the latest sequence number
323 */
299 __u64 handle; 324 __u64 handle;
300 /** Absolute timeout to wait */ 325 /** Absolute timeout to wait */
301 __u64 timeout; 326 __u64 timeout;
@@ -415,6 +440,8 @@ struct drm_amdgpu_gem_va {
415#define AMDGPU_CHUNK_ID_IB 0x01 440#define AMDGPU_CHUNK_ID_IB 0x01
416#define AMDGPU_CHUNK_ID_FENCE 0x02 441#define AMDGPU_CHUNK_ID_FENCE 0x02
417#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 442#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
443#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
444#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
418 445
419struct drm_amdgpu_cs_chunk { 446struct drm_amdgpu_cs_chunk {
420 __u32 chunk_id; 447 __u32 chunk_id;
@@ -482,6 +509,10 @@ struct drm_amdgpu_cs_chunk_fence {
482 __u32 offset; 509 __u32 offset;
483}; 510};
484 511
512struct drm_amdgpu_cs_chunk_sem {
513 __u32 handle;
514};
515
485struct drm_amdgpu_cs_chunk_data { 516struct drm_amdgpu_cs_chunk_data {
486 union { 517 union {
487 struct drm_amdgpu_cs_chunk_ib ib_data; 518 struct drm_amdgpu_cs_chunk_ib ib_data;
@@ -578,6 +609,8 @@ struct drm_amdgpu_cs_chunk_data {
578 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 609 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
579 /* Subquery id: Query graphics voltage */ 610 /* Subquery id: Query graphics voltage */
580 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 611 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
612/* Number of VRAM page faults on CPU access. */
613#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
581 614
582#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 615#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
583#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 616#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -766,6 +799,25 @@ struct drm_amdgpu_info_device {
766 __u64 cntl_sb_buf_gpu_addr; 799 __u64 cntl_sb_buf_gpu_addr;
767 /* NGG Parameter Cache */ 800 /* NGG Parameter Cache */
768 __u64 param_buf_gpu_addr; 801 __u64 param_buf_gpu_addr;
802 __u32 prim_buf_size;
803 __u32 pos_buf_size;
804 __u32 cntl_sb_buf_size;
805 __u32 param_buf_size;
806 /* wavefront size*/
807 __u32 wave_front_size;
808 /* shader visible vgprs*/
809 __u32 num_shader_visible_vgprs;
810 /* CU per shader array*/
811 __u32 num_cu_per_sh;
812 /* number of tcc blocks*/
813 __u32 num_tcc_blocks;
814 /* gs vgt table depth*/
815 __u32 gs_vgt_table_depth;
816 /* gs primitive buffer depth*/
817 __u32 gs_prim_buffer_depth;
818 /* max gs wavefront per vgt*/
819 __u32 max_gs_waves_per_vgt;
820 __u32 _pad1;
769}; 821};
770 822
771struct drm_amdgpu_info_hw_ip { 823struct drm_amdgpu_info_hw_ip {