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authorThierry Reding2017-11-14 11:50:30 -0600
committerThierry Reding2018-02-19 07:58:57 -0600
commitab5aaf6c8eb93462c15007e9b54f4447c1ea8148 (patch)
treed541cc706820c36b9be3f2bfa5793a528f2cd8b4 /include
parentb3c4c79e16f13a72e8124f69453a37135329f968 (diff)
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drm/tegra: Sanitize format modifiers
The existing format modifier definitions were merged prematurely, and recent work has unveiled that the definitions are suboptimal in several ways: - The format specifiers, except for one, are not Tegra specific, but the names don't reflect that. - The number space is split into two, reserving 32 bits for some "parameter" which most of the modifiers are not going to have. - Symbolic names for the modifiers are not using the standard DRM_FORMAT_MOD_* prefix, which makes them awkward to use. - The vendor prefix NV is somewhat ambiguous. Fortunately, nobody's started using these modifiers, so we can still fix the above issues. Do so by using the standard prefix. Also, remove TEGRA from the name of those modifiers that exist on NVIDIA GPUs as well. In case of the block linear modifiers, make the "parameter" smaller (4 bits, though only 6 values are valid) and don't let that leak into any of the other modifiers. Finally, also use the more canonical NVIDIA instead of the ambiguous NV prefix. This is based on commit 5843f4e02fbe86a59981e35adc6cabebee46fdc0 from Linux v4.16-rc1 and also updates modetest to use the new defines. Acked-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/drm_fourcc.h36
1 files changed, 19 insertions, 17 deletions
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index a76ed8f9..e04613d3 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -178,7 +178,7 @@ extern "C" {
178#define DRM_FORMAT_MOD_VENDOR_NONE 0 178#define DRM_FORMAT_MOD_VENDOR_NONE 0
179#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 179#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
180#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 180#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
181#define DRM_FORMAT_MOD_VENDOR_NV 0x03 181#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
182#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 182#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
183#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 183#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
184#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 184#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
@@ -338,29 +338,17 @@ extern "C" {
338 */ 338 */
339#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 339#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
340 340
341/* NVIDIA Tegra frame buffer modifiers */ 341/* NVIDIA frame buffer modifiers */
342
343/*
344 * Some modifiers take parameters, for example the number of vertical GOBs in
345 * a block. Reserve the lower 32 bits for parameters
346 */
347#define __fourcc_mod_tegra_mode_shift 32
348#define fourcc_mod_tegra_code(val, params) \
349 fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
350#define fourcc_mod_tegra_mod(m) \
351 (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
352#define fourcc_mod_tegra_param(m) \
353 (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
354 342
355/* 343/*
356 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 344 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
357 * 345 *
358 * Pixels are arranged in simple tiles of 16 x 16 bytes. 346 * Pixels are arranged in simple tiles of 16 x 16 bytes.
359 */ 347 */
360#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) 348#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
361 349
362/* 350/*
363 * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 351 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
364 * 352 *
365 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 353 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
366 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 354 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
@@ -380,7 +368,21 @@ extern "C" {
380 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 368 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
381 * in full detail. 369 * in full detail.
382 */ 370 */
383#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) 371#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
372 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
373
374#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
375 fourcc_mod_code(NVIDIA, 0x10)
376#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
377 fourcc_mod_code(NVIDIA, 0x11)
378#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
379 fourcc_mod_code(NVIDIA, 0x12)
380#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
381 fourcc_mod_code(NVIDIA, 0x13)
382#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
383 fourcc_mod_code(NVIDIA, 0x14)
384#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
385 fourcc_mod_code(NVIDIA, 0x15)
384 386
385/* 387/*
386 * Broadcom VC4 "T" format 388 * Broadcom VC4 "T" format