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authorMarek Olšák2017-10-12 13:31:44 -0500
committerMarek Olšák2017-10-12 13:35:57 -0500
commitad4df736a9f8098cd47008c72948ceff9e9f9dac (patch)
tree463a413eb065f09a80c6c1f395219821429cae62 /include
parentd27fd2d02300fdc107c9cc54d57989b8a29efd9f (diff)
downloadexternal-libgbm-ad4df736a9f8098cd47008c72948ceff9e9f9dac.tar.gz
external-libgbm-ad4df736a9f8098cd47008c72948ceff9e9f9dac.tar.xz
external-libgbm-ad4df736a9f8098cd47008c72948ceff9e9f9dac.zip
include: sync drm.h and amdgpu_drm.h with airlied/drm-next
Diffstat (limited to 'include')
-rw-r--r--include/drm/amdgpu_drm.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d9aa4a33..4c6e8c48 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -52,6 +52,7 @@ extern "C" {
52#define DRM_AMDGPU_GEM_USERPTR 0x11 52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12 53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13 54#define DRM_AMDGPU_VM 0x13
55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
55 56
56#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 57#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
57#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 58#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -67,6 +68,7 @@ extern "C" {
67#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 68#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
68#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 69#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
69#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 70#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
71#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
70 72
71#define AMDGPU_GEM_DOMAIN_CPU 0x1 73#define AMDGPU_GEM_DOMAIN_CPU 0x1
72#define AMDGPU_GEM_DOMAIN_GTT 0x2 74#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -87,6 +89,8 @@ extern "C" {
87#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 89#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
88/* Flag that allocating the BO should use linear VRAM */ 90/* Flag that allocating the BO should use linear VRAM */
89#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 91#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
92/* Flag that BO is always valid in this VM */
93#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
90 94
91struct drm_amdgpu_gem_create_in { 95struct drm_amdgpu_gem_create_in {
92 /** the requested memory size */ 96 /** the requested memory size */
@@ -513,6 +517,20 @@ struct drm_amdgpu_cs_chunk_sem {
513 __u32 handle; 517 __u32 handle;
514}; 518};
515 519
520#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
521#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
522#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
523
524union drm_amdgpu_fence_to_handle {
525 struct {
526 struct drm_amdgpu_fence fence;
527 __u32 what;
528 } in;
529 struct {
530 __u32 handle;
531 } out;
532};
533
516struct drm_amdgpu_cs_chunk_data { 534struct drm_amdgpu_cs_chunk_data {
517 union { 535 union {
518 struct drm_amdgpu_cs_chunk_ib ib_data; 536 struct drm_amdgpu_cs_chunk_ib ib_data;
@@ -764,6 +782,7 @@ struct drm_amdgpu_info_device {
764 __u64 max_memory_clock; 782 __u64 max_memory_clock;
765 /* cu information */ 783 /* cu information */
766 __u32 cu_active_number; 784 __u32 cu_active_number;
785 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
767 __u32 cu_ao_mask; 786 __u32 cu_ao_mask;
768 __u32 cu_bitmap[4][4]; 787 __u32 cu_bitmap[4][4];
769 /** Render backend pipe mask. One render backend is CB+DB. */ 788 /** Render backend pipe mask. One render backend is CB+DB. */
@@ -818,6 +837,8 @@ struct drm_amdgpu_info_device {
818 /* max gs wavefront per vgt*/ 837 /* max gs wavefront per vgt*/
819 __u32 max_gs_waves_per_vgt; 838 __u32 max_gs_waves_per_vgt;
820 __u32 _pad1; 839 __u32 _pad1;
840 /* always on cu bitmap */
841 __u32 cu_ao_bitmap[4][4];
821}; 842};
822 843
823struct drm_amdgpu_info_hw_ip { 844struct drm_amdgpu_info_hw_ip {