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authorMarek Olšák2017-03-21 14:14:45 -0500
committerMarek Olšák2017-03-27 14:42:07 -0500
commitc34b28ae9bac7a20e60482a2bf72f16ad5e28c67 (patch)
tree4259609be6d13a15eebe616a146c43cb15cb688d /include
parent3dc002df3e5607a3ae0a194b35e1f2fb2cd36697 (diff)
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amdgpu: update amdgpu_drm.h for Vega10
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/amdgpu_drm.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 5797283c..1e25a87d 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -209,6 +209,7 @@ struct drm_amdgpu_gem_userptr {
209 __u32 handle; 209 __u32 handle;
210}; 210};
211 211
212/* SI-CI-VI: */
212/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 213/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
213#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 214#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
214#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 215#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
@@ -227,10 +228,14 @@ struct drm_amdgpu_gem_userptr {
227#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 228#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
228#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 229#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
229 230
231/* GFX9 and later: */
232#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
233#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
234
230#define AMDGPU_TILING_SET(field, value) \ 235#define AMDGPU_TILING_SET(field, value) \
231 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 236 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
232#define AMDGPU_TILING_GET(value, field) \ 237#define AMDGPU_TILING_GET(value, field) \
233 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 238 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
234 239
235#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 240#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
236#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 241#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
@@ -755,6 +760,7 @@ struct drm_amdgpu_info_vce_clock_table {
755#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 760#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
756#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 761#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
757#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 762#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
763#define AMDGPU_FAMILY_AI 141 /* Vega10 */
758 764
759#if defined(__cplusplus) 765#if defined(__cplusplus)
760} 766}