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authorNicolai Hähnle2017-04-03 03:22:59 -0500
committerNicolai Hähnle2017-04-03 11:31:47 -0500
commitf104148e40d6285a04698f0fa5f4ef76383bee6f (patch)
tree948c328487bbef41682a714d1e3e79a18b59b4b8 /include
parent4e369f25a942837454f1c127a7a440571af4f486 (diff)
downloadexternal-libgbm-f104148e40d6285a04698f0fa5f4ef76383bee6f.tar.gz
external-libgbm-f104148e40d6285a04698f0fa5f4ef76383bee6f.tar.xz
external-libgbm-f104148e40d6285a04698f0fa5f4ef76383bee6f.zip
headers: sync amdgpu_drm.h from airlied/drm-next
Changes include: PRT and preemption flags, sensor info, and some more changes for Vega10. Generated using make headers_install from airlied/drm-next commit 320d8c3d38739fa8e31a076b86cbdafcf8897d5e. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Emil Velikov <emil.velikov@collabora.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/amdgpu_drm.h56
1 files changed, 55 insertions, 1 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index fa56499f..516a9f28 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -232,6 +232,7 @@ struct drm_amdgpu_gem_userptr {
232#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 232#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
233#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 233#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
234 234
235/* Set/Get helpers for tiling flags. */
235#define AMDGPU_TILING_SET(field, value) \ 236#define AMDGPU_TILING_SET(field, value) \
236 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 237 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
237#define AMDGPU_TILING_GET(value, field) \ 238#define AMDGPU_TILING_GET(value, field) \
@@ -355,6 +356,8 @@ struct drm_amdgpu_gem_op {
355 356
356#define AMDGPU_VA_OP_MAP 1 357#define AMDGPU_VA_OP_MAP 1
357#define AMDGPU_VA_OP_UNMAP 2 358#define AMDGPU_VA_OP_UNMAP 2
359#define AMDGPU_VA_OP_CLEAR 3
360#define AMDGPU_VA_OP_REPLACE 4
358 361
359/* Delay the page table update till the next CS */ 362/* Delay the page table update till the next CS */
360#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 363#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
@@ -366,6 +369,20 @@ struct drm_amdgpu_gem_op {
366#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 369#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
367/* executable mapping, new for VI */ 370/* executable mapping, new for VI */
368#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 371#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
372/* partially resident texture */
373#define AMDGPU_VM_PAGE_PRT (1 << 4)
374/* MTYPE flags use bit 5 to 8 */
375#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
376/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
377#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
378/* Use NC MTYPE instead of default MTYPE */
379#define AMDGPU_VM_MTYPE_NC (1 << 5)
380/* Use WC MTYPE instead of default MTYPE */
381#define AMDGPU_VM_MTYPE_WC (2 << 5)
382/* Use CC MTYPE instead of default MTYPE */
383#define AMDGPU_VM_MTYPE_CC (3 << 5)
384/* Use UC MTYPE instead of default MTYPE */
385#define AMDGPU_VM_MTYPE_UC (4 << 5)
369 386
370struct drm_amdgpu_gem_va { 387struct drm_amdgpu_gem_va {
371 /** GEM object handle */ 388 /** GEM object handle */
@@ -428,9 +445,12 @@ union drm_amdgpu_cs {
428/* This IB should be submitted to CE */ 445/* This IB should be submitted to CE */
429#define AMDGPU_IB_FLAG_CE (1<<0) 446#define AMDGPU_IB_FLAG_CE (1<<0)
430 447
431/* CE Preamble */ 448/* Preamble flag, which means the IB could be dropped if no context switch */
432#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 449#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
433 450
451/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
452#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
453
434struct drm_amdgpu_cs_chunk_ib { 454struct drm_amdgpu_cs_chunk_ib {
435 __u32 _pad; 455 __u32 _pad;
436 /** AMDGPU_IB_FLAG_* */ 456 /** AMDGPU_IB_FLAG_* */
@@ -506,6 +526,10 @@ struct drm_amdgpu_cs_chunk_data {
506 #define AMDGPU_INFO_FW_SMC 0x0a 526 #define AMDGPU_INFO_FW_SMC 0x0a
507 /* Subquery id: Query SDMA firmware version */ 527 /* Subquery id: Query SDMA firmware version */
508 #define AMDGPU_INFO_FW_SDMA 0x0b 528 #define AMDGPU_INFO_FW_SDMA 0x0b
529 /* Subquery id: Query PSP SOS firmware version */
530 #define AMDGPU_INFO_FW_SOS 0x0c
531 /* Subquery id: Query PSP ASD firmware version */
532 #define AMDGPU_INFO_FW_ASD 0x0d
509/* number of bytes moved for TTM migration */ 533/* number of bytes moved for TTM migration */
510#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 534#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
511/* the used VRAM size */ 535/* the used VRAM size */
@@ -536,6 +560,22 @@ struct drm_amdgpu_cs_chunk_data {
536 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 560 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
537/* Query UVD handles */ 561/* Query UVD handles */
538#define AMDGPU_INFO_NUM_HANDLES 0x1C 562#define AMDGPU_INFO_NUM_HANDLES 0x1C
563/* Query sensor related information */
564#define AMDGPU_INFO_SENSOR 0x1D
565 /* Subquery id: Query GPU shader clock */
566 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
567 /* Subquery id: Query GPU memory clock */
568 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
569 /* Subquery id: Query GPU temperature */
570 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
571 /* Subquery id: Query GPU load */
572 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
573 /* Subquery id: Query average GPU power */
574 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
575 /* Subquery id: Query northbridge voltage */
576 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
577 /* Subquery id: Query graphics voltage */
578 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
539 579
540#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 580#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
541#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 581#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -599,6 +639,10 @@ struct drm_amdgpu_info {
599 __u32 type; 639 __u32 type;
600 __u32 offset; 640 __u32 offset;
601 } vbios_info; 641 } vbios_info;
642
643 struct {
644 __u32 type;
645 } sensor_info;
602 }; 646 };
603}; 647};
604 648
@@ -710,6 +754,16 @@ struct drm_amdgpu_info_device {
710 __u32 vram_bit_width; 754 __u32 vram_bit_width;
711 /* vce harvesting instance */ 755 /* vce harvesting instance */
712 __u32 vce_harvest_config; 756 __u32 vce_harvest_config;
757 /* gfx double offchip LDS buffers */
758 __u32 gc_double_offchip_lds_buf;
759 /* NGG Primitive Buffer */
760 __u64 prim_buf_gpu_addr;
761 /* NGG Position Buffer */
762 __u64 pos_buf_gpu_addr;
763 /* NGG Control Sideband */
764 __u64 cntl_sb_buf_gpu_addr;
765 /* NGG Parameter Cache */
766 __u64 param_buf_gpu_addr;
713}; 767};
714 768
715struct drm_amdgpu_info_hw_ip { 769struct drm_amdgpu_info_hw_ip {