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authorEric Anholt2017-11-08 13:22:55 -0600
committerEric Anholt2017-11-10 14:10:17 -0600
commitf696698e0249a8b65ef7d1a0c484633fc3f286ef (patch)
tree1ed1425f17ac827b4afc744520f94fde6928822f /include
parent59808bcacd48f4168c3c1093b4616c2ee039b5a1 (diff)
downloadexternal-libgbm-f696698e0249a8b65ef7d1a0c484633fc3f286ef.tar.gz
external-libgbm-f696698e0249a8b65ef7d1a0c484633fc3f286ef.tar.xz
external-libgbm-f696698e0249a8b65ef7d1a0c484633fc3f286ef.zip
headers: Sync up kernel changes to use kernel types instead of stdint.h.
This pulls in pieces of drm-next d65d31388a23 ("Merge tag 'drm-misc-next-fixes-2017-11-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next") Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/README9
-rw-r--r--include/drm/nouveau_drm.h84
-rw-r--r--include/drm/qxl_drm.h72
-rw-r--r--include/drm/radeon_drm.h128
4 files changed, 144 insertions, 149 deletions
diff --git a/include/drm/README b/include/drm/README
index 6e12ca4d..042cfb17 100644
--- a/include/drm/README
+++ b/include/drm/README
@@ -102,19 +102,14 @@ Status: Trivial.
102 102
103nouveau_drm.h 103nouveau_drm.h
104 - Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs, 104 - Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs,
105enums, using stdint.h over the __u* types. 105enums
106Status: ? 106Status: ?
107 107
108qxl_drm.h
109 - Using the stdint.h uint*_t over the respective __u* ones
110Status: Trivial.
111
112r128_drm.h 108r128_drm.h
113 - Broken compat ioctls. 109 - Broken compat ioctls.
114 110
115radeon_drm.h 111radeon_drm.h
116 - Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls, 112 - Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls
117using stdint types.
118 - Both kernel and libdrm: missing padding - 113 - Both kernel and libdrm: missing padding -
119drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ? 114drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ?
120Status: ? 115Status: ?
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index 542a732b..cb077821 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -111,34 +111,34 @@ struct drm_nouveau_setparam {
111#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 111#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
112 112
113struct drm_nouveau_gem_info { 113struct drm_nouveau_gem_info {
114 uint32_t handle; 114 __u32 handle;
115 uint32_t domain; 115 __u32 domain;
116 uint64_t size; 116 __u64 size;
117 uint64_t offset; 117 __u64 offset;
118 uint64_t map_handle; 118 __u64 map_handle;
119 uint32_t tile_mode; 119 __u32 tile_mode;
120 uint32_t tile_flags; 120 __u32 tile_flags;
121}; 121};
122 122
123struct drm_nouveau_gem_new { 123struct drm_nouveau_gem_new {
124 struct drm_nouveau_gem_info info; 124 struct drm_nouveau_gem_info info;
125 uint32_t channel_hint; 125 __u32 channel_hint;
126 uint32_t align; 126 __u32 align;
127}; 127};
128 128
129#define NOUVEAU_GEM_MAX_BUFFERS 1024 129#define NOUVEAU_GEM_MAX_BUFFERS 1024
130struct drm_nouveau_gem_pushbuf_bo_presumed { 130struct drm_nouveau_gem_pushbuf_bo_presumed {
131 uint32_t valid; 131 __u32 valid;
132 uint32_t domain; 132 __u32 domain;
133 uint64_t offset; 133 __u64 offset;
134}; 134};
135 135
136struct drm_nouveau_gem_pushbuf_bo { 136struct drm_nouveau_gem_pushbuf_bo {
137 uint64_t user_priv; 137 __u64 user_priv;
138 uint32_t handle; 138 __u32 handle;
139 uint32_t read_domains; 139 __u32 read_domains;
140 uint32_t write_domains; 140 __u32 write_domains;
141 uint32_t valid_domains; 141 __u32 valid_domains;
142 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 142 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
143}; 143};
144 144
@@ -147,47 +147,47 @@ struct drm_nouveau_gem_pushbuf_bo {
147#define NOUVEAU_GEM_RELOC_OR (1 << 2) 147#define NOUVEAU_GEM_RELOC_OR (1 << 2)
148#define NOUVEAU_GEM_MAX_RELOCS 1024 148#define NOUVEAU_GEM_MAX_RELOCS 1024
149struct drm_nouveau_gem_pushbuf_reloc { 149struct drm_nouveau_gem_pushbuf_reloc {
150 uint32_t reloc_bo_index; 150 __u32 reloc_bo_index;
151 uint32_t reloc_bo_offset; 151 __u32 reloc_bo_offset;
152 uint32_t bo_index; 152 __u32 bo_index;
153 uint32_t flags; 153 __u32 flags;
154 uint32_t data; 154 __u32 data;
155 uint32_t vor; 155 __u32 vor;
156 uint32_t tor; 156 __u32 tor;
157}; 157};
158 158
159#define NOUVEAU_GEM_MAX_PUSH 512 159#define NOUVEAU_GEM_MAX_PUSH 512
160struct drm_nouveau_gem_pushbuf_push { 160struct drm_nouveau_gem_pushbuf_push {
161 uint32_t bo_index; 161 __u32 bo_index;
162 uint32_t pad; 162 __u32 pad;
163 uint64_t offset; 163 __u64 offset;
164 uint64_t length; 164 __u64 length;
165}; 165};
166 166
167struct drm_nouveau_gem_pushbuf { 167struct drm_nouveau_gem_pushbuf {
168 uint32_t channel; 168 __u32 channel;
169 uint32_t nr_buffers; 169 __u32 nr_buffers;
170 uint64_t buffers; 170 __u64 buffers;
171 uint32_t nr_relocs; 171 __u32 nr_relocs;
172 uint32_t nr_push; 172 __u32 nr_push;
173 uint64_t relocs; 173 __u64 relocs;
174 uint64_t push; 174 __u64 push;
175 uint32_t suffix0; 175 __u32 suffix0;
176 uint32_t suffix1; 176 __u32 suffix1;
177 uint64_t vram_available; 177 __u64 vram_available;
178 uint64_t gart_available; 178 __u64 gart_available;
179}; 179};
180 180
181#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 181#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
182#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 182#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
183#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 183#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
184struct drm_nouveau_gem_cpu_prep { 184struct drm_nouveau_gem_cpu_prep {
185 uint32_t handle; 185 __u32 handle;
186 uint32_t flags; 186 __u32 flags;
187}; 187};
188 188
189struct drm_nouveau_gem_cpu_fini { 189struct drm_nouveau_gem_cpu_fini {
190 uint32_t handle; 190 __u32 handle;
191}; 191};
192 192
193enum nouveau_bus_type { 193enum nouveau_bus_type {
diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h
index a520123b..38a0dbdf 100644
--- a/include/drm/qxl_drm.h
+++ b/include/drm/qxl_drm.h
@@ -52,14 +52,14 @@ extern "C" {
52#define DRM_QXL_ALLOC_SURF 0x06 52#define DRM_QXL_ALLOC_SURF 0x06
53 53
54struct drm_qxl_alloc { 54struct drm_qxl_alloc {
55 uint32_t size; 55 __u32 size;
56 uint32_t handle; /* 0 is an invalid handle */ 56 __u32 handle; /* 0 is an invalid handle */
57}; 57};
58 58
59struct drm_qxl_map { 59struct drm_qxl_map {
60 uint64_t offset; /* use for mmap system call */ 60 __u64 offset; /* use for mmap system call */
61 uint32_t handle; 61 __u32 handle;
62 uint32_t pad; 62 __u32 pad;
63}; 63};
64 64
65/* 65/*
@@ -72,59 +72,59 @@ struct drm_qxl_map {
72#define QXL_RELOC_TYPE_SURF 2 72#define QXL_RELOC_TYPE_SURF 2
73 73
74struct drm_qxl_reloc { 74struct drm_qxl_reloc {
75 uint64_t src_offset; /* offset into src_handle or src buffer */ 75 __u64 src_offset; /* offset into src_handle or src buffer */
76 uint64_t dst_offset; /* offset in dest handle */ 76 __u64 dst_offset; /* offset in dest handle */
77 uint32_t src_handle; /* dest handle to compute address from */ 77 __u32 src_handle; /* dest handle to compute address from */
78 uint32_t dst_handle; /* 0 if to command buffer */ 78 __u32 dst_handle; /* 0 if to command buffer */
79 uint32_t reloc_type; 79 __u32 reloc_type;
80 uint32_t pad; 80 __u32 pad;
81}; 81};
82 82
83struct drm_qxl_command { 83struct drm_qxl_command {
84 uint64_t command; /* void* */ 84 __u64 command; /* void* */
85 uint64_t relocs; /* struct drm_qxl_reloc* */ 85 __u64 relocs; /* struct drm_qxl_reloc* */
86 uint32_t type; 86 __u32 type;
87 uint32_t command_size; 87 __u32 command_size;
88 uint32_t relocs_num; 88 __u32 relocs_num;
89 uint32_t pad; 89 __u32 pad;
90}; 90};
91 91
92/* XXX: call it drm_qxl_commands? */ 92/* XXX: call it drm_qxl_commands? */
93struct drm_qxl_execbuffer { 93struct drm_qxl_execbuffer {
94 uint32_t flags; /* for future use */ 94 __u32 flags; /* for future use */
95 uint32_t commands_num; 95 __u32 commands_num;
96 uint64_t commands; /* struct drm_qxl_command* */ 96 __u64 commands; /* struct drm_qxl_command* */
97}; 97};
98 98
99struct drm_qxl_update_area { 99struct drm_qxl_update_area {
100 uint32_t handle; 100 __u32 handle;
101 uint32_t top; 101 __u32 top;
102 uint32_t left; 102 __u32 left;
103 uint32_t bottom; 103 __u32 bottom;
104 uint32_t right; 104 __u32 right;
105 uint32_t pad; 105 __u32 pad;
106}; 106};
107 107
108#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */ 108#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
109#define QXL_PARAM_MAX_RELOCS 2 109#define QXL_PARAM_MAX_RELOCS 2
110struct drm_qxl_getparam { 110struct drm_qxl_getparam {
111 uint64_t param; 111 __u64 param;
112 uint64_t value; 112 __u64 value;
113}; 113};
114 114
115/* these are one bit values */ 115/* these are one bit values */
116struct drm_qxl_clientcap { 116struct drm_qxl_clientcap {
117 uint32_t index; 117 __u32 index;
118 uint32_t pad; 118 __u32 pad;
119}; 119};
120 120
121struct drm_qxl_alloc_surf { 121struct drm_qxl_alloc_surf {
122 uint32_t format; 122 __u32 format;
123 uint32_t width; 123 __u32 width;
124 uint32_t height; 124 __u32 height;
125 int32_t stride; 125 __s32 stride;
126 uint32_t handle; 126 __u32 handle;
127 uint32_t pad; 127 __u32 pad;
128}; 128};
129 129
130#define DRM_IOCTL_QXL_ALLOC \ 130#define DRM_IOCTL_QXL_ALLOC \
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index f09cc04c..a1e385d6 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -797,9 +797,9 @@ typedef struct drm_radeon_surface_free {
797#define RADEON_GEM_DOMAIN_VRAM 0x4 797#define RADEON_GEM_DOMAIN_VRAM 0x4
798 798
799struct drm_radeon_gem_info { 799struct drm_radeon_gem_info {
800 uint64_t gart_size; 800 __u64 gart_size;
801 uint64_t vram_size; 801 __u64 vram_size;
802 uint64_t vram_visible; 802 __u64 vram_visible;
803}; 803};
804 804
805#define RADEON_GEM_NO_BACKING_STORE (1 << 0) 805#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
@@ -811,11 +811,11 @@ struct drm_radeon_gem_info {
811#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) 811#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
812 812
813struct drm_radeon_gem_create { 813struct drm_radeon_gem_create {
814 uint64_t size; 814 __u64 size;
815 uint64_t alignment; 815 __u64 alignment;
816 uint32_t handle; 816 __u32 handle;
817 uint32_t initial_domain; 817 __u32 initial_domain;
818 uint32_t flags; 818 __u32 flags;
819}; 819};
820 820
821/* 821/*
@@ -829,10 +829,10 @@ struct drm_radeon_gem_create {
829#define RADEON_GEM_USERPTR_REGISTER (1 << 3) 829#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
830 830
831struct drm_radeon_gem_userptr { 831struct drm_radeon_gem_userptr {
832 uint64_t addr; 832 __u64 addr;
833 uint64_t size; 833 __u64 size;
834 uint32_t flags; 834 __u32 flags;
835 uint32_t handle; 835 __u32 handle;
836}; 836};
837 837
838#define RADEON_TILING_MACRO 0x1 838#define RADEON_TILING_MACRO 0x1
@@ -855,72 +855,72 @@ struct drm_radeon_gem_userptr {
855#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 855#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
856 856
857struct drm_radeon_gem_set_tiling { 857struct drm_radeon_gem_set_tiling {
858 uint32_t handle; 858 __u32 handle;
859 uint32_t tiling_flags; 859 __u32 tiling_flags;
860 uint32_t pitch; 860 __u32 pitch;
861}; 861};
862 862
863struct drm_radeon_gem_get_tiling { 863struct drm_radeon_gem_get_tiling {
864 uint32_t handle; 864 __u32 handle;
865 uint32_t tiling_flags; 865 __u32 tiling_flags;
866 uint32_t pitch; 866 __u32 pitch;
867}; 867};
868 868
869struct drm_radeon_gem_mmap { 869struct drm_radeon_gem_mmap {
870 uint32_t handle; 870 __u32 handle;
871 uint32_t pad; 871 __u32 pad;
872 uint64_t offset; 872 __u64 offset;
873 uint64_t size; 873 __u64 size;
874 uint64_t addr_ptr; 874 __u64 addr_ptr;
875}; 875};
876 876
877struct drm_radeon_gem_set_domain { 877struct drm_radeon_gem_set_domain {
878 uint32_t handle; 878 __u32 handle;
879 uint32_t read_domains; 879 __u32 read_domains;
880 uint32_t write_domain; 880 __u32 write_domain;
881}; 881};
882 882
883struct drm_radeon_gem_wait_idle { 883struct drm_radeon_gem_wait_idle {
884 uint32_t handle; 884 __u32 handle;
885 uint32_t pad; 885 __u32 pad;
886}; 886};
887 887
888struct drm_radeon_gem_busy { 888struct drm_radeon_gem_busy {
889 uint32_t handle; 889 __u32 handle;
890 uint32_t domain; 890 __u32 domain;
891}; 891};
892 892
893struct drm_radeon_gem_pread { 893struct drm_radeon_gem_pread {
894 /** Handle for the object being read. */ 894 /** Handle for the object being read. */
895 uint32_t handle; 895 __u32 handle;
896 uint32_t pad; 896 __u32 pad;
897 /** Offset into the object to read from */ 897 /** Offset into the object to read from */
898 uint64_t offset; 898 __u64 offset;
899 /** Length of data to read */ 899 /** Length of data to read */
900 uint64_t size; 900 __u64 size;
901 /** Pointer to write the data into. */ 901 /** Pointer to write the data into. */
902 /* void *, but pointers are not 32/64 compatible */ 902 /* void *, but pointers are not 32/64 compatible */
903 uint64_t data_ptr; 903 __u64 data_ptr;
904}; 904};
905 905
906struct drm_radeon_gem_pwrite { 906struct drm_radeon_gem_pwrite {
907 /** Handle for the object being written to. */ 907 /** Handle for the object being written to. */
908 uint32_t handle; 908 __u32 handle;
909 uint32_t pad; 909 __u32 pad;
910 /** Offset into the object to write to */ 910 /** Offset into the object to write to */
911 uint64_t offset; 911 __u64 offset;
912 /** Length of data to write */ 912 /** Length of data to write */
913 uint64_t size; 913 __u64 size;
914 /** Pointer to read the data from. */ 914 /** Pointer to read the data from. */
915 /* void *, but pointers are not 32/64 compatible */ 915 /* void *, but pointers are not 32/64 compatible */
916 uint64_t data_ptr; 916 __u64 data_ptr;
917}; 917};
918 918
919/* Sets or returns a value associated with a buffer. */ 919/* Sets or returns a value associated with a buffer. */
920struct drm_radeon_gem_op { 920struct drm_radeon_gem_op {
921 uint32_t handle; /* buffer */ 921 __u32 handle; /* buffer */
922 uint32_t op; /* RADEON_GEM_OP_* */ 922 __u32 op; /* RADEON_GEM_OP_* */
923 uint64_t value; /* input or return value */ 923 __u64 value; /* input or return value */
924}; 924};
925 925
926#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 926#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
@@ -940,11 +940,11 @@ struct drm_radeon_gem_op {
940#define RADEON_VM_PAGE_SNOOPED (1 << 4) 940#define RADEON_VM_PAGE_SNOOPED (1 << 4)
941 941
942struct drm_radeon_gem_va { 942struct drm_radeon_gem_va {
943 uint32_t handle; 943 __u32 handle;
944 uint32_t operation; 944 __u32 operation;
945 uint32_t vm_id; 945 __u32 vm_id;
946 uint32_t flags; 946 __u32 flags;
947 uint64_t offset; 947 __u64 offset;
948}; 948};
949 949
950#define RADEON_CHUNK_ID_RELOCS 0x01 950#define RADEON_CHUNK_ID_RELOCS 0x01
@@ -966,29 +966,29 @@ struct drm_radeon_gem_va {
966/* 0 = normal, + = higher priority, - = lower priority */ 966/* 0 = normal, + = higher priority, - = lower priority */
967 967
968struct drm_radeon_cs_chunk { 968struct drm_radeon_cs_chunk {
969 uint32_t chunk_id; 969 __u32 chunk_id;
970 uint32_t length_dw; 970 __u32 length_dw;
971 uint64_t chunk_data; 971 __u64 chunk_data;
972}; 972};
973 973
974/* drm_radeon_cs_reloc.flags */ 974/* drm_radeon_cs_reloc.flags */
975#define RADEON_RELOC_PRIO_MASK (0xf << 0) 975#define RADEON_RELOC_PRIO_MASK (0xf << 0)
976 976
977struct drm_radeon_cs_reloc { 977struct drm_radeon_cs_reloc {
978 uint32_t handle; 978 __u32 handle;
979 uint32_t read_domains; 979 __u32 read_domains;
980 uint32_t write_domain; 980 __u32 write_domain;
981 uint32_t flags; 981 __u32 flags;
982}; 982};
983 983
984struct drm_radeon_cs { 984struct drm_radeon_cs {
985 uint32_t num_chunks; 985 __u32 num_chunks;
986 uint32_t cs_id; 986 __u32 cs_id;
987 /* this points to uint64_t * which point to cs chunks */ 987 /* this points to __u64 * which point to cs chunks */
988 uint64_t chunks; 988 __u64 chunks;
989 /* updates to the limits after this CS ioctl */ 989 /* updates to the limits after this CS ioctl */
990 uint64_t gart_limit; 990 __u64 gart_limit;
991 uint64_t vram_limit; 991 __u64 vram_limit;
992}; 992};
993 993
994#define RADEON_INFO_DEVICE_ID 0x00 994#define RADEON_INFO_DEVICE_ID 0x00
@@ -1047,9 +1047,9 @@ struct drm_radeon_cs {
1047#define RADEON_INFO_GPU_RESET_COUNTER 0x26 1047#define RADEON_INFO_GPU_RESET_COUNTER 0x26
1048 1048
1049struct drm_radeon_info { 1049struct drm_radeon_info {
1050 uint32_t request; 1050 __u32 request;
1051 uint32_t pad; 1051 __u32 pad;
1052 uint64_t value; 1052 __u64 value;
1053}; 1053};
1054 1054
1055/* Those correspond to the tile index to use, this is to explicitly state 1055/* Those correspond to the tile index to use, this is to explicitly state