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authorMarek Olšák2012-09-30 12:20:04 -0500
committerMarek Olšák2012-10-05 22:45:56 -0500
commit1aebfdc1121ccb6babb3a63dc0b99d68b4860b04 (patch)
tree3f0fd6c757f1022afbab218cce2d55c97858c0cb /radeon/radeon_surface.h
parent77413e77b82a5d800c86b7d3b864d6cc797721c9 (diff)
downloadexternal-libgbm-1aebfdc1121ccb6babb3a63dc0b99d68b4860b04.tar.gz
external-libgbm-1aebfdc1121ccb6babb3a63dc0b99d68b4860b04.tar.xz
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radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI
This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'radeon/radeon_surface.h')
-rw-r--r--radeon/radeon_surface.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index bfee8ab0..ed4b9941 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -54,6 +54,7 @@
54#define RADEON_SURF_SCANOUT (1 << 16) 54#define RADEON_SURF_SCANOUT (1 << 16)
55#define RADEON_SURF_ZBUFFER (1 << 17) 55#define RADEON_SURF_ZBUFFER (1 << 17)
56#define RADEON_SURF_SBUFFER (1 << 18) 56#define RADEON_SURF_SBUFFER (1 << 18)
57#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
57 58
58#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) 59#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
59#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) 60#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
@@ -102,6 +103,7 @@ struct radeon_surface {
102 uint32_t stencil_tile_split; 103 uint32_t stencil_tile_split;
103 uint64_t stencil_offset; 104 uint64_t stencil_offset;
104 struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL]; 105 struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
106 struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL];
105}; 107};
106 108
107struct radeon_surface_manager *radeon_surface_manager_new(int fd); 109struct radeon_surface_manager *radeon_surface_manager_new(int fd);