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authorJerome Glisse2013-04-08 12:35:37 -0500
committerJerome Glisse2013-04-12 08:46:40 -0500
commita36cdb858e21f287d7b51ded2f211f1c84bda90b (patch)
tree93f88ec4c18a694740948c7536337451e839757c /radeon/radeon_surface.h
parent309cb649a380d25a0eced4f3a0edb55d6b577099 (diff)
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radeon: add si tiling support v5
v2: Only writte tile index if flags for it is set v3: Remove useless allow2d scanout flags v4: Split radeon_drm.h update to its own patch v5: update against lastest next tree for radeon Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'radeon/radeon_surface.h')
-rw-r--r--radeon/radeon_surface.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index ed4b9941..2babfd71 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -55,6 +55,7 @@
55#define RADEON_SURF_ZBUFFER (1 << 17) 55#define RADEON_SURF_ZBUFFER (1 << 17)
56#define RADEON_SURF_SBUFFER (1 << 18) 56#define RADEON_SURF_SBUFFER (1 << 18)
57#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) 57#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
58#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
58 59
59#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) 60#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
60#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) 61#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
@@ -76,6 +77,34 @@ struct radeon_surface_level {
76 uint32_t mode; 77 uint32_t mode;
77}; 78};
78 79
80enum si_tiling_mode {
81 SI_TILING_AUTO = 0,
82
83 SI_TILING_COLOR_1D,
84 SI_TILING_COLOR_1D_SCANOUT,
85 SI_TILING_COLOR_2D_8BPP,
86 SI_TILING_COLOR_2D_16BPP,
87 SI_TILING_COLOR_2D_32BPP,
88 SI_TILING_COLOR_2D_64BPP,
89 SI_TILING_COLOR_2D_SCANOUT_16BPP,
90 SI_TILING_COLOR_2D_SCANOUT_32BPP,
91 SI_TILING_COLOR_LINEAR,
92
93 SI_TILING_STENCIL_1D,
94 SI_TILING_STENCIL_2D,
95 SI_TILING_STENCIL_2D_2AA,
96 SI_TILING_STENCIL_2D_4AA,
97 SI_TILING_STENCIL_2D_8AA,
98
99 SI_TILING_DEPTH_1D,
100 SI_TILING_DEPTH_2D,
101 SI_TILING_DEPTH_2D_2AA,
102 SI_TILING_DEPTH_2D_4AA,
103 SI_TILING_DEPTH_2D_8AA,
104
105 SI_TILING_LAST_MODE,
106};
107
79struct radeon_surface { 108struct radeon_surface {
80 uint32_t npix_x; 109 uint32_t npix_x;
81 uint32_t npix_y; 110 uint32_t npix_y;
@@ -104,6 +133,8 @@ struct radeon_surface {
104 uint64_t stencil_offset; 133 uint64_t stencil_offset;
105 struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL]; 134 struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
106 struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL]; 135 struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL];
136 uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
137 uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
107}; 138};
108 139
109struct radeon_surface_manager *radeon_surface_manager_new(int fd); 140struct radeon_surface_manager *radeon_surface_manager_new(int fd);