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authorJerome Glisse2011-12-09 20:07:15 -0600
committerJerome Glisse2012-02-01 16:11:29 -0600
commitc51f7f0e460dcadb9f1a56ecf1615810877c33c8 (patch)
tree25cfc7eba38eefb4da051ac59529b4808dec0683 /radeon/radeon_surface.h
parent151cdcfe685ee280a4344dfc40e6087d74a5590f (diff)
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radeon: add surface allocator helper v10
The surface allocator is able to build complete miptree when allocating surface for r600/r700/evergreen/northern islands GPU family. It also compute bo size and alignment for render buffer, depth buffer and scanout buffer. v2 fix r6xx/r7xx 2D tiling width align computation v3 add tile split support and fix 1d texture alignment v4 rework to more properly support compressed format, split surface pixel size and surface element size in separate fields v5 support texture array (still issue on r6xx) v6 split surface value computation and mipmap tree building, rework eg and newer computation v7 add a check for tile split and 2d tiled v8 initialize mode value before testing it in all case, reenable 2D macro tile mode on r6xx for cubemap and array. Fix cubemap to force array size to the number of face. v9 fix handling of stencil buffer on evergreen v10 on evergreen depth buffer need to have enough room for a stencil buffer just after depth one Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'radeon/radeon_surface.h')
-rw-r--r--radeon/radeon_surface.h114
1 files changed, 114 insertions, 0 deletions
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
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1/*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25/*
26 * Authors:
27 * Jérôme Glisse <jglisse@redhat.com>
28 */
29#ifndef RADEON_SURFACE_H
30#define RADEON_SURFACE_H
31
32/* Note :
33 *
34 * For texture array, the n layer are stored one after the other within each
35 * mipmap level. 0 value for field than can be hint is always valid.
36 */
37
38#define RADEON_SURF_MAX_LEVEL 32
39
40#define RADEON_SURF_TYPE_MASK 0xFF
41#define RADEON_SURF_TYPE_SHIFT 0
42#define RADEON_SURF_TYPE_1D 0
43#define RADEON_SURF_TYPE_2D 1
44#define RADEON_SURF_TYPE_3D 2
45#define RADEON_SURF_TYPE_CUBEMAP 3
46#define RADEON_SURF_TYPE_1D_ARRAY 4
47#define RADEON_SURF_TYPE_2D_ARRAY 5
48#define RADEON_SURF_MODE_MASK 0xFF
49#define RADEON_SURF_MODE_SHIFT 8
50#define RADEON_SURF_MODE_LINEAR 0
51#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
52#define RADEON_SURF_MODE_1D 2
53#define RADEON_SURF_MODE_2D 3
54#define RADEON_SURF_SCANOUT (1 << 16)
55#define RADEON_SURF_ZBUFFER (1 << 17)
56#define RADEON_SURF_SBUFFER (1 << 18)
57
58#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
59#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
60#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
61
62/* first field up to mode need to match r6 struct so that we can reuse
63 * same function for linear & linear aligned
64 */
65struct radeon_surface_level {
66 uint64_t offset;
67 uint64_t slice_size;
68 uint32_t npix_x;
69 uint32_t npix_y;
70 uint32_t npix_z;
71 uint32_t nblk_x;
72 uint32_t nblk_y;
73 uint32_t nblk_z;
74 uint32_t pitch_bytes;
75 uint32_t mode;
76};
77
78struct radeon_surface {
79 uint32_t npix_x;
80 uint32_t npix_y;
81 uint32_t npix_z;
82 uint32_t nblk_x;
83 uint32_t nblk_y;
84 uint32_t nblk_z;
85 uint32_t array_size;
86 uint32_t last_level;
87 uint32_t bpe;
88 uint32_t nsamples;
89 uint32_t flags;
90 /* Following is updated/fill by the allocator. It's allowed to
91 * set some of the value but they are use as hint and can be
92 * overridden (things lile bankw/bankh on evergreen for
93 * instance).
94 */
95 uint64_t bo_size;
96 uint64_t bo_alignment;
97 /* apply to eg */
98 uint32_t bankw;
99 uint32_t bankh;
100 uint32_t mtilea;
101 uint32_t tile_split;
102 uint32_t stencil_tile_split;
103 uint64_t stencil_offset;
104 struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
105};
106
107struct radeon_surface_manager *radeon_surface_manager_new(int fd);
108void radeon_surface_manager_free(struct radeon_surface_manager *surf_man);
109int radeon_surface_init(struct radeon_surface_manager *surf_man,
110 struct radeon_surface *surf);
111int radeon_surface_best(struct radeon_surface_manager *surf_man,
112 struct radeon_surface *surf);
113
114#endif