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authorJerome Glisse2012-02-03 11:22:11 -0600
committerJerome Glisse2012-02-03 13:42:47 -0600
commit10c0837780b2d4a33568c16bb92527e196d6c05e (patch)
tree515bb3bd240b41b32cac309cb9509696ac3f6708 /radeon
parent6a720cb8660975acea1100e61a88a92a7cb3856e (diff)
downloadexternal-libgbm-10c0837780b2d4a33568c16bb92527e196d6c05e.tar.gz
external-libgbm-10c0837780b2d4a33568c16bb92527e196d6c05e.tar.xz
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radeon: fix surface API for good before anyone start relying on it
The mipmap level computation was wrong, we need to know the block width, height, depth of compressed texture to properly compute this. Change API to provide block width, height, depth instead of nblk_x, nblk_y, nblk_z. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'radeon')
-rw-r--r--radeon/radeon_surface.c25
-rw-r--r--radeon/radeon_surface.h6
2 files changed, 11 insertions, 20 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index b2e55113..d7e91872 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -144,12 +144,12 @@ static void surf_minify(struct radeon_surface *surf,
144 uint32_t xalign, uint32_t yalign, uint32_t zalign, 144 uint32_t xalign, uint32_t yalign, uint32_t zalign,
145 unsigned offset) 145 unsigned offset)
146{ 146{
147 surf->level[level].nblk_x = mip_minify(surf->nblk_x, level);
148 surf->level[level].nblk_y = mip_minify(surf->nblk_y, level);
149 surf->level[level].nblk_z = mip_minify(surf->nblk_z, level);
150 surf->level[level].npix_x = mip_minify(surf->npix_x, level); 147 surf->level[level].npix_x = mip_minify(surf->npix_x, level);
151 surf->level[level].npix_y = mip_minify(surf->npix_y, level); 148 surf->level[level].npix_y = mip_minify(surf->npix_y, level);
152 surf->level[level].npix_z = mip_minify(surf->npix_z, level); 149 surf->level[level].npix_z = mip_minify(surf->npix_z, level);
150 surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
151 surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
152 surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
153 if (surf->level[level].mode == RADEON_SURF_MODE_2D) { 153 if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
154 if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) { 154 if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) {
155 surf->level[level].mode = RADEON_SURF_MODE_1D; 155 surf->level[level].mode = RADEON_SURF_MODE_1D;
@@ -499,12 +499,12 @@ static void eg_surf_minify(struct radeon_surface *surf,
499{ 499{
500 unsigned mtile_pr, mtile_ps; 500 unsigned mtile_pr, mtile_ps;
501 501
502 surf->level[level].nblk_x = mip_minify(surf->nblk_x, level);
503 surf->level[level].nblk_y = mip_minify(surf->nblk_y, level);
504 surf->level[level].nblk_z = mip_minify(surf->nblk_z, level);
505 surf->level[level].npix_x = mip_minify(surf->npix_x, level); 502 surf->level[level].npix_x = mip_minify(surf->npix_x, level);
506 surf->level[level].npix_y = mip_minify(surf->npix_y, level); 503 surf->level[level].npix_y = mip_minify(surf->npix_y, level);
507 surf->level[level].npix_z = mip_minify(surf->npix_z, level); 504 surf->level[level].npix_z = mip_minify(surf->npix_z, level);
505 surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
506 surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
507 surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
508 if (surf->level[level].mode == RADEON_SURF_MODE_2D) { 508 if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
509 if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) { 509 if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) {
510 surf->level[level].mode = RADEON_SURF_MODE_1D; 510 surf->level[level].mode = RADEON_SURF_MODE_1D;
@@ -595,12 +595,6 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
595 /* macro tile bytes */ 595 /* macro tile bytes */
596 mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb; 596 mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
597 597
598 /* check if surface is big enought */
599 if (surf->nblk_x < mtilew || surf->nblk_y < mtileh) {
600 surf->level[start_level].mode = RADEON_SURF_MODE_1D;
601 return eg_surface_init_1d(surf_man, surf, offset, start_level);
602 }
603
604 if (!start_level) { 598 if (!start_level) {
605 surf->bo_alignment = MAX2(256, mtileb); 599 surf->bo_alignment = MAX2(256, mtileb);
606 } 600 }
@@ -610,7 +604,7 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
610 surf->level[i].mode = RADEON_SURF_MODE_2D; 604 surf->level[i].mode = RADEON_SURF_MODE_2D;
611 eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset); 605 eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset);
612 if (surf->level[i].mode == RADEON_SURF_MODE_1D) { 606 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
613 return r6_surface_init_1d(surf_man, surf, offset, i); 607 return eg_surface_init_1d(surf_man, surf, offset, i);
614 } 608 }
615 /* level0 and first mipmap need to have alignment */ 609 /* level0 and first mipmap need to have alignment */
616 offset = surf->bo_size; 610 offset = surf->bo_size;
@@ -914,10 +908,7 @@ static int radeon_surface_sanity(struct radeon_surface_manager *surf_man,
914 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) { 908 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) {
915 return -EINVAL; 909 return -EINVAL;
916 } 910 }
917 if (!surf->nblk_x || !surf->nblk_y || !surf->nblk_z) { 911 if (!surf->blk_w || !surf->blk_h || !surf->blk_d) {
918 return -EINVAL;
919 }
920 if (surf->npix_x < surf->nblk_x || surf->npix_y < surf->nblk_y || surf->npix_z < surf->nblk_z) {
921 return -EINVAL; 912 return -EINVAL;
922 } 913 }
923 if (!surf->array_size) { 914 if (!surf->array_size) {
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index 3e5fbedc..bfee8ab0 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -79,9 +79,9 @@ struct radeon_surface {
79 uint32_t npix_x; 79 uint32_t npix_x;
80 uint32_t npix_y; 80 uint32_t npix_y;
81 uint32_t npix_z; 81 uint32_t npix_z;
82 uint32_t nblk_x; 82 uint32_t blk_w;
83 uint32_t nblk_y; 83 uint32_t blk_h;
84 uint32_t nblk_z; 84 uint32_t blk_d;
85 uint32_t array_size; 85 uint32_t array_size;
86 uint32_t last_level; 86 uint32_t last_level;
87 uint32_t bpe; 87 uint32_t bpe;