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authorJohn Stultz2018-04-13 18:31:33 -0500
committerJohn Stultz2018-04-13 18:31:33 -0500
commit84f838d71a75125b14d361f0ed7d23a0ac521edf (patch)
treea7694dfdab2ca2b1d32e25071589c7ea0a992bd6 /tests
parent2f9aea0661550a43c3d2ac33a5bc286870edd34e (diff)
parent35affe89d5f617a972b1cfee00c51cbe9e7c64a2 (diff)
downloadexternal-libgbm-84f838d71a75125b14d361f0ed7d23a0ac521edf.tar.gz
external-libgbm-84f838d71a75125b14d361f0ed7d23a0ac521edf.tar.xz
external-libgbm-84f838d71a75125b14d361f0ed7d23a0ac521edf.zip
Merge remote-tracking branch 'freedesktop/master' into aosp/master
This merges the freedesktop/master branch into aosp/master Change-Id: I3104d45924f67d37808154d04c15518394204478 Signed-off-by: John Stultz <john.stultz@linaro.org>
Diffstat (limited to 'tests')
l---------tests/amdgpu/.editorconfig1
-rw-r--r--tests/amdgpu/Makefile.am12
-rw-r--r--tests/amdgpu/amdgpu_test.c228
-rw-r--r--tests/amdgpu/amdgpu_test.h144
-rw-r--r--tests/amdgpu/basic_tests.c1122
-rw-r--r--tests/amdgpu/bo_tests.c79
-rw-r--r--tests/amdgpu/cs_tests.c74
-rw-r--r--tests/amdgpu/deadlock_tests.c255
-rw-r--r--tests/amdgpu/decode_messages.h (renamed from tests/amdgpu/uvd_messages.h)43
-rw-r--r--tests/amdgpu/frame.h2
-rw-r--r--tests/amdgpu/meson.build34
-rw-r--r--tests/amdgpu/uvd_enc_tests.c491
-rw-r--r--tests/amdgpu/uve_ib.h527
-rw-r--r--tests/amdgpu/vce_tests.c79
-rw-r--r--tests/amdgpu/vcn_tests.c398
-rw-r--r--tests/amdgpu/vm_tests.c169
-rw-r--r--tests/drmsl.c28
-rw-r--r--tests/drmstat.c419
-rw-r--r--tests/etnaviv/Makefile.am1
-rw-r--r--tests/etnaviv/etnaviv_2d_test.c4
-rw-r--r--tests/etnaviv/etnaviv_bo_cache_test.c4
-rw-r--r--tests/etnaviv/meson.build45
-rw-r--r--tests/etnaviv/write_bmp.c4
-rw-r--r--tests/exynos/exynos_fimg2d_event.c27
-rw-r--r--tests/exynos/exynos_fimg2d_perf.c34
-rw-r--r--tests/exynos/exynos_fimg2d_test.c68
-rw-r--r--tests/exynos/meson.build54
-rw-r--r--tests/kms/kms-steal-crtc.c4
-rw-r--r--tests/kms/kms-universal-planes.c4
-rw-r--r--tests/kms/libkms-test-crtc.c4
-rw-r--r--tests/kms/libkms-test-device.c13
-rw-r--r--tests/kms/libkms-test-framebuffer.c4
-rw-r--r--tests/kms/libkms-test-plane.c4
-rw-r--r--tests/kms/libkms-test-screen.c4
-rw-r--r--tests/kms/meson.build49
-rw-r--r--tests/kmstest/meson.build30
-rw-r--r--tests/meson.build86
-rw-r--r--tests/modeprint/meson.build29
-rw-r--r--tests/modeprint/modeprint.c2
-rw-r--r--tests/modetest/buffers.c4
-rw-r--r--tests/modetest/cursor.c4
-rw-r--r--tests/modetest/meson.build29
-rw-r--r--tests/modetest/modetest.c110
-rw-r--r--tests/nouveau/meson.build30
-rw-r--r--tests/nouveau/threaded.c4
-rw-r--r--tests/proptest/meson.build28
-rw-r--r--tests/radeon/meson.build27
-rw-r--r--tests/tegra/meson.build27
-rw-r--r--tests/tegra/openclose.c4
-rw-r--r--tests/util/format.c4
-rw-r--r--tests/util/kms.c7
-rw-r--r--tests/util/meson.build28
-rw-r--r--tests/util/pattern.c19
-rw-r--r--tests/vbltest/meson.build28
-rw-r--r--tests/vbltest/vbltest.c4
55 files changed, 4030 insertions, 906 deletions
diff --git a/tests/amdgpu/.editorconfig b/tests/amdgpu/.editorconfig
new file mode 120000
index 00000000..70734e42
--- /dev/null
+++ b/tests/amdgpu/.editorconfig
@@ -0,0 +1 @@
../../amdgpu/.editorconfig \ No newline at end of file
diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index c1c3a32e..e79c1bd3 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -1,7 +1,8 @@
1AM_CFLAGS = \ 1AM_CFLAGS = \
2 -I $(top_srcdir)/include/drm \ 2 -I $(top_srcdir)/include/drm \
3 -I $(top_srcdir)/amdgpu \ 3 -I $(top_srcdir)/amdgpu \
4 -I $(top_srcdir) 4 -I $(top_srcdir) \
5 -pthread
5 6
6LDADD = $(top_builddir)/libdrm.la \ 7LDADD = $(top_builddir)/libdrm.la \
7 $(top_builddir)/amdgpu/libdrm_amdgpu.la \ 8 $(top_builddir)/amdgpu/libdrm_amdgpu.la \
@@ -23,7 +24,12 @@ amdgpu_test_SOURCES = \
23 basic_tests.c \ 24 basic_tests.c \
24 bo_tests.c \ 25 bo_tests.c \
25 cs_tests.c \ 26 cs_tests.c \
26 uvd_messages.h \ 27 decode_messages.h \
27 vce_tests.c \ 28 vce_tests.c \
28 vce_ib.h \ 29 vce_ib.h \
29 frame.h 30 frame.h \
31 uvd_enc_tests.c \
32 vcn_tests.c \
33 uve_ib.h \
34 deadlock_tests.c \
35 vm_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 3fd6820a..96fcd687 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -21,10 +21,6 @@
21 * 21 *
22*/ 22*/
23 23
24#ifdef HAVE_CONFIG_H
25#include "config.h"
26#endif
27
28#include <string.h> 24#include <string.h>
29#include <stdio.h> 25#include <stdio.h>
30#include <stdlib.h> 26#include <stdlib.h>
@@ -49,6 +45,17 @@
49#include "CUnit/Basic.h" 45#include "CUnit/Basic.h"
50 46
51#include "amdgpu_test.h" 47#include "amdgpu_test.h"
48#include "amdgpu_internal.h"
49
50/* Test suite names */
51#define BASIC_TESTS_STR "Basic Tests"
52#define BO_TESTS_STR "BO Tests"
53#define CS_TESTS_STR "CS Tests"
54#define VCE_TESTS_STR "VCE Tests"
55#define VCN_TESTS_STR "VCN Tests"
56#define UVD_ENC_TESTS_STR "UVD ENC Tests"
57#define DEADLOCK_TESTS_STR "Deadlock Tests"
58#define VM_TESTS_STR "VM Tests"
52 59
53/** 60/**
54 * Open handles for amdgpu devices 61 * Open handles for amdgpu devices
@@ -62,49 +69,150 @@ int open_render_node = 0; /* By default run most tests on primary node */
62/** The table of all known test suites to run */ 69/** The table of all known test suites to run */
63static CU_SuiteInfo suites[] = { 70static CU_SuiteInfo suites[] = {
64 { 71 {
65 .pName = "Basic Tests", 72 .pName = BASIC_TESTS_STR,
66 .pInitFunc = suite_basic_tests_init, 73 .pInitFunc = suite_basic_tests_init,
67 .pCleanupFunc = suite_basic_tests_clean, 74 .pCleanupFunc = suite_basic_tests_clean,
68 .pTests = basic_tests, 75 .pTests = basic_tests,
69 }, 76 },
70 { 77 {
71 .pName = "BO Tests", 78 .pName = BO_TESTS_STR,
72 .pInitFunc = suite_bo_tests_init, 79 .pInitFunc = suite_bo_tests_init,
73 .pCleanupFunc = suite_bo_tests_clean, 80 .pCleanupFunc = suite_bo_tests_clean,
74 .pTests = bo_tests, 81 .pTests = bo_tests,
75 }, 82 },
76 { 83 {
77 .pName = "CS Tests", 84 .pName = CS_TESTS_STR,
78 .pInitFunc = suite_cs_tests_init, 85 .pInitFunc = suite_cs_tests_init,
79 .pCleanupFunc = suite_cs_tests_clean, 86 .pCleanupFunc = suite_cs_tests_clean,
80 .pTests = cs_tests, 87 .pTests = cs_tests,
81 }, 88 },
82 { 89 {
83 .pName = "VCE Tests", 90 .pName = VCE_TESTS_STR,
84 .pInitFunc = suite_vce_tests_init, 91 .pInitFunc = suite_vce_tests_init,
85 .pCleanupFunc = suite_vce_tests_clean, 92 .pCleanupFunc = suite_vce_tests_clean,
86 .pTests = vce_tests, 93 .pTests = vce_tests,
87 }, 94 },
95 {
96 .pName = VCN_TESTS_STR,
97 .pInitFunc = suite_vcn_tests_init,
98 .pCleanupFunc = suite_vcn_tests_clean,
99 .pTests = vcn_tests,
100 },
101 {
102 .pName = UVD_ENC_TESTS_STR,
103 .pInitFunc = suite_uvd_enc_tests_init,
104 .pCleanupFunc = suite_uvd_enc_tests_clean,
105 .pTests = uvd_enc_tests,
106 },
107 {
108 .pName = DEADLOCK_TESTS_STR,
109 .pInitFunc = suite_deadlock_tests_init,
110 .pCleanupFunc = suite_deadlock_tests_clean,
111 .pTests = deadlock_tests,
112 },
113 {
114 .pName = VM_TESTS_STR,
115 .pInitFunc = suite_vm_tests_init,
116 .pCleanupFunc = suite_vm_tests_clean,
117 .pTests = vm_tests,
118 },
119
88 CU_SUITE_INFO_NULL, 120 CU_SUITE_INFO_NULL,
89}; 121};
90 122
123typedef CU_BOOL (*active__stat_func)(void);
91 124
92/** Display information about all suites and their tests */ 125typedef struct Suites_Active_Status {
126 char* pName;
127 active__stat_func pActive;
128}Suites_Active_Status;
129
130static CU_BOOL always_active()
131{
132 return CU_TRUE;
133}
134
135static Suites_Active_Status suites_active_stat[] = {
136 {
137 .pName = BASIC_TESTS_STR,
138 .pActive = always_active,
139 },
140 {
141 .pName = BO_TESTS_STR,
142 .pActive = always_active,
143 },
144 {
145 .pName = CS_TESTS_STR,
146 .pActive = suite_cs_tests_enable,
147 },
148 {
149 .pName = VCE_TESTS_STR,
150 .pActive = suite_vce_tests_enable,
151 },
152 {
153 .pName = VCN_TESTS_STR,
154 .pActive = suite_vcn_tests_enable,
155 },
156 {
157 .pName = UVD_ENC_TESTS_STR,
158 .pActive = suite_uvd_enc_tests_enable,
159 },
160 {
161 .pName = DEADLOCK_TESTS_STR,
162 .pActive = suite_deadlock_tests_enable,
163 },
164 {
165 .pName = VM_TESTS_STR,
166 .pActive = suite_vm_tests_enable,
167 },
168};
169
170
171/*
172 * Display information about all suites and their tests
173 *
174 * NOTE: Must be run after registry is initialized and suites registered.
175 */
93static void display_test_suites(void) 176static void display_test_suites(void)
94{ 177{
95 int iSuite; 178 int iSuite;
96 int iTest; 179 int iTest;
180 CU_pSuite pSuite = NULL;
181 CU_pTest pTest = NULL;
97 182
98 printf("Suites\n"); 183 printf("Suites\n");
99 184
100 for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) { 185 for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) {
101 printf("Suite id = %d: Name '%s'\n", 186
102 iSuite + 1, suites[iSuite].pName); 187 pSuite = CU_get_suite_by_index((unsigned int) iSuite + 1,
188 CU_get_registry());
189
190 if (!pSuite) {
191 fprintf(stderr, "Invalid suite id : %d\n", iSuite + 1);
192 continue;
193 }
194
195 printf("Suite id = %d: Name '%s status: %s'\n",
196 iSuite + 1, suites[iSuite].pName,
197 pSuite->fActive ? "ENABLED" : "DISABLED");
198
199
103 200
104 for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL; 201 for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL;
105 iTest++) { 202 iTest++) {
106 printf(" Test id %d: Name: '%s'\n", iTest + 1, 203
107 suites[iSuite].pTests[iTest].pName); 204 pTest = CU_get_test_by_index((unsigned int) iTest + 1,
205 pSuite);
206
207 if (!pTest) {
208 fprintf(stderr, "Invalid test id : %d\n", iTest + 1);
209 continue;
210 }
211
212 printf("Test id %d: Name: '%s status: %s'\n", iTest + 1,
213 suites[iSuite].pTests[iTest].pName,
214 pSuite->fActive && pTest->fActive ?
215 "ENABLED" : "DISABLED");
108 } 216 }
109 } 217 }
110} 218}
@@ -112,7 +220,7 @@ static void display_test_suites(void)
112 220
113/** Help string for command line parameters */ 221/** Help string for command line parameters */
114static const char usage[] = 222static const char usage[] =
115 "Usage: %s [-hlpr] [<-s <suite id>> [-t <test id>]] " 223 "Usage: %s [-hlpr] [<-s <suite id>> [-t <test id>] [-f]] "
116 "[-b <pci_bus_id> [-d <pci_device_id>]]\n" 224 "[-b <pci_bus_id> [-d <pci_device_id>]]\n"
117 "where:\n" 225 "where:\n"
118 " l - Display all suites and their tests\n" 226 " l - Display all suites and their tests\n"
@@ -120,9 +228,10 @@ static const char usage[] =
120 " b - Specify device's PCI bus id to run tests\n" 228 " b - Specify device's PCI bus id to run tests\n"
121 " d - Specify device's PCI device id to run tests (optional)\n" 229 " d - Specify device's PCI device id to run tests (optional)\n"
122 " p - Display information of AMDGPU devices in system\n" 230 " p - Display information of AMDGPU devices in system\n"
231 " f - Force executing inactive suite or test\n"
123 " h - Display this help\n"; 232 " h - Display this help\n";
124/** Specified options strings for getopt */ 233/** Specified options strings for getopt */
125static const char options[] = "hlrps:t:b:d:"; 234static const char options[] = "hlrps:t:b:d:f";
126 235
127/* Open AMD devices. 236/* Open AMD devices.
128 * Return the number of AMD device openned. 237 * Return the number of AMD device openned.
@@ -130,7 +239,6 @@ static const char options[] = "hlrps:t:b:d:";
130static int amdgpu_open_devices(int open_render_node) 239static int amdgpu_open_devices(int open_render_node)
131{ 240{
132 drmDevicePtr devices[MAX_CARDS_SUPPORTED]; 241 drmDevicePtr devices[MAX_CARDS_SUPPORTED];
133 int ret;
134 int i; 242 int i;
135 int drm_node; 243 int drm_node;
136 int amd_index = 0; 244 int amd_index = 0;
@@ -264,29 +372,71 @@ static void amdgpu_print_devices()
264/* Find a match AMD device in PCI bus 372/* Find a match AMD device in PCI bus
265 * Return the index of the device or -1 if not found 373 * Return the index of the device or -1 if not found
266 */ 374 */
267static int amdgpu_find_device(uint8_t bus, uint8_t dev) 375static int amdgpu_find_device(uint8_t bus, uint16_t dev)
268{ 376{
269 int i; 377 int i;
270 drmDevicePtr device; 378 drmDevicePtr device;
271 379
272 for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++) 380 for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
273 if (drmGetDevice2(drm_amdgpu[i], 381 if (drmGetDevice2(drm_amdgpu[i],
274 DRM_DEVICE_GET_PCI_REVISION, 382 DRM_DEVICE_GET_PCI_REVISION,
275 &device) == 0) { 383 &device) == 0) {
276 if (device->bustype == DRM_BUS_PCI) 384 if (device->bustype == DRM_BUS_PCI)
277 if (device->businfo.pci->bus == bus && 385 if ((bus == 0xFF || device->businfo.pci->bus == bus) &&
278 device->businfo.pci->dev == dev) { 386 device->deviceinfo.pci->device_id == dev) {
279
280 drmFreeDevice(&device); 387 drmFreeDevice(&device);
281 return i; 388 return i;
282 } 389 }
283 390
284 drmFreeDevice(&device); 391 drmFreeDevice(&device);
285 } 392 }
393 }
286 394
287 return -1; 395 return -1;
288} 396}
289 397
398static void amdgpu_disable_suites()
399{
400 amdgpu_device_handle device_handle;
401 uint32_t major_version, minor_version, family_id;
402 int i;
403 int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]);
404
405 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
406 &minor_version, &device_handle))
407 return;
408
409 family_id = device_handle->info.family_id;
410
411 if (amdgpu_device_deinitialize(device_handle))
412 return;
413
414 /* Set active status for suites based on their policies */
415 for (i = 0; i < size; ++i)
416 if (amdgpu_set_suite_active(suites_active_stat[i].pName,
417 suites_active_stat[i].pActive()))
418 fprintf(stderr, "suite deactivation failed - %s\n", CU_get_error_msg());
419
420 /* Explicitly disable specific tests due to known bugs or preferences */
421 /*
422 * BUG: Compute ring stalls and never recovers when the address is
423 * written after the command already submitted
424 */
425 if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, "compute ring block test", CU_FALSE))
426 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
427
428 if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
429 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
430
431 if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE))
432 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
433
434 /* This test was ran on GFX8 and GFX9 only */
435 if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
436 if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE))
437 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
438}
439
290/* The main() function for setting up and running the tests. 440/* The main() function for setting up and running the tests.
291 * Returns a CUE_SUCCESS on successful running, another 441 * Returns a CUE_SUCCESS on successful running, another
292 * CUnit error code on failure. 442 * CUnit error code on failure.
@@ -303,6 +453,8 @@ int main(int argc, char **argv)
303 CU_pSuite pSuite = NULL; 453 CU_pSuite pSuite = NULL;
304 CU_pTest pTest = NULL; 454 CU_pTest pTest = NULL;
305 int test_device_index; 455 int test_device_index;
456 int display_list = 0;
457 int force_run = 0;
306 458
307 for (i = 0; i < MAX_CARDS_SUPPORTED; i++) 459 for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
308 drm_amdgpu[i] = -1; 460 drm_amdgpu[i] = -1;
@@ -313,8 +465,8 @@ int main(int argc, char **argv)
313 while ((c = getopt(argc, argv, options)) != -1) { 465 while ((c = getopt(argc, argv, options)) != -1) {
314 switch (c) { 466 switch (c) {
315 case 'l': 467 case 'l':
316 display_test_suites(); 468 display_list = 1;
317 exit(EXIT_SUCCESS); 469 break;
318 case 's': 470 case 's':
319 suite_id = atoi(optarg); 471 suite_id = atoi(optarg);
320 break; 472 break;
@@ -325,7 +477,7 @@ int main(int argc, char **argv)
325 pci_bus_id = atoi(optarg); 477 pci_bus_id = atoi(optarg);
326 break; 478 break;
327 case 'd': 479 case 'd':
328 pci_device_id = atoi(optarg); 480 sscanf(optarg, "%x", &pci_device_id);
329 break; 481 break;
330 case 'p': 482 case 'p':
331 display_devices = 1; 483 display_devices = 1;
@@ -333,6 +485,9 @@ int main(int argc, char **argv)
333 case 'r': 485 case 'r':
334 open_render_node = 1; 486 open_render_node = 1;
335 break; 487 break;
488 case 'f':
489 force_run = 1;
490 break;
336 case '?': 491 case '?':
337 case 'h': 492 case 'h':
338 fprintf(stderr, usage, argv[0]); 493 fprintf(stderr, usage, argv[0]);
@@ -359,10 +514,10 @@ int main(int argc, char **argv)
359 exit(EXIT_SUCCESS); 514 exit(EXIT_SUCCESS);
360 } 515 }
361 516
362 if (pci_bus_id > 0) { 517 if (pci_bus_id > 0 || pci_device_id) {
363 /* A device was specified to run the test */ 518 /* A device was specified to run the test */
364 test_device_index = amdgpu_find_device((uint8_t)pci_bus_id, 519 test_device_index = amdgpu_find_device(pci_bus_id,
365 (uint8_t)pci_device_id); 520 pci_device_id);
366 521
367 if (test_device_index >= 0) { 522 if (test_device_index >= 0) {
368 /* Most tests run on device of drm_amdgpu[0]. 523 /* Most tests run on device of drm_amdgpu[0].
@@ -398,17 +553,33 @@ int main(int argc, char **argv)
398 /* Run tests using the CUnit Basic interface */ 553 /* Run tests using the CUnit Basic interface */
399 CU_basic_set_mode(CU_BRM_VERBOSE); 554 CU_basic_set_mode(CU_BRM_VERBOSE);
400 555
556 /* Disable suites and individual tests based on misc. conditions */
557 amdgpu_disable_suites();
558
559 if (display_list) {
560 display_test_suites();
561 goto end;
562 }
563
401 if (suite_id != -1) { /* If user specify particular suite? */ 564 if (suite_id != -1) { /* If user specify particular suite? */
402 pSuite = CU_get_suite_by_index((unsigned int) suite_id, 565 pSuite = CU_get_suite_by_index((unsigned int) suite_id,
403 CU_get_registry()); 566 CU_get_registry());
404 567
405 if (pSuite) { 568 if (pSuite) {
569
570 if (force_run)
571 CU_set_suite_active(pSuite, CU_TRUE);
572
406 if (test_id != -1) { /* If user specify test id */ 573 if (test_id != -1) { /* If user specify test id */
407 pTest = CU_get_test_by_index( 574 pTest = CU_get_test_by_index(
408 (unsigned int) test_id, 575 (unsigned int) test_id,
409 pSuite); 576 pSuite);
410 if (pTest) 577 if (pTest) {
578 if (force_run)
579 CU_set_test_active(pTest, CU_TRUE);
580
411 CU_basic_run_test(pSuite, pTest); 581 CU_basic_run_test(pSuite, pTest);
582 }
412 else { 583 else {
413 fprintf(stderr, "Invalid test id: %d\n", 584 fprintf(stderr, "Invalid test id: %d\n",
414 test_id); 585 test_id);
@@ -428,6 +599,7 @@ int main(int argc, char **argv)
428 } else 599 } else
429 CU_basic_run_tests(); 600 CU_basic_run_tests();
430 601
602end:
431 CU_cleanup_registry(); 603 CU_cleanup_registry();
432 amdgpu_close_devices(); 604 amdgpu_close_devices();
433 return CU_get_error(); 605 return CU_get_error();
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index e30e2312..62875736 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -85,6 +85,11 @@ int suite_cs_tests_init();
85int suite_cs_tests_clean(); 85int suite_cs_tests_clean();
86 86
87/** 87/**
88 * Decide if the suite is enabled by default or not.
89 */
90CU_BOOL suite_cs_tests_enable(void);
91
92/**
88 * Tests in cs test suite 93 * Tests in cs test suite
89 */ 94 */
90extern CU_TestInfo cs_tests[]; 95extern CU_TestInfo cs_tests[];
@@ -100,11 +105,96 @@ int suite_vce_tests_init();
100int suite_vce_tests_clean(); 105int suite_vce_tests_clean();
101 106
102/** 107/**
108 * Decide if the suite is enabled by default or not.
109 */
110CU_BOOL suite_vce_tests_enable(void);
111
112/**
103 * Tests in vce test suite 113 * Tests in vce test suite
104 */ 114 */
105extern CU_TestInfo vce_tests[]; 115extern CU_TestInfo vce_tests[];
106 116
107/** 117/**
118+ * Initialize vcn test suite
119+ */
120int suite_vcn_tests_init();
121
122/**
123+ * Deinitialize vcn test suite
124+ */
125int suite_vcn_tests_clean();
126
127/**
128 * Decide if the suite is enabled by default or not.
129 */
130CU_BOOL suite_vcn_tests_enable(void);
131
132/**
133+ * Tests in vcn test suite
134+ */
135extern CU_TestInfo vcn_tests[];
136
137/**
138 * Initialize uvd enc test suite
139 */
140int suite_uvd_enc_tests_init();
141
142/**
143 * Deinitialize uvd enc test suite
144 */
145int suite_uvd_enc_tests_clean();
146
147/**
148 * Decide if the suite is enabled by default or not.
149 */
150CU_BOOL suite_uvd_enc_tests_enable(void);
151
152/**
153 * Tests in uvd enc test suite
154 */
155extern CU_TestInfo uvd_enc_tests[];
156
157/**
158 * Initialize deadlock test suite
159 */
160int suite_deadlock_tests_init();
161
162/**
163 * Deinitialize deadlock test suite
164 */
165int suite_deadlock_tests_clean();
166
167/**
168 * Decide if the suite is enabled by default or not.
169 */
170CU_BOOL suite_deadlock_tests_enable(void);
171
172/**
173 * Tests in uvd enc test suite
174 */
175extern CU_TestInfo deadlock_tests[];
176
177/**
178 * Initialize vm test suite
179 */
180int suite_vm_tests_init();
181
182/**
183 * Deinitialize deadlock test suite
184 */
185int suite_vm_tests_clean();
186
187/**
188 * Decide if the suite is enabled by default or not.
189 */
190CU_BOOL suite_vm_tests_enable(void);
191
192/**
193 * Tests in vm test suite
194 */
195extern CU_TestInfo vm_tests[];
196
197/**
108 * Helper functions 198 * Helper functions
109 */ 199 */
110static inline amdgpu_bo_handle gpu_mem_alloc( 200static inline amdgpu_bo_handle gpu_mem_alloc(
@@ -162,6 +252,29 @@ static inline int gpu_mem_free(amdgpu_bo_handle bo,
162} 252}
163 253
164static inline int 254static inline int
255amdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size,
256 unsigned alignment, unsigned heap, uint64_t flags,
257 amdgpu_bo_handle *bo)
258{
259 struct amdgpu_bo_alloc_request request = {};
260 amdgpu_bo_handle buf_handle;
261 int r;
262
263 request.alloc_size = size;
264 request.phys_alignment = alignment;
265 request.preferred_heap = heap;
266 request.flags = flags;
267
268 r = amdgpu_bo_alloc(dev, &request, &buf_handle);
269 if (r)
270 return r;
271
272 *bo = buf_handle;
273
274 return 0;
275}
276
277static inline int
165amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size, 278amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
166 unsigned alignment, unsigned heap, uint64_t flags, 279 unsigned alignment, unsigned heap, uint64_t flags,
167 amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address, 280 amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
@@ -236,4 +349,35 @@ amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1,
236 return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list); 349 return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list);
237} 350}
238 351
352
353static inline CU_ErrorCode amdgpu_set_suite_active(const char *suite_name,
354 CU_BOOL active)
355{
356 CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suite_name), active);
357
358 if (r != CUE_SUCCESS)
359 fprintf(stderr, "Failed to obtain suite %s\n", suite_name);
360
361 return r;
362}
363
364static inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name,
365 const char *test_name, CU_BOOL active)
366{
367 CU_ErrorCode r;
368 CU_pSuite pSuite = CU_get_suite(suite_name);
369
370 if (!pSuite) {
371 fprintf(stderr, "Failed to obtain suite %s\n",
372 suite_name);
373 return CUE_NOSUITE;
374 }
375
376 r = CU_set_test_active(CU_get_test(pSuite, test_name), active);
377 if (r != CUE_SUCCESS)
378 fprintf(stderr, "Failed to obtain test %s\n", test_name);
379
380 return r;
381}
382
239#endif /* #ifdef _AMDGPU_TEST_H_ */ 383#endif /* #ifdef _AMDGPU_TEST_H_ */
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index bfda21b1..1adbddd9 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -21,16 +21,13 @@
21 * 21 *
22*/ 22*/
23 23
24#ifdef HAVE_CONFIG_H
25#include "config.h"
26#endif
27
28#include <stdio.h> 24#include <stdio.h>
29#include <stdlib.h> 25#include <stdlib.h>
30#include <unistd.h> 26#include <unistd.h>
31#ifdef HAVE_ALLOCA_H 27#ifdef HAVE_ALLOCA_H
32# include <alloca.h> 28# include <alloca.h>
33#endif 29#endif
30#include <sys/wait.h>
34 31
35#include "CUnit/Basic.h" 32#include "CUnit/Basic.h"
36 33
@@ -40,27 +37,38 @@
40static amdgpu_device_handle device_handle; 37static amdgpu_device_handle device_handle;
41static uint32_t major_version; 38static uint32_t major_version;
42static uint32_t minor_version; 39static uint32_t minor_version;
40static uint32_t family_id;
43 41
44static void amdgpu_query_info_test(void); 42static void amdgpu_query_info_test(void);
45static void amdgpu_memory_alloc(void);
46static void amdgpu_command_submission_gfx(void); 43static void amdgpu_command_submission_gfx(void);
47static void amdgpu_command_submission_compute(void); 44static void amdgpu_command_submission_compute(void);
45static void amdgpu_command_submission_multi_fence(void);
48static void amdgpu_command_submission_sdma(void); 46static void amdgpu_command_submission_sdma(void);
49static void amdgpu_userptr_test(void); 47static void amdgpu_userptr_test(void);
50static void amdgpu_semaphore_test(void); 48static void amdgpu_semaphore_test(void);
49static void amdgpu_sync_dependency_test(void);
50static void amdgpu_bo_eviction_test(void);
51 51
52static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); 52static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
53static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); 53static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
54static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type); 54static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type);
55 55static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
56 unsigned ip_type,
57 int instance, int pm4_dw, uint32_t *pm4_src,
58 int res_cnt, amdgpu_bo_handle *resources,
59 struct amdgpu_cs_ib_info *ib_info,
60 struct amdgpu_cs_request *ibs_request);
61
56CU_TestInfo basic_tests[] = { 62CU_TestInfo basic_tests[] = {
57 { "Query Info Test", amdgpu_query_info_test }, 63 { "Query Info Test", amdgpu_query_info_test },
58 { "Memory alloc Test", amdgpu_memory_alloc },
59 { "Userptr Test", amdgpu_userptr_test }, 64 { "Userptr Test", amdgpu_userptr_test },
65 { "bo eviction Test", amdgpu_bo_eviction_test },
60 { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, 66 { "Command submission Test (GFX)", amdgpu_command_submission_gfx },
61 { "Command submission Test (Compute)", amdgpu_command_submission_compute }, 67 { "Command submission Test (Compute)", amdgpu_command_submission_compute },
68 { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence },
62 { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, 69 { "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
63 { "SW semaphore Test", amdgpu_semaphore_test }, 70 { "SW semaphore Test", amdgpu_semaphore_test },
71 { "Sync dependency Test", amdgpu_sync_dependency_test },
64 CU_TEST_INFO_NULL, 72 CU_TEST_INFO_NULL,
65}; 73};
66#define BUFFER_SIZE (8 * 1024) 74#define BUFFER_SIZE (8 * 1024)
@@ -197,22 +205,110 @@ CU_TestInfo basic_tests[] = {
197# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 205# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
198# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 206# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
199 207
208#define SDMA_PACKET_SI(op, b, t, s, cnt) ((((op) & 0xF) << 28) | \
209 (((b) & 0x1) << 26) | \
210 (((t) & 0x1) << 23) | \
211 (((s) & 0x1) << 22) | \
212 (((cnt) & 0xFFFFF) << 0))
213#define SDMA_OPCODE_COPY_SI 3
214#define SDMA_OPCODE_CONSTANT_FILL_SI 13
215#define SDMA_NOP_SI 0xf
216#define GFX_COMPUTE_NOP_SI 0x80000000
217#define PACKET3_DMA_DATA_SI 0x41
218# define PACKET3_DMA_DATA_SI_ENGINE(x) ((x) << 27)
219 /* 0 - ME
220 * 1 - PFP
221 */
222# define PACKET3_DMA_DATA_SI_DST_SEL(x) ((x) << 20)
223 /* 0 - DST_ADDR using DAS
224 * 1 - GDS
225 * 3 - DST_ADDR using L2
226 */
227# define PACKET3_DMA_DATA_SI_SRC_SEL(x) ((x) << 29)
228 /* 0 - SRC_ADDR using SAS
229 * 1 - GDS
230 * 2 - DATA
231 * 3 - SRC_ADDR using L2
232 */
233# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31)
234
235
236#define PKT3_CONTEXT_CONTROL 0x28
237#define CONTEXT_CONTROL_LOAD_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
238#define CONTEXT_CONTROL_LOAD_CE_RAM(x) (((unsigned)(x) & 0x1) << 28)
239#define CONTEXT_CONTROL_SHADOW_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
240
241#define PKT3_CLEAR_STATE 0x12
242
243#define PKT3_SET_SH_REG 0x76
244#define PACKET3_SET_SH_REG_START 0x00002c00
245
246#define PACKET3_DISPATCH_DIRECT 0x15
247
248
249/* gfx 8 */
250#define mmCOMPUTE_PGM_LO 0x2e0c
251#define mmCOMPUTE_PGM_RSRC1 0x2e12
252#define mmCOMPUTE_TMPRING_SIZE 0x2e18
253#define mmCOMPUTE_USER_DATA_0 0x2e40
254#define mmCOMPUTE_USER_DATA_1 0x2e41
255#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
256#define mmCOMPUTE_NUM_THREAD_X 0x2e07
257
258
259
260#define SWAP_32(num) (((num & 0xff000000) >> 24) | \
261 ((num & 0x0000ff00) << 8) | \
262 ((num & 0x00ff0000) >> 8) | \
263 ((num & 0x000000ff) << 24))
264
265
266/* Shader code
267 * void main()
268{
269
270 float x = some_input;
271 for (unsigned i = 0; i < 1000000; i++)
272 x = sin(x);
273
274 u[0] = 42u;
275}
276*/
277
278static uint32_t shader_bin[] = {
279 SWAP_32(0x800082be), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0x040085bf),
280 SWAP_32(0x02810281), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0xfcff84bf),
281 SWAP_32(0xff0083be), SWAP_32(0x00f00000), SWAP_32(0xc10082be), SWAP_32(0xaa02007e),
282 SWAP_32(0x000070e0), SWAP_32(0x00000080), SWAP_32(0x000081bf)
283};
284
285#define CODE_OFFSET 512
286#define DATA_OFFSET 1024
287
288
200int suite_basic_tests_init(void) 289int suite_basic_tests_init(void)
201{ 290{
291 struct amdgpu_gpu_info gpu_info = {0};
202 int r; 292 int r;
203 293
204 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 294 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
205 &minor_version, &device_handle); 295 &minor_version, &device_handle);
206 296
207 if (r == 0) 297 if (r) {
208 return CUE_SUCCESS;
209 else {
210 if ((r == -EACCES) && (errno == EACCES)) 298 if ((r == -EACCES) && (errno == EACCES))
211 printf("\n\nError:%s. " 299 printf("\n\nError:%s. "
212 "Hint:Try to run this test program as root.", 300 "Hint:Try to run this test program as root.",
213 strerror(errno)); 301 strerror(errno));
214 return CUE_SINIT_FAILED; 302 return CUE_SINIT_FAILED;
215 } 303 }
304
305 r = amdgpu_query_gpu_info(device_handle, &gpu_info);
306 if (r)
307 return CUE_SINIT_FAILED;
308
309 family_id = gpu_info.family_id;
310
311 return CUE_SUCCESS;
216} 312}
217 313
218int suite_basic_tests_clean(void) 314int suite_basic_tests_clean(void)
@@ -239,53 +335,6 @@ static void amdgpu_query_info_test(void)
239 CU_ASSERT_EQUAL(r, 0); 335 CU_ASSERT_EQUAL(r, 0);
240} 336}
241 337
242static void amdgpu_memory_alloc(void)
243{
244 amdgpu_bo_handle bo;
245 amdgpu_va_handle va_handle;
246 uint64_t bo_mc;
247 int r;
248
249 /* Test visible VRAM */
250 bo = gpu_mem_alloc(device_handle,
251 4096, 4096,
252 AMDGPU_GEM_DOMAIN_VRAM,
253 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
254 &bo_mc, &va_handle);
255
256 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
257 CU_ASSERT_EQUAL(r, 0);
258
259 /* Test invisible VRAM */
260 bo = gpu_mem_alloc(device_handle,
261 4096, 4096,
262 AMDGPU_GEM_DOMAIN_VRAM,
263 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
264 &bo_mc, &va_handle);
265
266 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
267 CU_ASSERT_EQUAL(r, 0);
268
269 /* Test GART Cacheable */
270 bo = gpu_mem_alloc(device_handle,
271 4096, 4096,
272 AMDGPU_GEM_DOMAIN_GTT,
273 0, &bo_mc, &va_handle);
274
275 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
276 CU_ASSERT_EQUAL(r, 0);
277
278 /* Test GART USWC */
279 bo = gpu_mem_alloc(device_handle,
280 4096, 4096,
281 AMDGPU_GEM_DOMAIN_GTT,
282 AMDGPU_GEM_CREATE_CPU_GTT_USWC,
283 &bo_mc, &va_handle);
284
285 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
286 CU_ASSERT_EQUAL(r, 0);
287}
288
289static void amdgpu_command_submission_gfx_separate_ibs(void) 338static void amdgpu_command_submission_gfx_separate_ibs(void)
290{ 339{
291 amdgpu_context_handle context_handle; 340 amdgpu_context_handle context_handle;
@@ -299,7 +348,7 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
299 uint32_t expired; 348 uint32_t expired;
300 amdgpu_bo_list_handle bo_list; 349 amdgpu_bo_list_handle bo_list;
301 amdgpu_va_handle va_handle, va_handle_ce; 350 amdgpu_va_handle va_handle, va_handle_ce;
302 int r; 351 int r, i = 0;
303 352
304 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 353 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
305 CU_ASSERT_EQUAL(r, 0); 354 CU_ASSERT_EQUAL(r, 0);
@@ -324,12 +373,14 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
324 373
325 /* IT_SET_CE_DE_COUNTERS */ 374 /* IT_SET_CE_DE_COUNTERS */
326 ptr = ib_result_ce_cpu; 375 ptr = ib_result_ce_cpu;
327 ptr[0] = 0xc0008900; 376 if (family_id != AMDGPU_FAMILY_SI) {
328 ptr[1] = 0; 377 ptr[i++] = 0xc0008900;
329 ptr[2] = 0xc0008400; 378 ptr[i++] = 0;
330 ptr[3] = 1; 379 }
380 ptr[i++] = 0xc0008400;
381 ptr[i++] = 1;
331 ib_info[0].ib_mc_address = ib_result_ce_mc_address; 382 ib_info[0].ib_mc_address = ib_result_ce_mc_address;
332 ib_info[0].size = 4; 383 ib_info[0].size = i;
333 ib_info[0].flags = AMDGPU_IB_FLAG_CE; 384 ib_info[0].flags = AMDGPU_IB_FLAG_CE;
334 385
335 /* IT_WAIT_ON_CE_COUNTER */ 386 /* IT_WAIT_ON_CE_COUNTER */
@@ -388,7 +439,7 @@ static void amdgpu_command_submission_gfx_shared_ib(void)
388 uint32_t expired; 439 uint32_t expired;
389 amdgpu_bo_list_handle bo_list; 440 amdgpu_bo_list_handle bo_list;
390 amdgpu_va_handle va_handle; 441 amdgpu_va_handle va_handle;
391 int r; 442 int r, i = 0;
392 443
393 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 444 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
394 CU_ASSERT_EQUAL(r, 0); 445 CU_ASSERT_EQUAL(r, 0);
@@ -407,12 +458,14 @@ static void amdgpu_command_submission_gfx_shared_ib(void)
407 458
408 /* IT_SET_CE_DE_COUNTERS */ 459 /* IT_SET_CE_DE_COUNTERS */
409 ptr = ib_result_cpu; 460 ptr = ib_result_cpu;
410 ptr[0] = 0xc0008900; 461 if (family_id != AMDGPU_FAMILY_SI) {
411 ptr[1] = 0; 462 ptr[i++] = 0xc0008900;
412 ptr[2] = 0xc0008400; 463 ptr[i++] = 0;
413 ptr[3] = 1; 464 }
465 ptr[i++] = 0xc0008400;
466 ptr[i++] = 1;
414 ib_info[0].ib_mc_address = ib_result_mc_address; 467 ib_info[0].ib_mc_address = ib_result_mc_address;
415 ib_info[0].size = 4; 468 ib_info[0].size = i;
416 ib_info[0].flags = AMDGPU_IB_FLAG_CE; 469 ib_info[0].flags = AMDGPU_IB_FLAG_CE;
417 470
418 ptr = (uint32_t *)ib_result_cpu + 4; 471 ptr = (uint32_t *)ib_result_cpu + 4;
@@ -467,6 +520,156 @@ static void amdgpu_command_submission_gfx_cp_copy_data(void)
467 amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX); 520 amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX);
468} 521}
469 522
523static void amdgpu_bo_eviction_test(void)
524{
525 const int sdma_write_length = 1024;
526 const int pm4_dw = 256;
527 amdgpu_context_handle context_handle;
528 amdgpu_bo_handle bo1, bo2, vram_max[2], gtt_max[2];
529 amdgpu_bo_handle *resources;
530 uint32_t *pm4;
531 struct amdgpu_cs_ib_info *ib_info;
532 struct amdgpu_cs_request *ibs_request;
533 uint64_t bo1_mc, bo2_mc;
534 volatile unsigned char *bo1_cpu, *bo2_cpu;
535 int i, j, r, loop1, loop2;
536 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
537 amdgpu_va_handle bo1_va_handle, bo2_va_handle;
538 struct amdgpu_heap_info vram_info, gtt_info;
539
540 pm4 = calloc(pm4_dw, sizeof(*pm4));
541 CU_ASSERT_NOT_EQUAL(pm4, NULL);
542
543 ib_info = calloc(1, sizeof(*ib_info));
544 CU_ASSERT_NOT_EQUAL(ib_info, NULL);
545
546 ibs_request = calloc(1, sizeof(*ibs_request));
547 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
548
549 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
550 CU_ASSERT_EQUAL(r, 0);
551
552 /* prepare resource */
553 resources = calloc(4, sizeof(amdgpu_bo_handle));
554 CU_ASSERT_NOT_EQUAL(resources, NULL);
555
556 r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM,
557 0, &vram_info);
558 CU_ASSERT_EQUAL(r, 0);
559
560 r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096,
561 AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]);
562 CU_ASSERT_EQUAL(r, 0);
563 r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096,
564 AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]);
565 CU_ASSERT_EQUAL(r, 0);
566
567 r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT,
568 0, &gtt_info);
569 CU_ASSERT_EQUAL(r, 0);
570
571 r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096,
572 AMDGPU_GEM_DOMAIN_GTT, 0, &gtt_max[0]);
573 CU_ASSERT_EQUAL(r, 0);
574 r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096,
575 AMDGPU_GEM_DOMAIN_GTT, 0, &gtt_max[1]);
576 CU_ASSERT_EQUAL(r, 0);
577
578
579
580 loop1 = loop2 = 0;
581 /* run 9 circle to test all mapping combination */
582 while(loop1 < 2) {
583 while(loop2 < 2) {
584 /* allocate UC bo1for sDMA use */
585 r = amdgpu_bo_alloc_and_map(device_handle,
586 sdma_write_length, 4096,
587 AMDGPU_GEM_DOMAIN_GTT,
588 gtt_flags[loop1], &bo1,
589 (void**)&bo1_cpu, &bo1_mc,
590 &bo1_va_handle);
591 CU_ASSERT_EQUAL(r, 0);
592
593 /* set bo1 */
594 memset((void*)bo1_cpu, 0xaa, sdma_write_length);
595
596 /* allocate UC bo2 for sDMA use */
597 r = amdgpu_bo_alloc_and_map(device_handle,
598 sdma_write_length, 4096,
599 AMDGPU_GEM_DOMAIN_GTT,
600 gtt_flags[loop2], &bo2,
601 (void**)&bo2_cpu, &bo2_mc,
602 &bo2_va_handle);
603 CU_ASSERT_EQUAL(r, 0);
604
605 /* clear bo2 */
606 memset((void*)bo2_cpu, 0, sdma_write_length);
607
608 resources[0] = bo1;
609 resources[1] = bo2;
610 resources[2] = vram_max[loop2];
611 resources[3] = gtt_max[loop2];
612
613 /* fulfill PM4: test DMA copy linear */
614 i = j = 0;
615 if (family_id == AMDGPU_FAMILY_SI) {
616 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0,
617 sdma_write_length);
618 pm4[i++] = 0xffffffff & bo2_mc;
619 pm4[i++] = 0xffffffff & bo1_mc;
620 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
621 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
622 } else {
623 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
624 if (family_id >= AMDGPU_FAMILY_AI)
625 pm4[i++] = sdma_write_length - 1;
626 else
627 pm4[i++] = sdma_write_length;
628 pm4[i++] = 0;
629 pm4[i++] = 0xffffffff & bo1_mc;
630 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
631 pm4[i++] = 0xffffffff & bo2_mc;
632 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
633 }
634
635 amdgpu_test_exec_cs_helper(context_handle,
636 AMDGPU_HW_IP_DMA, 0,
637 i, pm4,
638 4, resources,
639 ib_info, ibs_request);
640
641 /* verify if SDMA test result meets with expected */
642 i = 0;
643 while(i < sdma_write_length) {
644 CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa);
645 }
646 r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc,
647 sdma_write_length);
648 CU_ASSERT_EQUAL(r, 0);
649 r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
650 sdma_write_length);
651 CU_ASSERT_EQUAL(r, 0);
652 loop2++;
653 }
654 loop2 = 0;
655 loop1++;
656 }
657 amdgpu_bo_free(vram_max[0]);
658 amdgpu_bo_free(vram_max[1]);
659 amdgpu_bo_free(gtt_max[0]);
660 amdgpu_bo_free(gtt_max[1]);
661 /* clean resources */
662 free(resources);
663 free(ibs_request);
664 free(ib_info);
665 free(pm4);
666
667 /* end of test */
668 r = amdgpu_cs_ctx_free(context_handle);
669 CU_ASSERT_EQUAL(r, 0);
670}
671
672
470static void amdgpu_command_submission_gfx(void) 673static void amdgpu_command_submission_gfx(void)
471{ 674{
472 /* write data using the CP */ 675 /* write data using the CP */
@@ -493,10 +696,19 @@ static void amdgpu_semaphore_test(void)
493 struct amdgpu_cs_fence fence_status = {0}; 696 struct amdgpu_cs_fence fence_status = {0};
494 uint32_t *ptr; 697 uint32_t *ptr;
495 uint32_t expired; 698 uint32_t expired;
699 uint32_t sdma_nop, gfx_nop;
496 amdgpu_bo_list_handle bo_list[2]; 700 amdgpu_bo_list_handle bo_list[2];
497 amdgpu_va_handle va_handle[2]; 701 amdgpu_va_handle va_handle[2];
498 int r, i; 702 int r, i;
499 703
704 if (family_id == AMDGPU_FAMILY_SI) {
705 sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0);
706 gfx_nop = GFX_COMPUTE_NOP_SI;
707 } else {
708 sdma_nop = SDMA_PKT_HEADER_OP(SDMA_NOP);
709 gfx_nop = GFX_COMPUTE_NOP;
710 }
711
500 r = amdgpu_cs_create_semaphore(&sem); 712 r = amdgpu_cs_create_semaphore(&sem);
501 CU_ASSERT_EQUAL(r, 0); 713 CU_ASSERT_EQUAL(r, 0);
502 for (i = 0; i < 2; i++) { 714 for (i = 0; i < 2; i++) {
@@ -516,7 +728,7 @@ static void amdgpu_semaphore_test(void)
516 728
517 /* 1. same context different engine */ 729 /* 1. same context different engine */
518 ptr = ib_result_cpu[0]; 730 ptr = ib_result_cpu[0];
519 ptr[0] = SDMA_NOP; 731 ptr[0] = sdma_nop;
520 ib_info[0].ib_mc_address = ib_result_mc_address[0]; 732 ib_info[0].ib_mc_address = ib_result_mc_address[0];
521 ib_info[0].size = 1; 733 ib_info[0].size = 1;
522 734
@@ -533,7 +745,7 @@ static void amdgpu_semaphore_test(void)
533 r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); 745 r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem);
534 CU_ASSERT_EQUAL(r, 0); 746 CU_ASSERT_EQUAL(r, 0);
535 ptr = ib_result_cpu[1]; 747 ptr = ib_result_cpu[1];
536 ptr[0] = GFX_COMPUTE_NOP; 748 ptr[0] = gfx_nop;
537 ib_info[1].ib_mc_address = ib_result_mc_address[1]; 749 ib_info[1].ib_mc_address = ib_result_mc_address[1];
538 ib_info[1].size = 1; 750 ib_info[1].size = 1;
539 751
@@ -557,7 +769,7 @@ static void amdgpu_semaphore_test(void)
557 769
558 /* 2. same engine different context */ 770 /* 2. same engine different context */
559 ptr = ib_result_cpu[0]; 771 ptr = ib_result_cpu[0];
560 ptr[0] = GFX_COMPUTE_NOP; 772 ptr[0] = gfx_nop;
561 ib_info[0].ib_mc_address = ib_result_mc_address[0]; 773 ib_info[0].ib_mc_address = ib_result_mc_address[0];
562 ib_info[0].size = 1; 774 ib_info[0].size = 1;
563 775
@@ -574,7 +786,7 @@ static void amdgpu_semaphore_test(void)
574 r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); 786 r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem);
575 CU_ASSERT_EQUAL(r, 0); 787 CU_ASSERT_EQUAL(r, 0);
576 ptr = ib_result_cpu[1]; 788 ptr = ib_result_cpu[1];
577 ptr[0] = GFX_COMPUTE_NOP; 789 ptr[0] = gfx_nop;
578 ib_info[1].ib_mc_address = ib_result_mc_address[1]; 790 ib_info[1].ib_mc_address = ib_result_mc_address[1];
579 ib_info[1].size = 1; 791 ib_info[1].size = 1;
580 792
@@ -595,6 +807,7 @@ static void amdgpu_semaphore_test(void)
595 500000000, 0, &expired); 807 500000000, 0, &expired);
596 CU_ASSERT_EQUAL(r, 0); 808 CU_ASSERT_EQUAL(r, 0);
597 CU_ASSERT_EQUAL(expired, true); 809 CU_ASSERT_EQUAL(expired, true);
810
598 for (i = 0; i < 2; i++) { 811 for (i = 0; i < 2; i++) {
599 r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], 812 r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i],
600 ib_result_mc_address[i], 4096); 813 ib_result_mc_address[i], 4096);
@@ -622,14 +835,18 @@ static void amdgpu_command_submission_compute_nop(void)
622 struct amdgpu_cs_fence fence_status; 835 struct amdgpu_cs_fence fence_status;
623 uint32_t *ptr; 836 uint32_t *ptr;
624 uint32_t expired; 837 uint32_t expired;
625 int i, r, instance; 838 int r, instance;
626 amdgpu_bo_list_handle bo_list; 839 amdgpu_bo_list_handle bo_list;
627 amdgpu_va_handle va_handle; 840 amdgpu_va_handle va_handle;
841 struct drm_amdgpu_info_hw_ip info;
842
843 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
844 CU_ASSERT_EQUAL(r, 0);
628 845
629 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 846 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
630 CU_ASSERT_EQUAL(r, 0); 847 CU_ASSERT_EQUAL(r, 0);
631 848
632 for (instance = 0; instance < 8; instance++) { 849 for (instance = 0; (1 << instance) & info.available_rings; instance++) {
633 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, 850 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
634 AMDGPU_GEM_DOMAIN_GTT, 0, 851 AMDGPU_GEM_DOMAIN_GTT, 0,
635 &ib_result_handle, &ib_result_cpu, 852 &ib_result_handle, &ib_result_cpu,
@@ -641,8 +858,8 @@ static void amdgpu_command_submission_compute_nop(void)
641 CU_ASSERT_EQUAL(r, 0); 858 CU_ASSERT_EQUAL(r, 0);
642 859
643 ptr = ib_result_cpu; 860 ptr = ib_result_cpu;
644 for (i = 0; i < 16; ++i) 861 memset(ptr, 0, 16);
645 ptr[i] = 0xffff1000; 862 ptr[0]=PACKET3(PACKET3_NOP, 14);
646 863
647 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 864 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
648 ib_info.ib_mc_address = ib_result_mc_address; 865 ib_info.ib_mc_address = ib_result_mc_address;
@@ -805,9 +1022,10 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
805 struct amdgpu_cs_request *ibs_request; 1022 struct amdgpu_cs_request *ibs_request;
806 uint64_t bo_mc; 1023 uint64_t bo_mc;
807 volatile uint32_t *bo_cpu; 1024 volatile uint32_t *bo_cpu;
808 int i, j, r, loop; 1025 int i, j, r, loop, ring_id;
809 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; 1026 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
810 amdgpu_va_handle va_handle; 1027 amdgpu_va_handle va_handle;
1028 struct drm_amdgpu_info_hw_ip hw_ip_info;
811 1029
812 pm4 = calloc(pm4_dw, sizeof(*pm4)); 1030 pm4 = calloc(pm4_dw, sizeof(*pm4));
813 CU_ASSERT_NOT_EQUAL(pm4, NULL); 1031 CU_ASSERT_NOT_EQUAL(pm4, NULL);
@@ -818,6 +1036,9 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
818 ibs_request = calloc(1, sizeof(*ibs_request)); 1036 ibs_request = calloc(1, sizeof(*ibs_request));
819 CU_ASSERT_NOT_EQUAL(ibs_request, NULL); 1037 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
820 1038
1039 r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info);
1040 CU_ASSERT_EQUAL(r, 0);
1041
821 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 1042 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
822 CU_ASSERT_EQUAL(r, 0); 1043 CU_ASSERT_EQUAL(r, 0);
823 1044
@@ -825,58 +1046,66 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
825 resources = calloc(1, sizeof(amdgpu_bo_handle)); 1046 resources = calloc(1, sizeof(amdgpu_bo_handle));
826 CU_ASSERT_NOT_EQUAL(resources, NULL); 1047 CU_ASSERT_NOT_EQUAL(resources, NULL);
827 1048
828 loop = 0; 1049 for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) {
829 while(loop < 2) { 1050 loop = 0;
830 /* allocate UC bo for sDMA use */ 1051 while(loop < 2) {
831 r = amdgpu_bo_alloc_and_map(device_handle, 1052 /* allocate UC bo for sDMA use */
832 sdma_write_length * sizeof(uint32_t), 1053 r = amdgpu_bo_alloc_and_map(device_handle,
833 4096, AMDGPU_GEM_DOMAIN_GTT, 1054 sdma_write_length * sizeof(uint32_t),
834 gtt_flags[loop], &bo, (void**)&bo_cpu, 1055 4096, AMDGPU_GEM_DOMAIN_GTT,
835 &bo_mc, &va_handle); 1056 gtt_flags[loop], &bo, (void**)&bo_cpu,
836 CU_ASSERT_EQUAL(r, 0); 1057 &bo_mc, &va_handle);
1058 CU_ASSERT_EQUAL(r, 0);
837 1059
838 /* clear bo */ 1060 /* clear bo */
839 memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); 1061 memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t));
840
841
842 resources[0] = bo;
843
844 /* fulfill PM4: test DMA write-linear */
845 i = j = 0;
846 if (ip_type == AMDGPU_HW_IP_DMA) {
847 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
848 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
849 pm4[i++] = 0xffffffff & bo_mc;
850 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
851 pm4[i++] = sdma_write_length;
852 while(j++ < sdma_write_length)
853 pm4[i++] = 0xdeadbeaf;
854 } else if ((ip_type == AMDGPU_HW_IP_GFX) ||
855 (ip_type == AMDGPU_HW_IP_COMPUTE)) {
856 pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length);
857 pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
858 pm4[i++] = 0xfffffffc & bo_mc;
859 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
860 while(j++ < sdma_write_length)
861 pm4[i++] = 0xdeadbeaf;
862 }
863 1062
864 amdgpu_test_exec_cs_helper(context_handle, 1063 resources[0] = bo;
865 ip_type, 0,
866 i, pm4,
867 1, resources,
868 ib_info, ibs_request);
869 1064
870 /* verify if SDMA test result meets with expected */ 1065 /* fulfill PM4: test DMA write-linear */
871 i = 0; 1066 i = j = 0;
872 while(i < sdma_write_length) { 1067 if (ip_type == AMDGPU_HW_IP_DMA) {
873 CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); 1068 if (family_id == AMDGPU_FAMILY_SI)
874 } 1069 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0,
1070 sdma_write_length);
1071 else
1072 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
1073 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
1074 pm4[i++] = 0xffffffff & bo_mc;
1075 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1076 if (family_id >= AMDGPU_FAMILY_AI)
1077 pm4[i++] = sdma_write_length - 1;
1078 else if (family_id != AMDGPU_FAMILY_SI)
1079 pm4[i++] = sdma_write_length;
1080 while(j++ < sdma_write_length)
1081 pm4[i++] = 0xdeadbeaf;
1082 } else if ((ip_type == AMDGPU_HW_IP_GFX) ||
1083 (ip_type == AMDGPU_HW_IP_COMPUTE)) {
1084 pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length);
1085 pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
1086 pm4[i++] = 0xfffffffc & bo_mc;
1087 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1088 while(j++ < sdma_write_length)
1089 pm4[i++] = 0xdeadbeaf;
1090 }
875 1091
876 r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, 1092 amdgpu_test_exec_cs_helper(context_handle,
877 sdma_write_length * sizeof(uint32_t)); 1093 ip_type, ring_id,
878 CU_ASSERT_EQUAL(r, 0); 1094 i, pm4,
879 loop++; 1095 1, resources,
1096 ib_info, ibs_request);
1097
1098 /* verify if SDMA test result meets with expected */
1099 i = 0;
1100 while(i < sdma_write_length) {
1101 CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
1102 }
1103
1104 r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc,
1105 sdma_write_length * sizeof(uint32_t));
1106 CU_ASSERT_EQUAL(r, 0);
1107 loop++;
1108 }
880 } 1109 }
881 /* clean resources */ 1110 /* clean resources */
882 free(resources); 1111 free(resources);
@@ -906,9 +1135,10 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
906 struct amdgpu_cs_request *ibs_request; 1135 struct amdgpu_cs_request *ibs_request;
907 uint64_t bo_mc; 1136 uint64_t bo_mc;
908 volatile uint32_t *bo_cpu; 1137 volatile uint32_t *bo_cpu;
909 int i, j, r, loop; 1138 int i, j, r, loop, ring_id;
910 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; 1139 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
911 amdgpu_va_handle va_handle; 1140 amdgpu_va_handle va_handle;
1141 struct drm_amdgpu_info_hw_ip hw_ip_info;
912 1142
913 pm4 = calloc(pm4_dw, sizeof(*pm4)); 1143 pm4 = calloc(pm4_dw, sizeof(*pm4));
914 CU_ASSERT_NOT_EQUAL(pm4, NULL); 1144 CU_ASSERT_NOT_EQUAL(pm4, NULL);
@@ -919,6 +1149,9 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
919 ibs_request = calloc(1, sizeof(*ibs_request)); 1149 ibs_request = calloc(1, sizeof(*ibs_request));
920 CU_ASSERT_NOT_EQUAL(ibs_request, NULL); 1150 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
921 1151
1152 r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info);
1153 CU_ASSERT_EQUAL(r, 0);
1154
922 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 1155 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
923 CU_ASSERT_EQUAL(r, 0); 1156 CU_ASSERT_EQUAL(r, 0);
924 1157
@@ -926,60 +1159,86 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
926 resources = calloc(1, sizeof(amdgpu_bo_handle)); 1159 resources = calloc(1, sizeof(amdgpu_bo_handle));
927 CU_ASSERT_NOT_EQUAL(resources, NULL); 1160 CU_ASSERT_NOT_EQUAL(resources, NULL);
928 1161
929 loop = 0; 1162 for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) {
930 while(loop < 2) { 1163 loop = 0;
931 /* allocate UC bo for sDMA use */ 1164 while(loop < 2) {
932 r = amdgpu_bo_alloc_and_map(device_handle, 1165 /* allocate UC bo for sDMA use */
933 sdma_write_length, 4096, 1166 r = amdgpu_bo_alloc_and_map(device_handle,
934 AMDGPU_GEM_DOMAIN_GTT, 1167 sdma_write_length, 4096,
935 gtt_flags[loop], &bo, (void**)&bo_cpu, 1168 AMDGPU_GEM_DOMAIN_GTT,
936 &bo_mc, &va_handle); 1169 gtt_flags[loop], &bo, (void**)&bo_cpu,
937 CU_ASSERT_EQUAL(r, 0); 1170 &bo_mc, &va_handle);
1171 CU_ASSERT_EQUAL(r, 0);
938 1172
939 /* clear bo */ 1173 /* clear bo */
940 memset((void*)bo_cpu, 0, sdma_write_length); 1174 memset((void*)bo_cpu, 0, sdma_write_length);
941
942 resources[0] = bo;
943
944 /* fulfill PM4: test DMA const fill */
945 i = j = 0;
946 if (ip_type == AMDGPU_HW_IP_DMA) {
947 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
948 SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
949 pm4[i++] = 0xffffffff & bo_mc;
950 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
951 pm4[i++] = 0xdeadbeaf;
952 pm4[i++] = sdma_write_length;
953 } else if ((ip_type == AMDGPU_HW_IP_GFX) ||
954 (ip_type == AMDGPU_HW_IP_COMPUTE)) {
955 pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
956 pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
957 PACKET3_DMA_DATA_DST_SEL(0) |
958 PACKET3_DMA_DATA_SRC_SEL(2) |
959 PACKET3_DMA_DATA_CP_SYNC;
960 pm4[i++] = 0xdeadbeaf;
961 pm4[i++] = 0;
962 pm4[i++] = 0xfffffffc & bo_mc;
963 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
964 pm4[i++] = sdma_write_length;
965 }
966 1175
967 amdgpu_test_exec_cs_helper(context_handle, 1176 resources[0] = bo;
968 ip_type, 0,
969 i, pm4,
970 1, resources,
971 ib_info, ibs_request);
972 1177
973 /* verify if SDMA test result meets with expected */ 1178 /* fulfill PM4: test DMA const fill */
974 i = 0; 1179 i = j = 0;
975 while(i < (sdma_write_length / 4)) { 1180 if (ip_type == AMDGPU_HW_IP_DMA) {
976 CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); 1181 if (family_id == AMDGPU_FAMILY_SI) {
977 } 1182 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI,
1183 0, 0, 0,
1184 sdma_write_length / 4);
1185 pm4[i++] = 0xfffffffc & bo_mc;
1186 pm4[i++] = 0xdeadbeaf;
1187 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16;
1188 } else {
1189 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
1190 SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
1191 pm4[i++] = 0xffffffff & bo_mc;
1192 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1193 pm4[i++] = 0xdeadbeaf;
1194 if (family_id >= AMDGPU_FAMILY_AI)
1195 pm4[i++] = sdma_write_length - 1;
1196 else
1197 pm4[i++] = sdma_write_length;
1198 }
1199 } else if ((ip_type == AMDGPU_HW_IP_GFX) ||
1200 (ip_type == AMDGPU_HW_IP_COMPUTE)) {
1201 if (family_id == AMDGPU_FAMILY_SI) {
1202 pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4);
1203 pm4[i++] = 0xdeadbeaf;
1204 pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) |
1205 PACKET3_DMA_DATA_SI_DST_SEL(0) |
1206 PACKET3_DMA_DATA_SI_SRC_SEL(2) |
1207 PACKET3_DMA_DATA_SI_CP_SYNC;
1208 pm4[i++] = 0xffffffff & bo_mc;
1209 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1210 pm4[i++] = sdma_write_length;
1211 } else {
1212 pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
1213 pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
1214 PACKET3_DMA_DATA_DST_SEL(0) |
1215 PACKET3_DMA_DATA_SRC_SEL(2) |
1216 PACKET3_DMA_DATA_CP_SYNC;
1217 pm4[i++] = 0xdeadbeaf;
1218 pm4[i++] = 0;
1219 pm4[i++] = 0xfffffffc & bo_mc;
1220 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1221 pm4[i++] = sdma_write_length;
1222 }
1223 }
978 1224
979 r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, 1225 amdgpu_test_exec_cs_helper(context_handle,
980 sdma_write_length); 1226 ip_type, ring_id,
981 CU_ASSERT_EQUAL(r, 0); 1227 i, pm4,
982 loop++; 1228 1, resources,
1229 ib_info, ibs_request);
1230
1231 /* verify if SDMA test result meets with expected */
1232 i = 0;
1233 while(i < (sdma_write_length / 4)) {
1234 CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
1235 }
1236
1237 r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc,
1238 sdma_write_length);
1239 CU_ASSERT_EQUAL(r, 0);
1240 loop++;
1241 }
983 } 1242 }
984 /* clean resources */ 1243 /* clean resources */
985 free(resources); 1244 free(resources);
@@ -1009,9 +1268,10 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
1009 struct amdgpu_cs_request *ibs_request; 1268 struct amdgpu_cs_request *ibs_request;
1010 uint64_t bo1_mc, bo2_mc; 1269 uint64_t bo1_mc, bo2_mc;
1011 volatile unsigned char *bo1_cpu, *bo2_cpu; 1270 volatile unsigned char *bo1_cpu, *bo2_cpu;
1012 int i, j, r, loop1, loop2; 1271 int i, j, r, loop1, loop2, ring_id;
1013 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; 1272 uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
1014 amdgpu_va_handle bo1_va_handle, bo2_va_handle; 1273 amdgpu_va_handle bo1_va_handle, bo2_va_handle;
1274 struct drm_amdgpu_info_hw_ip hw_ip_info;
1015 1275
1016 pm4 = calloc(pm4_dw, sizeof(*pm4)); 1276 pm4 = calloc(pm4_dw, sizeof(*pm4));
1017 CU_ASSERT_NOT_EQUAL(pm4, NULL); 1277 CU_ASSERT_NOT_EQUAL(pm4, NULL);
@@ -1022,6 +1282,9 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
1022 ibs_request = calloc(1, sizeof(*ibs_request)); 1282 ibs_request = calloc(1, sizeof(*ibs_request));
1023 CU_ASSERT_NOT_EQUAL(ibs_request, NULL); 1283 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1024 1284
1285 r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info);
1286 CU_ASSERT_EQUAL(r, 0);
1287
1025 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 1288 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
1026 CU_ASSERT_EQUAL(r, 0); 1289 CU_ASSERT_EQUAL(r, 0);
1027 1290
@@ -1029,81 +1292,111 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
1029 resources = calloc(2, sizeof(amdgpu_bo_handle)); 1292 resources = calloc(2, sizeof(amdgpu_bo_handle));
1030 CU_ASSERT_NOT_EQUAL(resources, NULL); 1293 CU_ASSERT_NOT_EQUAL(resources, NULL);
1031 1294
1032 loop1 = loop2 = 0; 1295 for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) {
1033 /* run 9 circle to test all mapping combination */ 1296 loop1 = loop2 = 0;
1034 while(loop1 < 2) { 1297 /* run 9 circle to test all mapping combination */
1035 while(loop2 < 2) { 1298 while(loop1 < 2) {
1036 /* allocate UC bo1for sDMA use */ 1299 while(loop2 < 2) {
1037 r = amdgpu_bo_alloc_and_map(device_handle, 1300 /* allocate UC bo1for sDMA use */
1038 sdma_write_length, 4096, 1301 r = amdgpu_bo_alloc_and_map(device_handle,
1039 AMDGPU_GEM_DOMAIN_GTT, 1302 sdma_write_length, 4096,
1040 gtt_flags[loop1], &bo1, 1303 AMDGPU_GEM_DOMAIN_GTT,
1041 (void**)&bo1_cpu, &bo1_mc, 1304 gtt_flags[loop1], &bo1,
1042 &bo1_va_handle); 1305 (void**)&bo1_cpu, &bo1_mc,
1043 CU_ASSERT_EQUAL(r, 0); 1306 &bo1_va_handle);
1044 1307 CU_ASSERT_EQUAL(r, 0);
1045 /* set bo1 */ 1308
1046 memset((void*)bo1_cpu, 0xaa, sdma_write_length); 1309 /* set bo1 */
1047 1310 memset((void*)bo1_cpu, 0xaa, sdma_write_length);
1048 /* allocate UC bo2 for sDMA use */ 1311
1049 r = amdgpu_bo_alloc_and_map(device_handle, 1312 /* allocate UC bo2 for sDMA use */
1050 sdma_write_length, 4096, 1313 r = amdgpu_bo_alloc_and_map(device_handle,
1051 AMDGPU_GEM_DOMAIN_GTT, 1314 sdma_write_length, 4096,
1052 gtt_flags[loop2], &bo2, 1315 AMDGPU_GEM_DOMAIN_GTT,
1053 (void**)&bo2_cpu, &bo2_mc, 1316 gtt_flags[loop2], &bo2,
1054 &bo2_va_handle); 1317 (void**)&bo2_cpu, &bo2_mc,
1055 CU_ASSERT_EQUAL(r, 0); 1318 &bo2_va_handle);
1056 1319 CU_ASSERT_EQUAL(r, 0);
1057 /* clear bo2 */ 1320
1058 memset((void*)bo2_cpu, 0, sdma_write_length); 1321 /* clear bo2 */
1059 1322 memset((void*)bo2_cpu, 0, sdma_write_length);
1060 resources[0] = bo1; 1323
1061 resources[1] = bo2; 1324 resources[0] = bo1;
1062 1325 resources[1] = bo2;
1063 /* fulfill PM4: test DMA copy linear */ 1326
1064 i = j = 0; 1327 /* fulfill PM4: test DMA copy linear */
1065 if (ip_type == AMDGPU_HW_IP_DMA) { 1328 i = j = 0;
1066 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); 1329 if (ip_type == AMDGPU_HW_IP_DMA) {
1067 pm4[i++] = sdma_write_length; 1330 if (family_id == AMDGPU_FAMILY_SI) {
1068 pm4[i++] = 0; 1331 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI,
1069 pm4[i++] = 0xffffffff & bo1_mc; 1332 0, 0, 0,
1070 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; 1333 sdma_write_length);
1071 pm4[i++] = 0xffffffff & bo2_mc; 1334 pm4[i++] = 0xffffffff & bo2_mc;
1072 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; 1335 pm4[i++] = 0xffffffff & bo1_mc;
1073 } else if ((ip_type == AMDGPU_HW_IP_GFX) || 1336 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
1074 (ip_type == AMDGPU_HW_IP_COMPUTE)) { 1337 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
1075 pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); 1338 } else {
1076 pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | 1339 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY,
1077 PACKET3_DMA_DATA_DST_SEL(0) | 1340 SDMA_COPY_SUB_OPCODE_LINEAR,
1078 PACKET3_DMA_DATA_SRC_SEL(0) | 1341 0);
1079 PACKET3_DMA_DATA_CP_SYNC; 1342 if (family_id >= AMDGPU_FAMILY_AI)
1080 pm4[i++] = 0xfffffffc & bo1_mc; 1343 pm4[i++] = sdma_write_length - 1;
1081 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; 1344 else
1082 pm4[i++] = 0xfffffffc & bo2_mc; 1345 pm4[i++] = sdma_write_length;
1083 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; 1346 pm4[i++] = 0;
1084 pm4[i++] = sdma_write_length; 1347 pm4[i++] = 0xffffffff & bo1_mc;
1085 } 1348 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
1086 1349 pm4[i++] = 0xffffffff & bo2_mc;
1087 amdgpu_test_exec_cs_helper(context_handle, 1350 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
1088 ip_type, 0, 1351 }
1089 i, pm4, 1352 } else if ((ip_type == AMDGPU_HW_IP_GFX) ||
1090 2, resources, 1353 (ip_type == AMDGPU_HW_IP_COMPUTE)) {
1091 ib_info, ibs_request); 1354 if (family_id == AMDGPU_FAMILY_SI) {
1092 1355 pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4);
1093 /* verify if SDMA test result meets with expected */ 1356 pm4[i++] = 0xfffffffc & bo1_mc;
1094 i = 0; 1357 pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) |
1095 while(i < sdma_write_length) { 1358 PACKET3_DMA_DATA_SI_DST_SEL(0) |
1096 CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); 1359 PACKET3_DMA_DATA_SI_SRC_SEL(0) |
1360 PACKET3_DMA_DATA_SI_CP_SYNC |
1361 (0xffff00000000 & bo1_mc) >> 32;
1362 pm4[i++] = 0xfffffffc & bo2_mc;
1363 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
1364 pm4[i++] = sdma_write_length;
1365 } else {
1366 pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
1367 pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
1368 PACKET3_DMA_DATA_DST_SEL(0) |
1369 PACKET3_DMA_DATA_SRC_SEL(0) |
1370 PACKET3_DMA_DATA_CP_SYNC;
1371 pm4[i++] = 0xfffffffc & bo1_mc;
1372 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
1373 pm4[i++] = 0xfffffffc & bo2_mc;
1374 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
1375 pm4[i++] = sdma_write_length;
1376 }
1377 }
1378
1379 amdgpu_test_exec_cs_helper(context_handle,
1380 ip_type, ring_id,
1381 i, pm4,
1382 2, resources,
1383 ib_info, ibs_request);
1384
1385 /* verify if SDMA test result meets with expected */
1386 i = 0;
1387 while(i < sdma_write_length) {
1388 CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa);
1389 }
1390 r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc,
1391 sdma_write_length);
1392 CU_ASSERT_EQUAL(r, 0);
1393 r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
1394 sdma_write_length);
1395 CU_ASSERT_EQUAL(r, 0);
1396 loop2++;
1097 } 1397 }
1098 r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, 1398 loop1++;
1099 sdma_write_length);
1100 CU_ASSERT_EQUAL(r, 0);
1101 r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
1102 sdma_write_length);
1103 CU_ASSERT_EQUAL(r, 0);
1104 loop2++;
1105 } 1399 }
1106 loop1++;
1107 } 1400 }
1108 /* clean resources */ 1401 /* clean resources */
1109 free(resources); 1402 free(resources);
@@ -1128,6 +1421,106 @@ static void amdgpu_command_submission_sdma(void)
1128 amdgpu_command_submission_sdma_copy_linear(); 1421 amdgpu_command_submission_sdma_copy_linear();
1129} 1422}
1130 1423
1424static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all)
1425{
1426 amdgpu_context_handle context_handle;
1427 amdgpu_bo_handle ib_result_handle, ib_result_ce_handle;
1428 void *ib_result_cpu, *ib_result_ce_cpu;
1429 uint64_t ib_result_mc_address, ib_result_ce_mc_address;
1430 struct amdgpu_cs_request ibs_request[2] = {0};
1431 struct amdgpu_cs_ib_info ib_info[2];
1432 struct amdgpu_cs_fence fence_status[2] = {0};
1433 uint32_t *ptr;
1434 uint32_t expired;
1435 amdgpu_bo_list_handle bo_list;
1436 amdgpu_va_handle va_handle, va_handle_ce;
1437 int r;
1438 int i = 0, ib_cs_num = 2;
1439
1440 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
1441 CU_ASSERT_EQUAL(r, 0);
1442
1443 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
1444 AMDGPU_GEM_DOMAIN_GTT, 0,
1445 &ib_result_handle, &ib_result_cpu,
1446 &ib_result_mc_address, &va_handle);
1447 CU_ASSERT_EQUAL(r, 0);
1448
1449 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
1450 AMDGPU_GEM_DOMAIN_GTT, 0,
1451 &ib_result_ce_handle, &ib_result_ce_cpu,
1452 &ib_result_ce_mc_address, &va_handle_ce);
1453 CU_ASSERT_EQUAL(r, 0);
1454
1455 r = amdgpu_get_bo_list(device_handle, ib_result_handle,
1456 ib_result_ce_handle, &bo_list);
1457 CU_ASSERT_EQUAL(r, 0);
1458
1459 memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info));
1460
1461 /* IT_SET_CE_DE_COUNTERS */
1462 ptr = ib_result_ce_cpu;
1463 if (family_id != AMDGPU_FAMILY_SI) {
1464 ptr[i++] = 0xc0008900;
1465 ptr[i++] = 0;
1466 }
1467 ptr[i++] = 0xc0008400;
1468 ptr[i++] = 1;
1469 ib_info[0].ib_mc_address = ib_result_ce_mc_address;
1470 ib_info[0].size = i;
1471 ib_info[0].flags = AMDGPU_IB_FLAG_CE;
1472
1473 /* IT_WAIT_ON_CE_COUNTER */
1474 ptr = ib_result_cpu;
1475 ptr[0] = 0xc0008600;
1476 ptr[1] = 0x00000001;
1477 ib_info[1].ib_mc_address = ib_result_mc_address;
1478 ib_info[1].size = 2;
1479
1480 for (i = 0; i < ib_cs_num; i++) {
1481 ibs_request[i].ip_type = AMDGPU_HW_IP_GFX;
1482 ibs_request[i].number_of_ibs = 2;
1483 ibs_request[i].ibs = ib_info;
1484 ibs_request[i].resources = bo_list;
1485 ibs_request[i].fence_info.handle = NULL;
1486 }
1487
1488 r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num);
1489
1490 CU_ASSERT_EQUAL(r, 0);
1491
1492 for (i = 0; i < ib_cs_num; i++) {
1493 fence_status[i].context = context_handle;
1494 fence_status[i].ip_type = AMDGPU_HW_IP_GFX;
1495 fence_status[i].fence = ibs_request[i].seq_no;
1496 }
1497
1498 r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all,
1499 AMDGPU_TIMEOUT_INFINITE,
1500 &expired, NULL);
1501 CU_ASSERT_EQUAL(r, 0);
1502
1503 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
1504 ib_result_mc_address, 4096);
1505 CU_ASSERT_EQUAL(r, 0);
1506
1507 r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce,
1508 ib_result_ce_mc_address, 4096);
1509 CU_ASSERT_EQUAL(r, 0);
1510
1511 r = amdgpu_bo_list_destroy(bo_list);
1512 CU_ASSERT_EQUAL(r, 0);
1513
1514 r = amdgpu_cs_ctx_free(context_handle);
1515 CU_ASSERT_EQUAL(r, 0);
1516}
1517
1518static void amdgpu_command_submission_multi_fence(void)
1519{
1520 amdgpu_command_submission_multi_fence_wait_all(true);
1521 amdgpu_command_submission_multi_fence_wait_all(false);
1522}
1523
1131static void amdgpu_userptr_test(void) 1524static void amdgpu_userptr_test(void)
1132{ 1525{
1133 int i, r, j; 1526 int i, r, j;
@@ -1175,15 +1568,28 @@ static void amdgpu_userptr_test(void)
1175 handle = buf_handle; 1568 handle = buf_handle;
1176 1569
1177 j = i = 0; 1570 j = i = 0;
1178 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 1571
1179 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 1572 if (family_id == AMDGPU_FAMILY_SI)
1573 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0,
1574 sdma_write_length);
1575 else
1576 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
1577 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
1180 pm4[i++] = 0xffffffff & bo_mc; 1578 pm4[i++] = 0xffffffff & bo_mc;
1181 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; 1579 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
1182 pm4[i++] = sdma_write_length; 1580 if (family_id >= AMDGPU_FAMILY_AI)
1581 pm4[i++] = sdma_write_length - 1;
1582 else if (family_id != AMDGPU_FAMILY_SI)
1583 pm4[i++] = sdma_write_length;
1183 1584
1184 while (j++ < sdma_write_length) 1585 while (j++ < sdma_write_length)
1185 pm4[i++] = 0xdeadbeaf; 1586 pm4[i++] = 0xdeadbeaf;
1186 1587
1588 if (!fork()) {
1589 pm4[0] = 0x0;
1590 exit(0);
1591 }
1592
1187 amdgpu_test_exec_cs_helper(context_handle, 1593 amdgpu_test_exec_cs_helper(context_handle,
1188 AMDGPU_HW_IP_DMA, 0, 1594 AMDGPU_HW_IP_DMA, 0,
1189 i, pm4, 1595 i, pm4,
@@ -1207,4 +1613,212 @@ static void amdgpu_userptr_test(void)
1207 1613
1208 r = amdgpu_cs_ctx_free(context_handle); 1614 r = amdgpu_cs_ctx_free(context_handle);
1209 CU_ASSERT_EQUAL(r, 0); 1615 CU_ASSERT_EQUAL(r, 0);
1616
1617 wait(NULL);
1618}
1619
1620static void amdgpu_sync_dependency_test(void)
1621{
1622 amdgpu_context_handle context_handle[2];
1623 amdgpu_bo_handle ib_result_handle;
1624 void *ib_result_cpu;
1625 uint64_t ib_result_mc_address;
1626 struct amdgpu_cs_request ibs_request;
1627 struct amdgpu_cs_ib_info ib_info;
1628 struct amdgpu_cs_fence fence_status;
1629 uint32_t expired;
1630 int i, j, r;
1631 amdgpu_bo_list_handle bo_list;
1632 amdgpu_va_handle va_handle;
1633 static uint32_t *ptr;
1634 uint64_t seq_no;
1635
1636 r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]);
1637 CU_ASSERT_EQUAL(r, 0);
1638 r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]);
1639 CU_ASSERT_EQUAL(r, 0);
1640
1641 r = amdgpu_bo_alloc_and_map(device_handle, 8192, 4096,
1642 AMDGPU_GEM_DOMAIN_GTT, 0,
1643 &ib_result_handle, &ib_result_cpu,
1644 &ib_result_mc_address, &va_handle);
1645 CU_ASSERT_EQUAL(r, 0);
1646
1647 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
1648 &bo_list);
1649 CU_ASSERT_EQUAL(r, 0);
1650
1651 ptr = ib_result_cpu;
1652 i = 0;
1653
1654 memcpy(ptr + CODE_OFFSET , shader_bin, sizeof(shader_bin));
1655
1656 /* Dispatch minimal init config and verify it's executed */
1657 ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
1658 ptr[i++] = 0x80000000;
1659 ptr[i++] = 0x80000000;
1660
1661 ptr[i++] = PACKET3(PKT3_CLEAR_STATE, 0);
1662 ptr[i++] = 0x80000000;
1663
1664
1665 /* Program compute regs */
1666 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
1667 ptr[i++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1668 ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 8;
1669 ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 40;
1670
1671
1672 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
1673 ptr[i++] = mmCOMPUTE_PGM_RSRC1 - PACKET3_SET_SH_REG_START;
1674 /*
1675 * 002c0040 COMPUTE_PGM_RSRC1 <- VGPRS = 0
1676 SGPRS = 1
1677 PRIORITY = 0
1678 FLOAT_MODE = 192 (0xc0)
1679 PRIV = 0
1680 DX10_CLAMP = 1
1681 DEBUG_MODE = 0
1682 IEEE_MODE = 0
1683 BULKY = 0
1684 CDBG_USER = 0
1685 *
1686 */
1687 ptr[i++] = 0x002c0040;
1688
1689
1690 /*
1691 * 00000010 COMPUTE_PGM_RSRC2 <- SCRATCH_EN = 0
1692 USER_SGPR = 8
1693 TRAP_PRESENT = 0
1694 TGID_X_EN = 0
1695 TGID_Y_EN = 0
1696 TGID_Z_EN = 0
1697 TG_SIZE_EN = 0
1698 TIDIG_COMP_CNT = 0
1699 EXCP_EN_MSB = 0
1700 LDS_SIZE = 0
1701 EXCP_EN = 0
1702 *
1703 */
1704 ptr[i++] = 0x00000010;
1705
1706
1707/*
1708 * 00000100 COMPUTE_TMPRING_SIZE <- WAVES = 256 (0x100)
1709 WAVESIZE = 0
1710 *
1711 */
1712 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
1713 ptr[i++] = mmCOMPUTE_TMPRING_SIZE - PACKET3_SET_SH_REG_START;
1714 ptr[i++] = 0x00000100;
1715
1716 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
1717 ptr[i++] = mmCOMPUTE_USER_DATA_0 - PACKET3_SET_SH_REG_START;
1718 ptr[i++] = 0xffffffff & (ib_result_mc_address + DATA_OFFSET * 4);
1719 ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
1720
1721 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
1722 ptr[i++] = mmCOMPUTE_RESOURCE_LIMITS - PACKET3_SET_SH_REG_START;
1723 ptr[i++] = 0;
1724
1725 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
1726 ptr[i++] = mmCOMPUTE_NUM_THREAD_X - PACKET3_SET_SH_REG_START;
1727 ptr[i++] = 1;
1728 ptr[i++] = 1;
1729 ptr[i++] = 1;
1730
1731
1732 /* Dispatch */
1733 ptr[i++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1734 ptr[i++] = 1;
1735 ptr[i++] = 1;
1736 ptr[i++] = 1;
1737 ptr[i++] = 0x00000045; /* DISPATCH DIRECT field */
1738
1739
1740 while (i & 7)
1741 ptr[i++] = 0xffff1000; /* type3 nop packet */
1742
1743 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
1744 ib_info.ib_mc_address = ib_result_mc_address;
1745 ib_info.size = i;
1746
1747 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
1748 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
1749 ibs_request.ring = 0;
1750 ibs_request.number_of_ibs = 1;
1751 ibs_request.ibs = &ib_info;
1752 ibs_request.resources = bo_list;
1753 ibs_request.fence_info.handle = NULL;
1754
1755 r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request, 1);
1756 CU_ASSERT_EQUAL(r, 0);
1757 seq_no = ibs_request.seq_no;
1758
1759
1760
1761 /* Prepare second command with dependency on the first */
1762 j = i;
1763 ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
1764 ptr[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
1765 ptr[i++] = 0xfffffffc & (ib_result_mc_address + DATA_OFFSET * 4);
1766 ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
1767 ptr[i++] = 99;
1768
1769 while (i & 7)
1770 ptr[i++] = 0xffff1000; /* type3 nop packet */
1771
1772 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
1773 ib_info.ib_mc_address = ib_result_mc_address + j * 4;
1774 ib_info.size = i - j;
1775
1776 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
1777 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
1778 ibs_request.ring = 0;
1779 ibs_request.number_of_ibs = 1;
1780 ibs_request.ibs = &ib_info;
1781 ibs_request.resources = bo_list;
1782 ibs_request.fence_info.handle = NULL;
1783
1784 ibs_request.number_of_dependencies = 1;
1785
1786 ibs_request.dependencies = calloc(1, sizeof(*ibs_request.dependencies));
1787 ibs_request.dependencies[0].context = context_handle[1];
1788 ibs_request.dependencies[0].ip_instance = 0;
1789 ibs_request.dependencies[0].ring = 0;
1790 ibs_request.dependencies[0].fence = seq_no;
1791
1792
1793 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request, 1);
1794 CU_ASSERT_EQUAL(r, 0);
1795
1796
1797 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
1798 fence_status.context = context_handle[0];
1799 fence_status.ip_type = AMDGPU_HW_IP_GFX;
1800 fence_status.ip_instance = 0;
1801 fence_status.ring = 0;
1802 fence_status.fence = ibs_request.seq_no;
1803
1804 r = amdgpu_cs_query_fence_status(&fence_status,
1805 AMDGPU_TIMEOUT_INFINITE,0, &expired);
1806 CU_ASSERT_EQUAL(r, 0);
1807
1808 /* Expect the second command to wait for shader to complete */
1809 CU_ASSERT_EQUAL(ptr[DATA_OFFSET], 99);
1810
1811 r = amdgpu_bo_list_destroy(bo_list);
1812 CU_ASSERT_EQUAL(r, 0);
1813
1814 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
1815 ib_result_mc_address, 4096);
1816 CU_ASSERT_EQUAL(r, 0);
1817
1818 r = amdgpu_cs_ctx_free(context_handle[0]);
1819 CU_ASSERT_EQUAL(r, 0);
1820 r = amdgpu_cs_ctx_free(context_handle[1]);
1821 CU_ASSERT_EQUAL(r, 0);
1822
1823 free(ibs_request.dependencies);
1210} 1824}
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 74b5e77b..9d4da4af 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -21,10 +21,6 @@
21 * 21 *
22*/ 22*/
23 23
24#ifdef HAVE_CONFIG_H
25#include "config.h"
26#endif
27
28#include <stdio.h> 24#include <stdio.h>
29 25
30#include "CUnit/Basic.h" 26#include "CUnit/Basic.h"
@@ -46,13 +42,15 @@ static amdgpu_va_handle va_handle;
46static void amdgpu_bo_export_import(void); 42static void amdgpu_bo_export_import(void);
47static void amdgpu_bo_metadata(void); 43static void amdgpu_bo_metadata(void);
48static void amdgpu_bo_map_unmap(void); 44static void amdgpu_bo_map_unmap(void);
45static void amdgpu_memory_alloc(void);
46static void amdgpu_mem_fail_alloc(void);
49 47
50CU_TestInfo bo_tests[] = { 48CU_TestInfo bo_tests[] = {
51 { "Export/Import", amdgpu_bo_export_import }, 49 { "Export/Import", amdgpu_bo_export_import },
52#if 0
53 { "Metadata", amdgpu_bo_metadata }, 50 { "Metadata", amdgpu_bo_metadata },
54#endif
55 { "CPU map/unmap", amdgpu_bo_map_unmap }, 51 { "CPU map/unmap", amdgpu_bo_map_unmap },
52 { "Memory alloc Test", amdgpu_memory_alloc },
53 { "Memory fail alloc Test", amdgpu_mem_fail_alloc },
56 CU_TEST_INFO_NULL, 54 CU_TEST_INFO_NULL,
57}; 55};
58 56
@@ -195,3 +193,72 @@ static void amdgpu_bo_map_unmap(void)
195 r = amdgpu_bo_cpu_unmap(buffer_handle); 193 r = amdgpu_bo_cpu_unmap(buffer_handle);
196 CU_ASSERT_EQUAL(r, 0); 194 CU_ASSERT_EQUAL(r, 0);
197} 195}
196
197static void amdgpu_memory_alloc(void)
198{
199 amdgpu_bo_handle bo;
200 amdgpu_va_handle va_handle;
201 uint64_t bo_mc;
202 int r;
203
204 /* Test visible VRAM */
205 bo = gpu_mem_alloc(device_handle,
206 4096, 4096,
207 AMDGPU_GEM_DOMAIN_VRAM,
208 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
209 &bo_mc, &va_handle);
210
211 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
212 CU_ASSERT_EQUAL(r, 0);
213
214 /* Test invisible VRAM */
215 bo = gpu_mem_alloc(device_handle,
216 4096, 4096,
217 AMDGPU_GEM_DOMAIN_VRAM,
218 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
219 &bo_mc, &va_handle);
220
221 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
222 CU_ASSERT_EQUAL(r, 0);
223
224 /* Test GART Cacheable */
225 bo = gpu_mem_alloc(device_handle,
226 4096, 4096,
227 AMDGPU_GEM_DOMAIN_GTT,
228 0, &bo_mc, &va_handle);
229
230 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
231 CU_ASSERT_EQUAL(r, 0);
232
233 /* Test GART USWC */
234 bo = gpu_mem_alloc(device_handle,
235 4096, 4096,
236 AMDGPU_GEM_DOMAIN_GTT,
237 AMDGPU_GEM_CREATE_CPU_GTT_USWC,
238 &bo_mc, &va_handle);
239
240 r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
241 CU_ASSERT_EQUAL(r, 0);
242}
243
244static void amdgpu_mem_fail_alloc(void)
245{
246 amdgpu_bo_handle bo;
247 int r;
248 struct amdgpu_bo_alloc_request req = {0};
249 amdgpu_bo_handle buf_handle;
250
251 /* Test impossible mem allocation, 1TB */
252 req.alloc_size = 0xE8D4A51000;
253 req.phys_alignment = 4096;
254 req.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
255 req.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
256
257 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
258 CU_ASSERT_EQUAL(r, -ENOMEM);
259
260 if (!r) {
261 r = amdgpu_bo_free(bo);
262 CU_ASSERT_EQUAL(r, 0);
263 }
264}
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 82c55aa8..7ad0f0dc 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -21,10 +21,6 @@
21 * 21 *
22*/ 22*/
23 23
24#ifdef HAVE_CONFIG_H
25#include "config.h"
26#endif
27
28#include <stdio.h> 24#include <stdio.h>
29 25
30#include "CUnit/Basic.h" 26#include "CUnit/Basic.h"
@@ -32,7 +28,7 @@
32#include "util_math.h" 28#include "util_math.h"
33 29
34#include "amdgpu_test.h" 30#include "amdgpu_test.h"
35#include "uvd_messages.h" 31#include "decode_messages.h"
36#include "amdgpu_drm.h" 32#include "amdgpu_drm.h"
37#include "amdgpu_internal.h" 33#include "amdgpu_internal.h"
38 34
@@ -66,6 +62,26 @@ CU_TestInfo cs_tests[] = {
66 CU_TEST_INFO_NULL, 62 CU_TEST_INFO_NULL,
67}; 63};
68 64
65CU_BOOL suite_cs_tests_enable(void)
66{
67 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
68 &minor_version, &device_handle))
69 return CU_FALSE;
70
71 family_id = device_handle->info.family_id;
72
73 if (amdgpu_device_deinitialize(device_handle))
74 return CU_FALSE;
75
76
77 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
78 printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
79 return CU_FALSE;
80 }
81
82 return CU_TRUE;
83}
84
69int suite_cs_tests_init(void) 85int suite_cs_tests_init(void)
70{ 86{
71 amdgpu_bo_handle ib_result_handle; 87 amdgpu_bo_handle ib_result_handle;
@@ -175,11 +191,11 @@ static int submit(unsigned ndw, unsigned ip)
175 191
176static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx) 192static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
177{ 193{
178 ib_cpu[(*idx)++] = 0x3BC4; 194 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4;
179 ib_cpu[(*idx)++] = addr; 195 ib_cpu[(*idx)++] = addr;
180 ib_cpu[(*idx)++] = 0x3BC5; 196 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5;
181 ib_cpu[(*idx)++] = addr >> 32; 197 ib_cpu[(*idx)++] = addr >> 32;
182 ib_cpu[(*idx)++] = 0x3BC3; 198 ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3;
183 ib_cpu[(*idx)++] = cmd << 1; 199 ib_cpu[(*idx)++] = cmd << 1;
184} 200}
185 201
@@ -211,10 +227,13 @@ static void amdgpu_cs_uvd_create(void)
211 CU_ASSERT_EQUAL(r, 0); 227 CU_ASSERT_EQUAL(r, 0);
212 228
213 memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); 229 memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
230
214 if (family_id >= AMDGPU_FAMILY_VI) { 231 if (family_id >= AMDGPU_FAMILY_VI) {
215 ((uint8_t*)msg)[0x10] = 7; 232 ((uint8_t*)msg)[0x10] = 7;
216 /* chip polaris 10/11 */ 233 /* chip beyond polaris 10/11 */
217 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { 234 if ((family_id == AMDGPU_FAMILY_AI) ||
235 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
236 chip_id == chip_rev+0x64)) {
218 /* dpb size */ 237 /* dpb size */
219 ((uint8_t*)msg)[0x28] = 0x00; 238 ((uint8_t*)msg)[0x28] = 0x00;
220 ((uint8_t*)msg)[0x29] = 0x94; 239 ((uint8_t*)msg)[0x29] = 0x94;
@@ -250,7 +269,7 @@ static void amdgpu_cs_uvd_create(void)
250 269
251static void amdgpu_cs_uvd_decode(void) 270static void amdgpu_cs_uvd_decode(void)
252{ 271{
253 const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280; 272 const unsigned dpb_size = 15923584, dt_size = 737280;
254 uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr; 273 uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
255 struct amdgpu_bo_alloc_request req = {0}; 274 struct amdgpu_bo_alloc_request req = {0};
256 amdgpu_bo_handle buf_handle; 275 amdgpu_bo_handle buf_handle;
@@ -286,14 +305,18 @@ static void amdgpu_cs_uvd_decode(void)
286 r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr); 305 r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
287 CU_ASSERT_EQUAL(r, 0); 306 CU_ASSERT_EQUAL(r, 0);
288 307
289 memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg)); 308 memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg));
309 memcpy(ptr + sizeof(uvd_decode_msg), avc_decode_msg, sizeof(avc_decode_msg));
310
290 if (family_id >= AMDGPU_FAMILY_VI) { 311 if (family_id >= AMDGPU_FAMILY_VI) {
291 ptr[0x10] = 7; 312 ptr[0x10] = 7;
292 ptr[0x98] = 0x00; 313 ptr[0x98] = 0x00;
293 ptr[0x99] = 0x02; 314 ptr[0x99] = 0x02;
294 /* chip polaris10/11 */ 315 /* chip beyond polaris10/11 */
295 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { 316 if ((family_id == AMDGPU_FAMILY_AI) ||
296 /*dpb size */ 317 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
318 chip_id == chip_rev+0x64)) {
319 /* dpb size */
297 ptr[0x24] = 0x00; 320 ptr[0x24] = 0x00;
298 ptr[0x25] = 0x94; 321 ptr[0x25] = 0x94;
299 ptr[0x26] = 0x6B; 322 ptr[0x26] = 0x6B;
@@ -335,9 +358,12 @@ static void amdgpu_cs_uvd_decode(void)
335 bs_addr = fb_addr + 4*1024; 358 bs_addr = fb_addr + 4*1024;
336 dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); 359 dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
337 360
338 if ((family_id >= AMDGPU_FAMILY_VI) && 361 if (family_id >= AMDGPU_FAMILY_VI) {
339 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { 362 if ((family_id == AMDGPU_FAMILY_AI) ||
340 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); 363 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
364 chip_id == chip_rev+0x64)) {
365 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
366 }
341 } 367 }
342 368
343 dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); 369 dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
@@ -348,12 +374,16 @@ static void amdgpu_cs_uvd_decode(void)
348 uvd_cmd(dt_addr, 0x2, &i); 374 uvd_cmd(dt_addr, 0x2, &i);
349 uvd_cmd(fb_addr, 0x3, &i); 375 uvd_cmd(fb_addr, 0x3, &i);
350 uvd_cmd(bs_addr, 0x100, &i); 376 uvd_cmd(bs_addr, 0x100, &i);
377
351 if (family_id >= AMDGPU_FAMILY_VI) { 378 if (family_id >= AMDGPU_FAMILY_VI) {
352 uvd_cmd(it_addr, 0x204, &i); 379 uvd_cmd(it_addr, 0x204, &i);
353 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) 380 if ((family_id == AMDGPU_FAMILY_AI) ||
381 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
382 chip_id == chip_rev+0x64))
354 uvd_cmd(ctx_addr, 0x206, &i); 383 uvd_cmd(ctx_addr, 0x206, &i);
355} 384 }
356 ib_cpu[i++] = 0x3BC6; 385
386 ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
357 ib_cpu[i++] = 0x1; 387 ib_cpu[i++] = 0x1;
358 for (; i % 16; ++i) 388 for (; i % 16; ++i)
359 ib_cpu[i] = 0x80000000; 389 ib_cpu[i] = 0x80000000;
@@ -364,7 +394,7 @@ static void amdgpu_cs_uvd_decode(void)
364 /* TODO: use a real CRC32 */ 394 /* TODO: use a real CRC32 */
365 for (i = 0, sum = 0; i < dt_size; ++i) 395 for (i = 0, sum = 0; i < dt_size; ++i)
366 sum += ptr[i]; 396 sum += ptr[i];
367 CU_ASSERT_EQUAL(sum, 0x20345d8); 397 CU_ASSERT_EQUAL(sum, SUM_DECODE);
368 398
369 r = amdgpu_bo_cpu_unmap(buf_handle); 399 r = amdgpu_bo_cpu_unmap(buf_handle);
370 CU_ASSERT_EQUAL(r, 0); 400 CU_ASSERT_EQUAL(r, 0);
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
new file mode 100644
index 00000000..1eb5761a
--- /dev/null
+++ b/tests/amdgpu/deadlock_tests.c
@@ -0,0 +1,255 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22*/
23
24#include <stdio.h>
25#include <stdlib.h>
26#include <unistd.h>
27#ifdef HAVE_ALLOCA_H
28# include <alloca.h>
29#endif
30
31#include "CUnit/Basic.h"
32
33#include "amdgpu_test.h"
34#include "amdgpu_drm.h"
35#include "amdgpu_internal.h"
36
37#include <pthread.h>
38
39
40/*
41 * This defines the delay in MS after which memory location designated for
42 * compression against reference value is written to, unblocking command
43 * processor
44 */
45#define WRITE_MEM_ADDRESS_DELAY_MS 100
46
47#define PACKET_TYPE3 3
48
49#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
50 (((op) & 0xFF) << 8) | \
51 ((n) & 0x3FFF) << 16)
52
53#define PACKET3_WAIT_REG_MEM 0x3C
54#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
55 /* 0 - always
56 * 1 - <
57 * 2 - <=
58 * 3 - ==
59 * 4 - !=
60 * 5 - >=
61 * 6 - >
62 */
63#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
64 /* 0 - reg
65 * 1 - mem
66 */
67#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
68 /* 0 - wait_reg_mem
69 * 1 - wr_wait_wr_reg
70 */
71#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
72 /* 0 - me
73 * 1 - pfp
74 */
75
76static amdgpu_device_handle device_handle;
77static uint32_t major_version;
78static uint32_t minor_version;
79
80static pthread_t stress_thread;
81static uint32_t *ptr;
82
83static void amdgpu_deadlock_helper(unsigned ip_type);
84static void amdgpu_deadlock_gfx(void);
85static void amdgpu_deadlock_compute(void);
86
87CU_BOOL suite_deadlock_tests_enable(void)
88{
89 CU_BOOL enable = CU_TRUE;
90
91 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
92 &minor_version, &device_handle))
93 return CU_FALSE;
94
95 if (device_handle->info.family_id == AMDGPU_FAMILY_AI ||
96 device_handle->info.family_id == AMDGPU_FAMILY_SI) {
97 printf("\n\nCurrently hangs the CP on this ASIC, deadlock suite disabled\n");
98 enable = CU_FALSE;
99 }
100
101 if (amdgpu_device_deinitialize(device_handle))
102 return CU_FALSE;
103
104 return enable;
105}
106
107int suite_deadlock_tests_init(void)
108{
109 int r;
110
111 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
112 &minor_version, &device_handle);
113
114 if (r) {
115 if ((r == -EACCES) && (errno == EACCES))
116 printf("\n\nError:%s. "
117 "Hint:Try to run this test program as root.",
118 strerror(errno));
119 return CUE_SINIT_FAILED;
120 }
121
122 return CUE_SUCCESS;
123}
124
125int suite_deadlock_tests_clean(void)
126{
127 int r = amdgpu_device_deinitialize(device_handle);
128
129 if (r == 0)
130 return CUE_SUCCESS;
131 else
132 return CUE_SCLEAN_FAILED;
133}
134
135
136CU_TestInfo deadlock_tests[] = {
137 { "gfx ring block test", amdgpu_deadlock_gfx },
138 { "compute ring block test", amdgpu_deadlock_compute },
139 CU_TEST_INFO_NULL,
140};
141
142static void *write_mem_address(void *data)
143{
144 int i;
145
146 /* useconds_t range is [0, 1,000,000] so use loop for waits > 1s */
147 for (i = 0; i < WRITE_MEM_ADDRESS_DELAY_MS; i++)
148 usleep(1000);
149
150 ptr[256] = 0x1;
151
152 return 0;
153}
154
155static void amdgpu_deadlock_gfx(void)
156{
157 amdgpu_deadlock_helper(AMDGPU_HW_IP_GFX);
158}
159
160static void amdgpu_deadlock_compute(void)
161{
162 amdgpu_deadlock_helper(AMDGPU_HW_IP_COMPUTE);
163}
164
165static void amdgpu_deadlock_helper(unsigned ip_type)
166{
167 amdgpu_context_handle context_handle;
168 amdgpu_bo_handle ib_result_handle;
169 void *ib_result_cpu;
170 uint64_t ib_result_mc_address;
171 struct amdgpu_cs_request ibs_request;
172 struct amdgpu_cs_ib_info ib_info;
173 struct amdgpu_cs_fence fence_status;
174 uint32_t expired;
175 int i, r;
176 amdgpu_bo_list_handle bo_list;
177 amdgpu_va_handle va_handle;
178
179 r = pthread_create(&stress_thread, NULL, write_mem_address, NULL);
180 CU_ASSERT_EQUAL(r, 0);
181
182 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
183 CU_ASSERT_EQUAL(r, 0);
184
185 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
186 AMDGPU_GEM_DOMAIN_GTT, 0,
187 &ib_result_handle, &ib_result_cpu,
188 &ib_result_mc_address, &va_handle);
189 CU_ASSERT_EQUAL(r, 0);
190
191 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
192 &bo_list);
193 CU_ASSERT_EQUAL(r, 0);
194
195 ptr = ib_result_cpu;
196
197 ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5);
198 ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
199 WAIT_REG_MEM_FUNCTION(4) | /* != */
200 WAIT_REG_MEM_ENGINE(0)); /* me */
201 ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc;
202 ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
203 ptr[4] = 0x00000000; /* reference value */
204 ptr[5] = 0xffffffff; /* and mask */
205 ptr[6] = 0x00000004; /* poll interval */
206
207 for (i = 7; i < 16; ++i)
208 ptr[i] = 0xffff1000;
209
210
211 ptr[256] = 0x0; /* the memory we wait on to change */
212
213
214
215 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
216 ib_info.ib_mc_address = ib_result_mc_address;
217 ib_info.size = 16;
218
219 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
220 ibs_request.ip_type = ip_type;
221 ibs_request.ring = 0;
222 ibs_request.number_of_ibs = 1;
223 ibs_request.ibs = &ib_info;
224 ibs_request.resources = bo_list;
225 ibs_request.fence_info.handle = NULL;
226
227 for (i = 0; i < 200; i++) {
228 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
229 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
230
231 }
232
233 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
234 fence_status.context = context_handle;
235 fence_status.ip_type = ip_type;
236 fence_status.ip_instance = 0;
237 fence_status.ring = 0;
238 fence_status.fence = ibs_request.seq_no;
239
240 r = amdgpu_cs_query_fence_status(&fence_status,
241 AMDGPU_TIMEOUT_INFINITE,0, &expired);
242 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
243
244 pthread_join(stress_thread, NULL);
245
246 r = amdgpu_bo_list_destroy(bo_list);
247 CU_ASSERT_EQUAL(r, 0);
248
249 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
250 ib_result_mc_address, 4096);
251 CU_ASSERT_EQUAL(r, 0);
252
253 r = amdgpu_cs_ctx_free(context_handle);
254 CU_ASSERT_EQUAL(r, 0);
255}
diff --git a/tests/amdgpu/uvd_messages.h b/tests/amdgpu/decode_messages.h
index 00235cbb..bd6fe4b6 100644
--- a/tests/amdgpu/uvd_messages.h
+++ b/tests/amdgpu/decode_messages.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc. 2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,10 @@
21 * 21 *
22 */ 22 */
23 23
24#ifndef _UVD_MESSAGES_H_ 24#ifndef _DECODE_MESSAGES_H_
25#define _UVD_MESSAGES_H_ 25#define _DECODE_MESSAGES_H_
26
27#define SUM_DECODE 0x20345d8
26 28
27static const uint8_t uvd_create_msg[] = { 29static const uint8_t uvd_create_msg[] = {
28 0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, 30 0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
@@ -356,6 +358,9 @@ static const uint8_t uvd_decode_msg[] = {
356 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 358 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
357 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 359 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
358 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 360 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
361};
362
363static const uint8_t avc_decode_msg[] = {
359 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x88,0x00,0x00,0x00, 364 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
360 0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 365 0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
361 0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, 366 0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
@@ -810,4 +815,34 @@ static const uint8_t uvd_it_scaling_table[] = {
810 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, 815 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
811}; 816};
812 817
813#endif /* _UVD_MESSAGES_H_ */ 818static const uint8_t vcn_dec_create_msg[] = {
819 0x28,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
820 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x28,0x00,0x00,0x00,
821 0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
822 0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
823};
824
825static const uint8_t vcn_dec_decode_msg[] = {
826 0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
827 0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00,
828 0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00,
829 0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
830 0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x94,0x6b,0x00,
831 0x96,0x4e,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x50,0x00,
832 0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
833 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
834 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
835 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
836 0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
837 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
838 0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00,
839 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
840 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
841};
842
843static const uint8_t vcn_dec_destroy_msg[] = {
844 0x28,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,
845 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
846};
847
848#endif /* _DECODE_MESSAGES_H_ */
diff --git a/tests/amdgpu/frame.h b/tests/amdgpu/frame.h
index 4c946c27..335401c1 100644
--- a/tests/amdgpu/frame.h
+++ b/tests/amdgpu/frame.h
@@ -24,7 +24,7 @@
24#ifndef _frame_h_ 24#ifndef _frame_h_
25#define _frame_h_ 25#define _frame_h_
26 26
27const uint8_t frame[] = { 27static const uint8_t frame[] = {
28 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 28 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb,
29 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 29 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2,
30 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, 30 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa,
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
new file mode 100644
index 00000000..4c1237c6
--- /dev/null
+++ b/tests/amdgpu/meson.build
@@ -0,0 +1,34 @@
1# Copyright © 2017-2018 Intel Corporation
2
3# Permission is hereby granted, free of charge, to any person obtaining a copy
4# of this software and associated documentation files (the "Software"), to deal
5# in the Software without restriction, including without limitation the rights
6# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7# copies of the Software, and to permit persons to whom the Software is
8# furnished to do so, subject to the following conditions:
9
10# The above copyright notice and this permission notice shall be included in
11# all copies or substantial portions of the Software.
12
13# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
19# SOFTWARE.
20
21if dep_cunit.found()
22 amdgpu_test = executable(
23 'amdgpu_test',
24 files(
25 'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
26 'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
27 'vm_tests.c',
28 ),
29 dependencies : [dep_cunit, dep_threads],
30 include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
31 link_with : [libdrm, libdrm_amdgpu],
32 install : with_install_tests,
33 )
34endif
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
new file mode 100644
index 00000000..b4251bcf
--- /dev/null
+++ b/tests/amdgpu/uvd_enc_tests.c
@@ -0,0 +1,491 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22*/
23
24#include <stdio.h>
25#include <inttypes.h>
26
27#include "CUnit/Basic.h"
28
29#include "util_math.h"
30
31#include "amdgpu_test.h"
32#include "amdgpu_drm.h"
33#include "amdgpu_internal.h"
34#include "frame.h"
35#include "uve_ib.h"
36
37#define IB_SIZE 4096
38#define MAX_RESOURCES 16
39
40struct amdgpu_uvd_enc_bo {
41 amdgpu_bo_handle handle;
42 amdgpu_va_handle va_handle;
43 uint64_t addr;
44 uint64_t size;
45 uint8_t *ptr;
46};
47
48struct amdgpu_uvd_enc {
49 unsigned width;
50 unsigned height;
51 struct amdgpu_uvd_enc_bo session;
52 struct amdgpu_uvd_enc_bo vbuf;
53 struct amdgpu_uvd_enc_bo bs;
54 struct amdgpu_uvd_enc_bo fb;
55 struct amdgpu_uvd_enc_bo cpb;
56};
57
58static amdgpu_device_handle device_handle;
59static uint32_t major_version;
60static uint32_t minor_version;
61static uint32_t family_id;
62
63static amdgpu_context_handle context_handle;
64static amdgpu_bo_handle ib_handle;
65static amdgpu_va_handle ib_va_handle;
66static uint64_t ib_mc_address;
67static uint32_t *ib_cpu;
68
69static struct amdgpu_uvd_enc enc;
70static amdgpu_bo_handle resources[MAX_RESOURCES];
71static unsigned num_resources;
72
73static void amdgpu_cs_uvd_enc_create(void);
74static void amdgpu_cs_uvd_enc_session_init(void);
75static void amdgpu_cs_uvd_enc_encode(void);
76static void amdgpu_cs_uvd_enc_destroy(void);
77
78
79CU_TestInfo uvd_enc_tests[] = {
80 { "UVD ENC create", amdgpu_cs_uvd_enc_create },
81 { "UVD ENC session init", amdgpu_cs_uvd_enc_session_init },
82 { "UVD ENC encode", amdgpu_cs_uvd_enc_encode },
83 { "UVD ENC destroy", amdgpu_cs_uvd_enc_destroy },
84 CU_TEST_INFO_NULL,
85};
86
87CU_BOOL suite_uvd_enc_tests_enable(void)
88{
89 int r;
90 struct drm_amdgpu_info_hw_ip info;
91
92 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
93 &minor_version, &device_handle))
94 return CU_FALSE;
95
96 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info);
97
98 if (amdgpu_device_deinitialize(device_handle))
99 return CU_FALSE;
100
101 if (!info.available_rings)
102 printf("\n\nThe ASIC NOT support UVD ENC, suite disabled.\n");
103
104 return (r == 0 && (info.available_rings ? CU_TRUE : CU_FALSE));
105}
106
107
108int suite_uvd_enc_tests_init(void)
109{
110 int r;
111
112 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
113 &minor_version, &device_handle);
114 if (r)
115 return CUE_SINIT_FAILED;
116
117 family_id = device_handle->info.family_id;
118
119 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
120 if (r)
121 return CUE_SINIT_FAILED;
122
123 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
124 AMDGPU_GEM_DOMAIN_GTT, 0,
125 &ib_handle, (void**)&ib_cpu,
126 &ib_mc_address, &ib_va_handle);
127 if (r)
128 return CUE_SINIT_FAILED;
129
130 return CUE_SUCCESS;
131}
132
133int suite_uvd_enc_tests_clean(void)
134{
135 int r;
136
137 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
138 ib_mc_address, IB_SIZE);
139 if (r)
140 return CUE_SCLEAN_FAILED;
141
142 r = amdgpu_cs_ctx_free(context_handle);
143 if (r)
144 return CUE_SCLEAN_FAILED;
145
146 r = amdgpu_device_deinitialize(device_handle);
147 if (r)
148 return CUE_SCLEAN_FAILED;
149
150 return CUE_SUCCESS;
151}
152
153static int submit(unsigned ndw, unsigned ip)
154{
155 struct amdgpu_cs_request ibs_request = {0};
156 struct amdgpu_cs_ib_info ib_info = {0};
157 struct amdgpu_cs_fence fence_status = {0};
158 uint32_t expired;
159 int r;
160
161 ib_info.ib_mc_address = ib_mc_address;
162 ib_info.size = ndw;
163
164 ibs_request.ip_type = ip;
165
166 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
167 NULL, &ibs_request.resources);
168 if (r)
169 return r;
170
171 ibs_request.number_of_ibs = 1;
172 ibs_request.ibs = &ib_info;
173 ibs_request.fence_info.handle = NULL;
174
175 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
176 if (r)
177 return r;
178
179 r = amdgpu_bo_list_destroy(ibs_request.resources);
180 if (r)
181 return r;
182
183 fence_status.context = context_handle;
184 fence_status.ip_type = ip;
185 fence_status.fence = ibs_request.seq_no;
186
187 r = amdgpu_cs_query_fence_status(&fence_status,
188 AMDGPU_TIMEOUT_INFINITE,
189 0, &expired);
190 if (r)
191 return r;
192
193 return 0;
194}
195
196static void alloc_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo,
197 unsigned size, unsigned domain)
198{
199 struct amdgpu_bo_alloc_request req = {0};
200 amdgpu_bo_handle buf_handle;
201 amdgpu_va_handle va_handle;
202 uint64_t va = 0;
203 int r;
204
205 req.alloc_size = ALIGN(size, 4096);
206 req.preferred_heap = domain;
207 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
208 CU_ASSERT_EQUAL(r, 0);
209 r = amdgpu_va_range_alloc(device_handle,
210 amdgpu_gpu_va_range_general,
211 req.alloc_size, 1, 0, &va,
212 &va_handle, 0);
213 CU_ASSERT_EQUAL(r, 0);
214 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
215 AMDGPU_VA_OP_MAP);
216 CU_ASSERT_EQUAL(r, 0);
217 uvd_enc_bo->addr = va;
218 uvd_enc_bo->handle = buf_handle;
219 uvd_enc_bo->size = req.alloc_size;
220 uvd_enc_bo->va_handle = va_handle;
221 r = amdgpu_bo_cpu_map(uvd_enc_bo->handle, (void **)&uvd_enc_bo->ptr);
222 CU_ASSERT_EQUAL(r, 0);
223 memset(uvd_enc_bo->ptr, 0, size);
224 r = amdgpu_bo_cpu_unmap(uvd_enc_bo->handle);
225 CU_ASSERT_EQUAL(r, 0);
226}
227
228static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo)
229{
230 int r;
231
232 r = amdgpu_bo_va_op(uvd_enc_bo->handle, 0, uvd_enc_bo->size,
233 uvd_enc_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
234 CU_ASSERT_EQUAL(r, 0);
235
236 r = amdgpu_va_range_free(uvd_enc_bo->va_handle);
237 CU_ASSERT_EQUAL(r, 0);
238
239 r = amdgpu_bo_free(uvd_enc_bo->handle);
240 CU_ASSERT_EQUAL(r, 0);
241 memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo));
242}
243
244static void amdgpu_cs_uvd_enc_create(void)
245{
246 enc.width = 160;
247 enc.height = 128;
248
249 num_resources = 0;
250 alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT);
251 resources[num_resources++] = enc.session.handle;
252 resources[num_resources++] = ib_handle;
253}
254
255static void check_result(struct amdgpu_uvd_enc *enc)
256{
257 uint64_t sum;
258 uint32_t s = 175602;
259 uint32_t *ptr, size;
260 int j, r;
261
262 r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr);
263 CU_ASSERT_EQUAL(r, 0);
264 ptr = (uint32_t *)enc->fb.ptr;
265 size = ptr[6];
266 r = amdgpu_bo_cpu_unmap(enc->fb.handle);
267 CU_ASSERT_EQUAL(r, 0);
268 r = amdgpu_bo_cpu_map(enc->bs.handle, (void **)&enc->bs.ptr);
269 CU_ASSERT_EQUAL(r, 0);
270 for (j = 0, sum = 0; j < size; ++j)
271 sum += enc->bs.ptr[j];
272 CU_ASSERT_EQUAL(sum, s);
273 r = amdgpu_bo_cpu_unmap(enc->bs.handle);
274 CU_ASSERT_EQUAL(r, 0);
275
276}
277
278static void amdgpu_cs_uvd_enc_session_init(void)
279{
280 int len, r;
281
282 len = 0;
283 memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
284 len += sizeof(uve_session_info) / 4;
285 ib_cpu[len++] = enc.session.addr >> 32;
286 ib_cpu[len++] = enc.session.addr;
287
288 memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info));
289 len += sizeof(uve_task_info) / 4;
290 ib_cpu[len++] = 0x000000d8;
291 ib_cpu[len++] = 0x00000000;
292 ib_cpu[len++] = 0x00000000;
293
294 memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init));
295 len += sizeof(uve_op_init) / 4;
296
297 memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init));
298 len += sizeof(uve_session_init) / 4;
299
300 memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl));
301 len += sizeof(uve_layer_ctrl) / 4;
302
303 memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl));
304 len += sizeof(uve_slice_ctrl) / 4;
305
306 memcpy((ib_cpu + len), uve_spec_misc, sizeof(uve_spec_misc));
307 len += sizeof(uve_spec_misc) / 4;
308
309 memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init));
310 len += sizeof(uve_rc_session_init) / 4;
311
312 memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter));
313 len += sizeof(uve_deblocking_filter) / 4;
314
315 memcpy((ib_cpu + len), uve_quality_params, sizeof(uve_quality_params));
316 len += sizeof(uve_quality_params) / 4;
317
318 memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc));
319 len += sizeof(uve_op_init_rc) / 4;
320
321 memcpy((ib_cpu + len), uve_op_init_rc_vbv_level, sizeof(uve_op_init_rc_vbv_level));
322 len += sizeof(uve_op_init_rc_vbv_level) / 4;
323
324 r = submit(len, AMDGPU_HW_IP_UVD_ENC);
325 CU_ASSERT_EQUAL(r, 0);
326}
327
328static void amdgpu_cs_uvd_enc_encode(void)
329{
330 int len, r, i;
331 uint64_t luma_offset, chroma_offset;
332 uint32_t vbuf_size, bs_size = 0x003f4800, cpb_size;
333 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
334 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
335 cpb_size = vbuf_size * 10;
336
337
338 num_resources = 0;
339 alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM);
340 resources[num_resources++] = enc.fb.handle;
341 alloc_resource(&enc.bs, bs_size, AMDGPU_GEM_DOMAIN_VRAM);
342 resources[num_resources++] = enc.bs.handle;
343 alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
344 resources[num_resources++] = enc.vbuf.handle;
345 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
346 resources[num_resources++] = enc.cpb.handle;
347 resources[num_resources++] = ib_handle;
348
349 r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
350 CU_ASSERT_EQUAL(r, 0);
351
352 memset(enc.vbuf.ptr, 0, vbuf_size);
353 for (i = 0; i < enc.height; ++i) {
354 memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
355 enc.vbuf.ptr += ALIGN(enc.width, align);
356 }
357 for (i = 0; i < enc.height / 2; ++i) {
358 memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
359 enc.vbuf.ptr += ALIGN(enc.width, align);
360 }
361
362 r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
363 CU_ASSERT_EQUAL(r, 0);
364
365 len = 0;
366 memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
367 len += sizeof(uve_session_info) / 4;
368 ib_cpu[len++] = enc.session.addr >> 32;
369 ib_cpu[len++] = enc.session.addr;
370
371 memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info));
372 len += sizeof(uve_task_info) / 4;
373 ib_cpu[len++] = 0x000005e0;
374 ib_cpu[len++] = 0x00000001;
375 ib_cpu[len++] = 0x00000001;
376
377 memcpy((ib_cpu + len), uve_nalu_buffer_1, sizeof(uve_nalu_buffer_1));
378 len += sizeof(uve_nalu_buffer_1) / 4;
379
380 memcpy((ib_cpu + len), uve_nalu_buffer_2, sizeof(uve_nalu_buffer_2));
381 len += sizeof(uve_nalu_buffer_2) / 4;
382
383 memcpy((ib_cpu + len), uve_nalu_buffer_3, sizeof(uve_nalu_buffer_3));
384 len += sizeof(uve_nalu_buffer_3) / 4;
385
386 memcpy((ib_cpu + len), uve_nalu_buffer_4, sizeof(uve_nalu_buffer_4));
387 len += sizeof(uve_nalu_buffer_4) / 4;
388
389 memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header));
390 len += sizeof(uve_slice_header) / 4;
391
392 ib_cpu[len++] = 0x00000254;
393 ib_cpu[len++] = 0x00000010;
394 ib_cpu[len++] = enc.cpb.addr >> 32;
395 ib_cpu[len++] = enc.cpb.addr;
396 memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer));
397 len += sizeof(uve_ctx_buffer) / 4;
398
399 memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer));
400 len += sizeof(uve_bitstream_buffer) / 4;
401 ib_cpu[len++] = 0x00000000;
402 ib_cpu[len++] = enc.bs.addr >> 32;
403 ib_cpu[len++] = enc.bs.addr;
404 ib_cpu[len++] = 0x003f4800;
405 ib_cpu[len++] = 0x00000000;
406
407 memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer));
408 len += sizeof(uve_feedback_buffer) / 4;
409 ib_cpu[len++] = enc.fb.addr >> 32;
410 ib_cpu[len++] = enc.fb.addr;
411 ib_cpu[len++] = 0x00000010;
412 ib_cpu[len++] = 0x00000028;
413
414 memcpy((ib_cpu + len), uve_feedback_buffer_additional, sizeof(uve_feedback_buffer_additional));
415 len += sizeof(uve_feedback_buffer_additional) / 4;
416
417 memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh));
418 len += sizeof(uve_intra_refresh) / 4;
419
420 memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select));
421 len += sizeof(uve_layer_select) / 4;
422
423 memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init));
424 len += sizeof(uve_rc_layer_init) / 4;
425
426 memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select));
427 len += sizeof(uve_layer_select) / 4;
428
429 memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic));
430 len += sizeof(uve_rc_per_pic) / 4;
431
432 unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16);
433 luma_offset = enc.vbuf.addr;
434 chroma_offset = luma_offset + luma_size;
435 ib_cpu[len++] = 0x00000054;
436 ib_cpu[len++] = 0x0000000c;
437 ib_cpu[len++] = 0x00000002;
438 ib_cpu[len++] = 0x003f4800;
439 ib_cpu[len++] = luma_offset >> 32;
440 ib_cpu[len++] = luma_offset;
441 ib_cpu[len++] = chroma_offset >> 32;
442 ib_cpu[len++] = chroma_offset;
443 memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param));
444 ib_cpu[len] = ALIGN(enc.width, align);
445 ib_cpu[len + 1] = ALIGN(enc.width, align);
446 len += sizeof(uve_encode_param) / 4;
447
448 memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode));
449 len += sizeof(uve_op_speed_enc_mode) / 4;
450
451 memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode));
452 len += sizeof(uve_op_encode) / 4;
453
454 r = submit(len, AMDGPU_HW_IP_UVD_ENC);
455 CU_ASSERT_EQUAL(r, 0);
456
457 check_result(&enc);
458
459 free_resource(&enc.fb);
460 free_resource(&enc.bs);
461 free_resource(&enc.vbuf);
462 free_resource(&enc.cpb);
463}
464
465static void amdgpu_cs_uvd_enc_destroy(void)
466{
467 int len, r;
468
469 num_resources = 0;
470 resources[num_resources++] = ib_handle;
471
472 len = 0;
473 memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
474 len += sizeof(uve_session_info) / 4;
475 ib_cpu[len++] = enc.session.addr >> 32;
476 ib_cpu[len++] = enc.session.addr;
477
478 memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info));
479 len += sizeof(uve_task_info) / 4;
480 ib_cpu[len++] = 0xffffffff;
481 ib_cpu[len++] = 0x00000002;
482 ib_cpu[len++] = 0x00000000;
483
484 memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close));
485 len += sizeof(uve_op_close) / 4;
486
487 r = submit(len, AMDGPU_HW_IP_UVD_ENC);
488 CU_ASSERT_EQUAL(r, 0);
489
490 free_resource(&enc.session);
491}
diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h
new file mode 100644
index 00000000..cb72be22
--- /dev/null
+++ b/tests/amdgpu/uve_ib.h
@@ -0,0 +1,527 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22*/
23
24#ifndef _uve_ib_h_
25#define _uve_ib_h_
26
27static const uint32_t uve_session_info[] = {
28 0x00000018,
29 0x00000001,
30 0x00000000,
31 0x00010000,
32};
33
34static const uint32_t uve_task_info[] = {
35 0x00000014,
36 0x00000002,
37};
38
39static const uint32_t uve_session_init[] = {
40 0x00000020,
41 0x00000003,
42 0x000000c0,
43 0x00000080,
44 0x00000020,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48};
49
50static const uint32_t uve_layer_ctrl[] = {
51 0x00000010,
52 0x00000004,
53 0x00000001,
54 0x00000001,
55};
56
57static const uint32_t uve_layer_select[] = {
58 0x0000000c,
59 0x00000005,
60 0x00000000,
61};
62
63static const uint32_t uve_slice_ctrl[] = {
64 0x00000014,
65 0x00000006,
66 0x00000000,
67 0x00000006,
68 0x00000006,
69};
70
71static const uint32_t uve_spec_misc[] = {
72 0x00000024,
73 0x00000007,
74 0x00000000,
75 0x00000000,
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000001,
80 0x00000001,
81};
82
83static const uint32_t uve_rc_session_init[] = {
84 0x00000010,
85 0x00000008,
86 0x00000000,
87 0x00000040,
88};
89
90static const uint32_t uve_rc_layer_init[] = {
91 0x00000028,
92 0x00000009,
93 0x001e8480,
94 0x001e8480,
95 0x0000001e,
96 0x00000001,
97 0x0001046a,
98 0x0001046a,
99 0x0001046a,
100 0xaaaaaaaa,
101};
102
103static const uint32_t uve_deblocking_filter[] = {
104 0x00000020,
105 0x0000000e,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112};
113
114static const uint32_t uve_quality_params[] = {
115 0x00000014,
116 0x0000000d,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120};
121
122static const uint32_t uve_feedback_buffer[] = {
123 0x0000001c,
124 0x00000012,
125 0x00000000,
126};
127
128static const uint32_t uve_feedback_buffer_additional[] = {
129 0x00000108,
130 0x00000014,
131 0x00000001,
132 0x00000010,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139 0x00000000,
140 0x00000000,
141 0x00000000,
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195};
196
197static const uint32_t uve_nalu_buffer_1[] = {
198 0x00000018,
199 0x00000013,
200 0x00000001,
201 0x00000007,
202 0x00000001,
203 0x46011000,
204};
205
206static const uint32_t uve_nalu_buffer_2[] = {
207 0x0000002c,
208 0x00000013,
209 0x00000002,
210 0x0000001b,
211 0x00000001,
212 0x40010c01,
213 0xffff0160,
214 0x00000300,
215 0xb0000003,
216 0x00000300,
217 0x962c0900,
218};
219
220static const uint32_t uve_nalu_buffer_3[] = {
221 0x00000034,
222 0x00000013,
223 0x00000003,
224 0x00000023,
225 0x00000001,
226 0x42010101,
227 0x60000003,
228 0x00b00000,
229 0x03000003,
230 0x0096a018,
231 0x2020708f,
232 0xcb924295,
233 0x12e08000,
234};
235
236static const uint32_t uve_nalu_buffer_4[] = {
237 0x0000001c,
238 0x00000013,
239 0x00000004,
240 0x0000000b,
241 0x00000001,
242 0x4401e0f1,
243 0x80992000,
244};
245
246static const uint32_t uve_slice_header[] = {
247 0x000000c8,
248 0x0000000b,
249 0x28010000,
250 0x40000000,
251 0x60000000,
252 0x00000000,
253 0x00000000,
254 0x00000000,
255 0x00000000,
256 0x00000000,
257 0x00000000,
258 0x00000000,
259 0x00000000,
260 0x00000000,
261 0x00000000,
262 0x00000000,
263 0x00000000,
264 0x00000000,
265 0x00000002,
266 0x00000010,
267 0x00000003,
268 0x00000000,
269 0x00000002,
270 0x00000002,
271 0x00000004,
272 0x00000000,
273 0x00000001,
274 0x00000000,
275 0x00000002,
276 0x00000003,
277 0x00000005,
278 0x00000000,
279 0x00000002,
280 0x00000000,
281 0x00000000,
282 0x00000000,
283 0x00000000,
284 0x00000000,
285 0x00000000,
286 0x00000000,
287 0x00000000,
288 0x00000000,
289 0x00000000,
290 0x00000000,
291 0x00000000,
292 0x00000000,
293 0x00000000,
294 0x00000000,
295 0x00000000,
296 0x00000000,
297};
298
299static const uint32_t uve_encode_param[] = {
300 0x00000000,
301 0x00000000,
302 0x00000000,
303 0x00000000,
304 0xffffffff,
305 0x00000001,
306 0x00000000,
307 0x00000000,
308 0x00000000,
309 0x00000000,
310 0x00000000,
311 0x00000000,
312 0x00000000,
313};
314
315static const uint32_t uve_intra_refresh[] = {
316 0x00000014,
317 0x0000000f,
318 0x00000000,
319 0x00000000,
320 0x00000001,
321};
322
323static const uint32_t uve_ctx_buffer[] = {
324 0x00000000,
325 0x00000000,
326 0x000000a0,
327 0x000000a0,
328 0x00000000,
329 0x00000000,
330 0x00000000,
331 0x00000000,
332 0x00000000,
333 0x00000000,
334 0x00000000,
335 0x00000000,
336 0x00000000,
337 0x00000000,
338 0x00000000,
339 0x00000000,
340 0x00000000,
341 0x00000000,
342 0x00000000,
343 0x00000000,
344 0x00000000,
345 0x00000000,
346 0x00000000,
347 0x00000000,
348 0x00000000,
349 0x00000000,
350 0x00000000,
351 0x00000000,
352 0x00000000,
353 0x00000000,
354 0x00000000,
355 0x00000000,
356 0x00000000,
357 0x00000000,
358 0x00000000,
359 0x00000000,
360 0x00000000,
361 0x00000000,
362 0x00000000,
363 0x00000000,
364 0x00000000,
365 0x00000000,
366 0x00000000,
367 0x00000000,
368 0x00000000,
369 0x00000000,
370 0x00000000,
371 0x00000000,
372 0x00000000,
373 0x00000000,
374 0x00000000,
375 0x00000000,
376 0x00000000,
377 0x00000000,
378 0x00000000,
379 0x00000000,
380 0x00000000,
381 0x00000000,
382 0x00000000,
383 0x00000000,
384 0x00000000,
385 0x00000000,
386 0x00000000,
387 0x00000000,
388 0x00000000,
389 0x00000000,
390 0x00000000,
391 0x00000000,
392 0x00000000,
393 0x00000000,
394 0x00000000,
395 0x00000000,
396 0x00000000,
397 0x00000000,
398 0x00000000,
399 0x00000000,
400 0x00000000,
401 0x00000000,
402 0x00000000,
403 0x00000000,
404 0x00000000,
405 0x00000000,
406 0x00000000,
407 0x00000000,
408 0x00000000,
409 0x00000000,
410 0x00000000,
411 0x00000000,
412 0x00000000,
413 0x00000000,
414 0x00000000,
415 0x00000000,
416 0x00000000,
417 0x00000000,
418 0x00000000,
419 0x00000000,
420 0x00000000,
421 0x00000000,
422 0x00000000,
423 0x00000000,
424 0x00000000,
425 0x00000000,
426 0x00000000,