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authorAndrey Grodzovsky2017-11-24 14:19:09 -0600
committerAndrey Grodzovsky2017-11-30 13:51:12 -0600
commitbc21168fa924d3fc4a000492e861f50a1a135b25 (patch)
tree3cd56f6c934e85f709e16db650504a341793ccad /tests
parentf71e95108de9a414226b0421ae2af99902ea28a5 (diff)
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amdgpu: Add explicit dependency test.
The test is as following: 1) Create context A & B 2) Send a command submission using context A which fires up a compute shader. 3) The shader wait a bit and then write a value to a memory location. 4) Send a command submission using context B which writes another value to the same memory location, but having an explicit dependency on the first command submission. 5) Wait with the CPU for both submissions to finish and inspect the written value. Test passes if the value seen in the memory location after both submissions is from command B. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian K├Ânig <christian.koenig@amd.com>
Diffstat (limited to 'tests')
-rw-r--r--tests/amdgpu/amdgpu_test.c18
-rw-r--r--tests/amdgpu/basic_tests.c264
2 files changed, 282 insertions, 0 deletions
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 50da17ca..8fa3399a 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -49,6 +49,7 @@
49#include "CUnit/Basic.h" 49#include "CUnit/Basic.h"
50 50
51#include "amdgpu_test.h" 51#include "amdgpu_test.h"
52#include "amdgpu_internal.h"
52 53
53/* Test suit names */ 54/* Test suit names */
54#define BASIC_TESTS_STR "Basic Tests" 55#define BASIC_TESTS_STR "Basic Tests"
@@ -401,9 +402,20 @@ static int amdgpu_find_device(uint8_t bus, uint16_t dev)
401 402
402static void amdgpu_disable_suits() 403static void amdgpu_disable_suits()
403{ 404{
405 amdgpu_device_handle device_handle;
406 uint32_t major_version, minor_version, family_id;
404 int i; 407 int i;
405 int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]); 408 int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]);
406 409
410 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
411 &minor_version, &device_handle))
412 return;
413
414 family_id = device_handle->info.family_id;
415
416 if (amdgpu_device_deinitialize(device_handle))
417 return;
418
407 /* Set active status for suits based on their policies */ 419 /* Set active status for suits based on their policies */
408 for (i = 0; i < size; ++i) 420 for (i = 0; i < size; ++i)
409 if (amdgpu_set_suite_active(suites_active_stat[i].pName, 421 if (amdgpu_set_suite_active(suites_active_stat[i].pName,
@@ -420,6 +432,12 @@ static void amdgpu_disable_suits()
420 432
421 if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) 433 if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
422 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); 434 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
435
436
437 /* This test was ran on GFX8 and GFX9 only */
438 if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
439 if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE))
440 fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
423} 441}
424 442
425/* The main() function for setting up and running the tests. 443/* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index e7f48e39..a78cf521 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -50,6 +50,7 @@ static void amdgpu_command_submission_multi_fence(void);
50static void amdgpu_command_submission_sdma(void); 50static void amdgpu_command_submission_sdma(void);
51static void amdgpu_userptr_test(void); 51static void amdgpu_userptr_test(void);
52static void amdgpu_semaphore_test(void); 52static void amdgpu_semaphore_test(void);
53static void amdgpu_sync_dependency_test(void);
53 54
54static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); 55static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
55static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); 56static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -63,6 +64,7 @@ CU_TestInfo basic_tests[] = {
63 { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, 64 { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence },
64 { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, 65 { "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
65 { "SW semaphore Test", amdgpu_semaphore_test }, 66 { "SW semaphore Test", amdgpu_semaphore_test },
67 { "Sync dependency Test", amdgpu_sync_dependency_test },
66 CU_TEST_INFO_NULL, 68 CU_TEST_INFO_NULL,
67}; 69};
68#define BUFFER_SIZE (8 * 1024) 70#define BUFFER_SIZE (8 * 1024)
@@ -226,6 +228,60 @@ CU_TestInfo basic_tests[] = {
226 */ 228 */
227# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31) 229# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31)
228 230
231
232#define PKT3_CONTEXT_CONTROL 0x28
233#define CONTEXT_CONTROL_LOAD_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
234#define CONTEXT_CONTROL_LOAD_CE_RAM(x) (((unsigned)(x) & 0x1) << 28)
235#define CONTEXT_CONTROL_SHADOW_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
236
237#define PKT3_CLEAR_STATE 0x12
238
239#define PKT3_SET_SH_REG 0x76
240#define PACKET3_SET_SH_REG_START 0x00002c00
241
242#define PACKET3_DISPATCH_DIRECT 0x15
243
244
245/* gfx 8 */
246#define mmCOMPUTE_PGM_LO 0x2e0c
247#define mmCOMPUTE_PGM_RSRC1 0x2e12
248#define mmCOMPUTE_TMPRING_SIZE 0x2e18
249#define mmCOMPUTE_USER_DATA_0 0x2e40
250#define mmCOMPUTE_USER_DATA_1 0x2e41
251#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
252#define mmCOMPUTE_NUM_THREAD_X 0x2e07
253
254
255
256#define SWAP_32(num) ((num>>24)&0xff) | \
257 ((num<<8)&0xff0000) | \
258 ((num>>8)&0xff00) | \
259 ((num<<24)&0xff000000)
260
261
262/* Shader code
263 * void main()
264{
265
266 float x = some_input;
267 for (unsigned i = 0; i < 1000000; i++)
268 x = sin(x);
269
270 u[0] = 42u;
271}
272*/
273
274static uint32_t shader_bin[] = {
275 SWAP_32(0x800082be), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0x040085bf),
276 SWAP_32(0x02810281), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0xfcff84bf),
277 SWAP_32(0xff0083be), SWAP_32(0x00f00000), SWAP_32(0xc10082be), SWAP_32(0xaa02007e),
278 SWAP_32(0x000070e0), SWAP_32(0x00000080), SWAP_32(0x000081bf)
279};
280
281#define CODE_OFFSET 512
282#define DATA_OFFSET 1024
283
284
229int suite_basic_tests_init(void) 285int suite_basic_tests_init(void)
230{ 286{
231 struct amdgpu_gpu_info gpu_info = {0}; 287 struct amdgpu_gpu_info gpu_info = {0};
@@ -1386,3 +1442,211 @@ static void amdgpu_userptr_test(void)
1386 1442
1387 wait(NULL); 1443 wait(NULL);
1388} 1444}
1445
1446static void amdgpu_sync_dependency_test(void)
1447{
1448 amdgpu_context_handle context_handle[2];
1449 amdgpu_bo_handle ib_result_handle;
1450 void *ib_result_cpu;
1451 uint64_t ib_result_mc_address;
1452 struct amdgpu_cs_request ibs_request;
1453 struct amdgpu_cs_ib_info ib_info;
1454 struct amdgpu_cs_fence fence_status;
1455 uint32_t expired;
1456 int i, j, r, instance;
1457 amdgpu_bo_list_handle bo_list;
1458 amdgpu_va_handle va_handle;
1459 static uint32_t *ptr;
1460 uint64_t seq_no;
1461
1462 CU_ASSERT_EQUAL(r, 0);
1463
1464 r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]);
1465 CU_ASSERT_EQUAL(r, 0);
1466 r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]);
1467 CU_ASSERT_EQUAL(r, 0);
1468
1469 r = amdgpu_bo_alloc_and_map(device_handle, 8192, 4096,
1470 AMDGPU_GEM_DOMAIN_GTT, 0,
1471 &ib_result_handle, &ib_result_cpu,
1472 &ib_result_mc_address, &va_handle);
1473 CU_ASSERT_EQUAL(r, 0);
1474
1475 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
1476 &bo_list);
1477 CU_ASSERT_EQUAL(r, 0);
1478
1479 ptr = ib_result_cpu;
1480 i = 0;
1481
1482 memcpy(ptr + CODE_OFFSET , shader_bin, sizeof(shader_bin));
1483
1484 /* Dispatch minimal init config and verify it's executed */
1485 ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
1486 ptr[i++] = 0x80000000;
1487 ptr[i++] = 0x80000000;
1488
1489 ptr[i++] = PACKET3(PKT3_CLEAR_STATE, 0);
1490 ptr[i++] = 0x80000000;
1491
1492
1493 /* Program compute regs */
1494 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
1495 ptr[i++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1496 ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 8;
1497 ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 40;
1498
1499
1500 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
1501 ptr[i++] = mmCOMPUTE_PGM_RSRC1 - PACKET3_SET_SH_REG_START;
1502 /*
1503 * 002c0040 COMPUTE_PGM_RSRC1 <- VGPRS = 0
1504 SGPRS = 1
1505 PRIORITY = 0
1506 FLOAT_MODE = 192 (0xc0)
1507 PRIV = 0
1508 DX10_CLAMP = 1
1509 DEBUG_MODE = 0
1510 IEEE_MODE = 0
1511 BULKY = 0
1512 CDBG_USER = 0
1513 *
1514 */
1515 ptr[i++] = 0x002c0040;
1516
1517
1518 /*
1519 * 00000010 COMPUTE_PGM_RSRC2 <- SCRATCH_EN = 0
1520 USER_SGPR = 8
1521 TRAP_PRESENT = 0
1522 TGID_X_EN = 0
1523 TGID_Y_EN = 0
1524 TGID_Z_EN = 0
1525 TG_SIZE_EN = 0
1526 TIDIG_COMP_CNT = 0
1527 EXCP_EN_MSB = 0
1528 LDS_SIZE = 0
1529 EXCP_EN = 0
1530 *
1531 */
1532 ptr[i++] = 0x00000010;
1533
1534
1535/*
1536 * 00000100 COMPUTE_TMPRING_SIZE <- WAVES = 256 (0x100)
1537 WAVESIZE = 0
1538 *
1539 */
1540 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
1541 ptr[i++] = mmCOMPUTE_TMPRING_SIZE - PACKET3_SET_SH_REG_START;
1542 ptr[i++] = 0x00000100;
1543
1544 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
1545 ptr[i++] = mmCOMPUTE_USER_DATA_0 - PACKET3_SET_SH_REG_START;
1546 ptr[i++] = 0xffffffff & (ib_result_mc_address + DATA_OFFSET * 4);
1547 ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
1548
1549 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
1550 ptr[i++] = mmCOMPUTE_RESOURCE_LIMITS - PACKET3_SET_SH_REG_START;
1551 ptr[i++] = 0;
1552
1553 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
1554 ptr[i++] = mmCOMPUTE_NUM_THREAD_X - PACKET3_SET_SH_REG_START;
1555 ptr[i++] = 1;
1556 ptr[i++] = 1;
1557 ptr[i++] = 1;
1558
1559
1560 /* Dispatch */
1561 ptr[i++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1562 ptr[i++] = 1;
1563 ptr[i++] = 1;
1564 ptr[i++] = 1;
1565 ptr[i++] = 0x00000045; /* DISPATCH DIRECT field */
1566
1567
1568 while (i & 7)
1569 ptr[i++] = 0xffff1000; /* type3 nop packet */
1570
1571 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
1572 ib_info.ib_mc_address = ib_result_mc_address;
1573 ib_info.size = i;
1574
1575 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
1576 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
1577 ibs_request.ring = 0;
1578 ibs_request.number_of_ibs = 1;
1579 ibs_request.ibs = &ib_info;
1580 ibs_request.resources = bo_list;
1581 ibs_request.fence_info.handle = NULL;
1582
1583 r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request, 1);
1584 CU_ASSERT_EQUAL(r, 0);
1585 seq_no = ibs_request.seq_no;
1586
1587
1588
1589 /* Prepare second command with dependency on the first */
1590 j = i;
1591 ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
1592 ptr[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
1593 ptr[i++] = 0xfffffffc & ib_result_mc_address + DATA_OFFSET * 4;
1594 ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32;
1595 ptr[i++] = 99;
1596
1597 while (i & 7)
1598 ptr[i++] = 0xffff1000; /* type3 nop packet */
1599
1600 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
1601 ib_info.ib_mc_address = ib_result_mc_address + j * 4;
1602 ib_info.size = i - j;
1603
1604 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
1605 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
1606 ibs_request.ring = 0;
1607 ibs_request.number_of_ibs = 1;
1608 ibs_request.ibs = &ib_info;
1609 ibs_request.resources = bo_list;
1610 ibs_request.fence_info.handle = NULL;
1611
1612 ibs_request.number_of_dependencies = 1;
1613
1614 ibs_request.dependencies = calloc(1, sizeof(*ibs_request.dependencies));
1615 ibs_request.dependencies[0].context = context_handle[1];
1616 ibs_request.dependencies[0].ip_instance = 0;
1617 ibs_request.dependencies[0].ring = 0;
1618 ibs_request.dependencies[0].fence = seq_no;
1619
1620
1621 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request, 1);
1622 CU_ASSERT_EQUAL(r, 0);
1623
1624
1625 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
1626 fence_status.context = context_handle[0];
1627 fence_status.ip_type = AMDGPU_HW_IP_GFX;
1628 fence_status.ip_instance = 0;
1629 fence_status.ring = 0;
1630 fence_status.fence = ibs_request.seq_no;
1631
1632 r = amdgpu_cs_query_fence_status(&fence_status,
1633 AMDGPU_TIMEOUT_INFINITE,0, &expired);
1634 CU_ASSERT_EQUAL(r, 0);
1635
1636 /* Expect the second command to wait for shader to complete */
1637 CU_ASSERT_EQUAL(ptr[DATA_OFFSET], 99);
1638
1639 r = amdgpu_bo_list_destroy(bo_list);
1640 CU_ASSERT_EQUAL(r, 0);
1641
1642 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
1643 ib_result_mc_address, 4096);
1644 CU_ASSERT_EQUAL(r, 0);
1645
1646 r = amdgpu_cs_ctx_free(context_handle[0]);
1647 CU_ASSERT_EQUAL(r, 0);
1648 r = amdgpu_cs_ctx_free(context_handle[1]);
1649 CU_ASSERT_EQUAL(r, 0);
1650
1651 free(ibs_request.dependencies);
1652}