diff options
-rw-r--r-- | include/drm/radeon_drm.h | 11 | ||||
-rw-r--r-- | radeon/radeon_surface.c | 625 | ||||
-rw-r--r-- | radeon/radeon_surface.h | 1 |
3 files changed, 624 insertions, 13 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index d1bebf5a..96ea5559 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h | |||
@@ -979,6 +979,10 @@ struct drm_radeon_cs { | |||
979 | #define RADEON_INFO_RING_WORKING 0x15 | 979 | #define RADEON_INFO_RING_WORKING 0x15 |
980 | /* SI tile mode array */ | 980 | /* SI tile mode array */ |
981 | #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 | 981 | #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 |
982 | /* query if CP DMA is supported on the compute ring */ | ||
983 | #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 | ||
984 | /* CIK macrotile mode array */ | ||
985 | #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 | ||
982 | 986 | ||
983 | struct drm_radeon_info { | 987 | struct drm_radeon_info { |
984 | uint32_t request; | 988 | uint32_t request; |
@@ -1004,6 +1008,13 @@ struct drm_radeon_info { | |||
1004 | #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 | 1008 | #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 |
1005 | #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 | 1009 | #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 |
1006 | 1010 | ||
1011 | #define CIK_TILE_MODE_COLOR_2D 14 | ||
1012 | #define CIK_TILE_MODE_COLOR_2D_SCANOUT 10 | ||
1013 | #define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0 | ||
1014 | #define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1 | ||
1015 | #define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2 | ||
1016 | #define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3 | ||
1017 | #define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4 | ||
1007 | #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 | 1018 | #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 |
1008 | 1019 | ||
1009 | #endif | 1020 | #endif |
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index c6aefc15..ea7c0900 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c | |||
@@ -26,6 +26,8 @@ | |||
26 | * Authors: | 26 | * Authors: |
27 | * Jérôme Glisse <jglisse@redhat.com> | 27 | * Jérôme Glisse <jglisse@redhat.com> |
28 | */ | 28 | */ |
29 | #include <stdbool.h> | ||
30 | #include <assert.h> | ||
29 | #include <errno.h> | 31 | #include <errno.h> |
30 | #include <stdio.h> | 32 | #include <stdio.h> |
31 | #include <stdlib.h> | 33 | #include <stdlib.h> |
@@ -96,6 +98,8 @@ struct radeon_hw_info { | |||
96 | unsigned allow_2d; | 98 | unsigned allow_2d; |
97 | /* apply to si */ | 99 | /* apply to si */ |
98 | uint32_t tile_mode_array[32]; | 100 | uint32_t tile_mode_array[32]; |
101 | /* apply to cik */ | ||
102 | uint32_t macrotile_mode_array[16]; | ||
99 | }; | 103 | }; |
100 | 104 | ||
101 | struct radeon_surface_manager { | 105 | struct radeon_surface_manager { |
@@ -1383,16 +1387,10 @@ static int si_surface_sanity(struct radeon_surface_manager *surf_man, | |||
1383 | break; | 1387 | break; |
1384 | case RADEON_SURF_MODE_1D: | 1388 | case RADEON_SURF_MODE_1D: |
1385 | if (surf->flags & RADEON_SURF_SBUFFER) { | 1389 | if (surf->flags & RADEON_SURF_SBUFFER) { |
1386 | if (surf_man->family >= CHIP_BONAIRE) | 1390 | *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; |
1387 | *stencil_tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; | ||
1388 | else | ||
1389 | *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; | ||
1390 | } | 1391 | } |
1391 | if (surf->flags & RADEON_SURF_ZBUFFER) { | 1392 | if (surf->flags & RADEON_SURF_ZBUFFER) { |
1392 | if (surf_man->family >= CHIP_BONAIRE) | 1393 | *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; |
1393 | *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; | ||
1394 | else | ||
1395 | *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; | ||
1396 | } else if (surf->flags & RADEON_SURF_SCANOUT) { | 1394 | } else if (surf->flags & RADEON_SURF_SCANOUT) { |
1397 | *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; | 1395 | *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; |
1398 | } else { | 1396 | } else { |
@@ -1660,10 +1658,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, | |||
1660 | tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; | 1658 | tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; |
1661 | break; | 1659 | break; |
1662 | case SI_TILE_MODE_DEPTH_STENCIL_2D: | 1660 | case SI_TILE_MODE_DEPTH_STENCIL_2D: |
1663 | if (surf_man->family >= CHIP_BONAIRE) | 1661 | tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; |
1664 | tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; | ||
1665 | else | ||
1666 | tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; | ||
1667 | break; | 1662 | break; |
1668 | default: | 1663 | default: |
1669 | return -EINVAL; | 1664 | return -EINVAL; |
@@ -1792,6 +1787,604 @@ static int si_surface_best(struct radeon_surface_manager *surf_man, | |||
1792 | 1787 | ||
1793 | 1788 | ||
1794 | /* =========================================================================== | 1789 | /* =========================================================================== |
1790 | * Sea Islands family | ||
1791 | */ | ||
1792 | #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f) | ||
1793 | #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0 | ||
1794 | #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4 | ||
1795 | #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5 | ||
1796 | #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6 | ||
1797 | #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7 | ||
1798 | #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8 | ||
1799 | #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9 | ||
1800 | #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10 | ||
1801 | #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11 | ||
1802 | #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12 | ||
1803 | #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13 | ||
1804 | #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14 | ||
1805 | #define CIK__GB_TILE_MODE__TILE_SPLIT(x) (((x) >> 11) & 0x7) | ||
1806 | #define CIK__TILE_SPLIT__64B 0 | ||
1807 | #define CIK__TILE_SPLIT__128B 1 | ||
1808 | #define CIK__TILE_SPLIT__256B 2 | ||
1809 | #define CIK__TILE_SPLIT__512B 3 | ||
1810 | #define CIK__TILE_SPLIT__1024B 4 | ||
1811 | #define CIK__TILE_SPLIT__2048B 5 | ||
1812 | #define CIK__TILE_SPLIT__4096B 6 | ||
1813 | #define CIK__GB_TILE_MODE__SAMPLE_SPLIT(x) (((x) >> 25) & 0x3) | ||
1814 | #define CIK__SAMPLE_SPLIT__1 0 | ||
1815 | #define CIK__SAMPLE_SPLIT__2 1 | ||
1816 | #define CIK__SAMPLE_SPLIT__4 2 | ||
1817 | #define CIK__SAMPLE_SPLIT__8 3 | ||
1818 | #define CIK__GB_MACROTILE_MODE__BANK_WIDTH(x) ((x) & 0x3) | ||
1819 | #define CIK__BANK_WIDTH__1 0 | ||
1820 | #define CIK__BANK_WIDTH__2 1 | ||
1821 | #define CIK__BANK_WIDTH__4 2 | ||
1822 | #define CIK__BANK_WIDTH__8 3 | ||
1823 | #define CIK__GB_MACROTILE_MODE__BANK_HEIGHT(x) (((x) >> 2) & 0x3) | ||
1824 | #define CIK__BANK_HEIGHT__1 0 | ||
1825 | #define CIK__BANK_HEIGHT__2 1 | ||
1826 | #define CIK__BANK_HEIGHT__4 2 | ||
1827 | #define CIK__BANK_HEIGHT__8 3 | ||
1828 | #define CIK__GB_MACROTILE_MODE__MACRO_TILE_ASPECT(x) (((x) >> 4) & 0x3) | ||
1829 | #define CIK__MACRO_TILE_ASPECT__1 0 | ||
1830 | #define CIK__MACRO_TILE_ASPECT__2 1 | ||
1831 | #define CIK__MACRO_TILE_ASPECT__4 2 | ||
1832 | #define CIK__MACRO_TILE_ASPECT__8 3 | ||
1833 | #define CIK__GB_MACROTILE_MODE__NUM_BANKS(x) (((x) >> 6) & 0x3) | ||
1834 | #define CIK__NUM_BANKS__2_BANK 0 | ||
1835 | #define CIK__NUM_BANKS__4_BANK 1 | ||
1836 | #define CIK__NUM_BANKS__8_BANK 2 | ||
1837 | #define CIK__NUM_BANKS__16_BANK 3 | ||
1838 | |||
1839 | |||
1840 | static void cik_get_2d_params(struct radeon_surface_manager *surf_man, | ||
1841 | unsigned bpe, unsigned nsamples, bool is_color, | ||
1842 | unsigned tile_mode, | ||
1843 | uint32_t *num_pipes, | ||
1844 | uint32_t *tile_split_ptr, | ||
1845 | uint32_t *num_banks, | ||
1846 | uint32_t *macro_tile_aspect, | ||
1847 | uint32_t *bank_w, | ||
1848 | uint32_t *bank_h) | ||
1849 | { | ||
1850 | uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; | ||
1851 | unsigned tileb_1x, tileb; | ||
1852 | unsigned gb_macrotile_mode; | ||
1853 | unsigned macrotile_index; | ||
1854 | unsigned tile_split, sample_split; | ||
1855 | |||
1856 | if (num_pipes) { | ||
1857 | switch (CIK__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) { | ||
1858 | case CIK__PIPE_CONFIG__ADDR_SURF_P2: | ||
1859 | default: | ||
1860 | *num_pipes = 2; | ||
1861 | break; | ||
1862 | case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16: | ||
1863 | case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16: | ||
1864 | case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32: | ||
1865 | case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32: | ||
1866 | *num_pipes = 4; | ||
1867 | break; | ||
1868 | case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16: | ||
1869 | case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16: | ||
1870 | case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16: | ||
1871 | case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16: | ||
1872 | case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16: | ||
1873 | case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32: | ||
1874 | case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32: | ||
1875 | *num_pipes = 8; | ||
1876 | break; | ||
1877 | } | ||
1878 | } | ||
1879 | switch (CIK__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) { | ||
1880 | default: | ||
1881 | case CIK__TILE_SPLIT__64B: | ||
1882 | tile_split = 64; | ||
1883 | break; | ||
1884 | case CIK__TILE_SPLIT__128B: | ||
1885 | tile_split = 128; | ||
1886 | break; | ||
1887 | case CIK__TILE_SPLIT__256B: | ||
1888 | tile_split = 256; | ||
1889 | break; | ||
1890 | case CIK__TILE_SPLIT__512B: | ||
1891 | tile_split = 512; | ||
1892 | break; | ||
1893 | case CIK__TILE_SPLIT__1024B: | ||
1894 | tile_split = 1024; | ||
1895 | break; | ||
1896 | case CIK__TILE_SPLIT__2048B: | ||
1897 | tile_split = 2048; | ||
1898 | break; | ||
1899 | case CIK__TILE_SPLIT__4096B: | ||
1900 | tile_split = 4096; | ||
1901 | break; | ||
1902 | } | ||
1903 | switch (CIK__GB_TILE_MODE__SAMPLE_SPLIT(gb_tile_mode)) { | ||
1904 | default: | ||
1905 | case CIK__SAMPLE_SPLIT__1: | ||
1906 | sample_split = 1; | ||
1907 | break; | ||
1908 | case CIK__SAMPLE_SPLIT__2: | ||
1909 | sample_split = 1; | ||
1910 | break; | ||
1911 | case CIK__SAMPLE_SPLIT__4: | ||
1912 | sample_split = 4; | ||
1913 | break; | ||
1914 | case CIK__SAMPLE_SPLIT__8: | ||
1915 | sample_split = 8; | ||
1916 | break; | ||
1917 | } | ||
1918 | |||
1919 | /* Adjust the tile split. */ | ||
1920 | tileb_1x = 8 * 8 * bpe; | ||
1921 | if (is_color) { | ||
1922 | tile_split = MAX2(256, sample_split * tileb_1x); | ||
1923 | } | ||
1924 | tile_split = MIN2(surf_man->hw_info.row_size, tile_split); | ||
1925 | |||
1926 | /* Determine the macrotile index. */ | ||
1927 | tileb = MIN2(tile_split, nsamples * tileb_1x); | ||
1928 | |||
1929 | for (macrotile_index = 0; tileb > 64; macrotile_index++) { | ||
1930 | tileb >>= 1; | ||
1931 | } | ||
1932 | gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index]; | ||
1933 | |||
1934 | if (tile_split_ptr) { | ||
1935 | *tile_split_ptr = tile_split; | ||
1936 | } | ||
1937 | if (num_banks) { | ||
1938 | switch (CIK__GB_MACROTILE_MODE__NUM_BANKS(gb_macrotile_mode)) { | ||
1939 | default: | ||
1940 | case CIK__NUM_BANKS__2_BANK: | ||
1941 | *num_banks = 2; | ||
1942 | break; | ||
1943 | case CIK__NUM_BANKS__4_BANK: | ||
1944 | *num_banks = 4; | ||
1945 | break; | ||
1946 | case CIK__NUM_BANKS__8_BANK: | ||
1947 | *num_banks = 8; | ||
1948 | break; | ||
1949 | case CIK__NUM_BANKS__16_BANK: | ||
1950 | *num_banks = 16; | ||
1951 | break; | ||
1952 | } | ||
1953 | } | ||
1954 | if (macro_tile_aspect) { | ||
1955 | switch (CIK__GB_MACROTILE_MODE__MACRO_TILE_ASPECT(gb_macrotile_mode)) { | ||
1956 | default: | ||
1957 | case CIK__MACRO_TILE_ASPECT__1: | ||
1958 | *macro_tile_aspect = 1; | ||
1959 | break; | ||
1960 | case CIK__MACRO_TILE_ASPECT__2: | ||
1961 | *macro_tile_aspect = 2; | ||
1962 | break; | ||
1963 | case CIK__MACRO_TILE_ASPECT__4: | ||
1964 | *macro_tile_aspect = 4; | ||
1965 | break; | ||
1966 | case CIK__MACRO_TILE_ASPECT__8: | ||
1967 | *macro_tile_aspect = 8; | ||
1968 | break; | ||
1969 | } | ||
1970 | } | ||
1971 | if (bank_w) { | ||
1972 | switch (CIK__GB_MACROTILE_MODE__BANK_WIDTH(gb_macrotile_mode)) { | ||
1973 | default: | ||
1974 | case CIK__BANK_WIDTH__1: | ||
1975 | *bank_w = 1; | ||
1976 | break; | ||
1977 | case CIK__BANK_WIDTH__2: | ||
1978 | *bank_w = 2; | ||
1979 | break; | ||
1980 | case CIK__BANK_WIDTH__4: | ||
1981 | *bank_w = 4; | ||
1982 | break; | ||
1983 | case CIK__BANK_WIDTH__8: | ||
1984 | *bank_w = 8; | ||
1985 | break; | ||
1986 | } | ||
1987 | } | ||
1988 | if (bank_h) { | ||
1989 | switch (CIK__GB_MACROTILE_MODE__BANK_HEIGHT(gb_macrotile_mode)) { | ||
1990 | default: | ||
1991 | case CIK__BANK_HEIGHT__1: | ||
1992 | *bank_h = 1; | ||
1993 | break; | ||
1994 | case CIK__BANK_HEIGHT__2: | ||
1995 | *bank_h = 2; | ||
1996 | break; | ||
1997 | case CIK__BANK_HEIGHT__4: | ||
1998 | *bank_h = 4; | ||
1999 | break; | ||
2000 | case CIK__BANK_HEIGHT__8: | ||
2001 | *bank_h = 8; | ||
2002 | break; | ||
2003 | } | ||
2004 | } | ||
2005 | } | ||
2006 | |||
2007 | static int cik_init_hw_info(struct radeon_surface_manager *surf_man) | ||
2008 | { | ||
2009 | uint32_t tiling_config; | ||
2010 | drmVersionPtr version; | ||
2011 | int r; | ||
2012 | |||
2013 | r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, | ||
2014 | &tiling_config); | ||
2015 | if (r) { | ||
2016 | return r; | ||
2017 | } | ||
2018 | |||
2019 | surf_man->hw_info.allow_2d = 0; | ||
2020 | version = drmGetVersion(surf_man->fd); | ||
2021 | if (version && version->version_minor >= 35) { | ||
2022 | if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_array) && | ||
2023 | !radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_mode_array)) { | ||
2024 | surf_man->hw_info.allow_2d = 1; | ||
2025 | } | ||
2026 | } | ||
2027 | drmFreeVersion(version); | ||
2028 | |||
2029 | switch (tiling_config & 0xf) { | ||
2030 | case 0: | ||
2031 | surf_man->hw_info.num_pipes = 1; | ||
2032 | break; | ||
2033 | case 1: | ||
2034 | surf_man->hw_info.num_pipes = 2; | ||
2035 | break; | ||
2036 | case 2: | ||
2037 | surf_man->hw_info.num_pipes = 4; | ||
2038 | break; | ||
2039 | case 3: | ||
2040 | surf_man->hw_info.num_pipes = 8; | ||
2041 | break; | ||
2042 | default: | ||
2043 | surf_man->hw_info.num_pipes = 8; | ||
2044 | surf_man->hw_info.allow_2d = 0; | ||
2045 | break; | ||
2046 | } | ||
2047 | |||
2048 | switch ((tiling_config & 0xf0) >> 4) { | ||
2049 | case 0: | ||
2050 | surf_man->hw_info.num_banks = 4; | ||
2051 | break; | ||
2052 | case 1: | ||
2053 | surf_man->hw_info.num_banks = 8; | ||
2054 | break; | ||
2055 | case 2: | ||
2056 | surf_man->hw_info.num_banks = 16; | ||
2057 | break; | ||
2058 | default: | ||
2059 | surf_man->hw_info.num_banks = 8; | ||
2060 | surf_man->hw_info.allow_2d = 0; | ||
2061 | break; | ||
2062 | } | ||
2063 | |||
2064 | switch ((tiling_config & 0xf00) >> 8) { | ||
2065 | case 0: | ||
2066 | surf_man->hw_info.group_bytes = 256; | ||
2067 | break; | ||
2068 | case 1: | ||
2069 | surf_man->hw_info.group_bytes = 512; | ||
2070 | break; | ||
2071 | default: | ||
2072 | surf_man->hw_info.group_bytes = 256; | ||
2073 | surf_man->hw_info.allow_2d = 0; | ||
2074 | break; | ||
2075 | } | ||
2076 | |||
2077 | switch ((tiling_config & 0xf000) >> 12) { | ||
2078 | case 0: | ||
2079 | surf_man->hw_info.row_size = 1024; | ||
2080 | break; | ||
2081 | case 1: | ||
2082 | surf_man->hw_info.row_size = 2048; | ||
2083 | break; | ||
2084 | case 2: | ||
2085 | surf_man->hw_info.row_size = 4096; | ||
2086 | break; | ||
2087 | default: | ||
2088 | surf_man->hw_info.row_size = 4096; | ||
2089 | surf_man->hw_info.allow_2d = 0; | ||
2090 | break; | ||
2091 | } | ||
2092 | return 0; | ||
2093 | } | ||
2094 | |||
2095 | static int cik_surface_sanity(struct radeon_surface_manager *surf_man, | ||
2096 | struct radeon_surface *surf, | ||
2097 | unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode) | ||
2098 | { | ||
2099 | /* check surface dimension */ | ||
2100 | if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { | ||
2101 | return -EINVAL; | ||
2102 | } | ||
2103 | |||
2104 | /* check mipmap last_level */ | ||
2105 | if (surf->last_level > 15) { | ||
2106 | return -EINVAL; | ||
2107 | } | ||
2108 | |||
2109 | /* force 1d on kernel that can't do 2d */ | ||
2110 | if (mode > RADEON_SURF_MODE_1D && | ||
2111 | (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { | ||
2112 | if (surf->nsamples > 1) { | ||
2113 | fprintf(stderr, "radeon: Cannot use 1D tiling for an MSAA surface (%i).\n", __LINE__); | ||
2114 | return -EFAULT; | ||
2115 | } | ||
2116 | mode = RADEON_SURF_MODE_1D; | ||
2117 | surf->flags = RADEON_SURF_CLR(surf->flags, MODE); | ||
2118 | surf->flags |= RADEON_SURF_SET(mode, MODE); | ||
2119 | } | ||
2120 | |||
2121 | if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) { | ||
2122 | return -EINVAL; | ||
2123 | } | ||
2124 | |||
2125 | if (!surf->tile_split) { | ||
2126 | /* default value */ | ||
2127 | surf->mtilea = 1; | ||
2128 | surf->bankw = 1; | ||
2129 | surf->bankw = 1; | ||
2130 | surf->tile_split = 64; | ||
2131 | surf->stencil_tile_split = 64; | ||
2132 | } | ||
2133 | |||
2134 | switch (mode) { | ||
2135 | case RADEON_SURF_MODE_2D: { | ||
2136 | if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) { | ||
2137 | switch (surf->nsamples) { | ||
2138 | case 1: | ||
2139 | *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64; | ||
2140 | break; | ||
2141 | case 2: | ||
2142 | case 4: | ||
2143 | *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128; | ||
2144 | break; | ||
2145 | case 8: | ||
2146 | *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256; | ||
2147 | break; | ||
2148 | default: | ||
2149 | return -EINVAL; | ||
2150 | } | ||
2151 | |||
2152 | if (surf->flags & RADEON_SURF_SBUFFER) { | ||
2153 | *stencil_tile_mode = *tile_mode; | ||
2154 | |||
2155 | cik_get_2d_params(surf_man, 1, surf->nsamples, false, | ||
2156 | *stencil_tile_mode, NULL, | ||
2157 | &surf->stencil_tile_split, | ||
2158 | NULL, NULL, NULL, NULL); | ||
2159 | } | ||
2160 | } else if (surf->flags & RADEON_SURF_SCANOUT) { | ||
2161 | *tile_mode = CIK_TILE_MODE_COLOR_2D_SCANOUT; | ||
2162 | } else { | ||
2163 | *tile_mode = CIK_TILE_MODE_COLOR_2D; | ||
2164 | } | ||
2165 | |||
2166 | /* retrieve tiling mode values */ | ||
2167 | cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, | ||
2168 | !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), *tile_mode, | ||
2169 | NULL, &surf->tile_split, NULL, &surf->mtilea, | ||
2170 | &surf->bankw, &surf->bankh); | ||
2171 | break; | ||
2172 | } | ||
2173 | case RADEON_SURF_MODE_1D: | ||
2174 | if (surf->flags & RADEON_SURF_SBUFFER) { | ||
2175 | *stencil_tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; | ||
2176 | } | ||
2177 | if (surf->flags & RADEON_SURF_ZBUFFER) { | ||
2178 | *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; | ||
2179 | } else if (surf->flags & RADEON_SURF_SCANOUT) { | ||
2180 | *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; | ||
2181 | } else { | ||
2182 | *tile_mode = SI_TILE_MODE_COLOR_1D; | ||
2183 | } | ||
2184 | break; | ||
2185 | case RADEON_SURF_MODE_LINEAR_ALIGNED: | ||
2186 | default: | ||
2187 | *tile_mode = SI_TILE_MODE_COLOR_LINEAR_ALIGNED; | ||
2188 | } | ||
2189 | |||
2190 | return 0; | ||
2191 | } | ||
2192 | |||
2193 | static int cik_surface_init_2d(struct radeon_surface_manager *surf_man, | ||
2194 | struct radeon_surface *surf, | ||
2195 | struct radeon_surface_level *level, | ||
2196 | unsigned bpe, unsigned tile_mode, | ||
2197 | unsigned tile_split, | ||
2198 | unsigned num_pipes, unsigned num_banks, | ||
2199 | uint64_t offset, | ||
2200 | unsigned start_level) | ||
2201 | { | ||
2202 | uint64_t aligned_offset = offset; | ||
2203 | unsigned tilew, tileh, tileb_1x, tileb; | ||
2204 | unsigned mtilew, mtileh, mtileb; | ||
2205 | unsigned slice_pt; | ||
2206 | unsigned i; | ||
2207 | |||
2208 | /* compute tile values */ | ||
2209 | tilew = 8; | ||
2210 | tileh = 8; | ||
2211 | tileb_1x = tilew * tileh * bpe; | ||
2212 | |||
2213 | tile_split = MIN2(surf_man->hw_info.row_size, tile_split); | ||
2214 | |||
2215 | tileb = surf->nsamples * tileb_1x; | ||
2216 | |||
2217 | /* slices per tile */ | ||
2218 | slice_pt = 1; | ||
2219 | if (tileb > tile_split) { | ||
2220 | slice_pt = tileb / tile_split; | ||
2221 | tileb = tileb / slice_pt; | ||
2222 | } | ||
2223 | |||
2224 | /* macro tile width & height */ | ||
2225 | mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea; | ||
2226 | mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea; | ||
2227 | |||
2228 | /* macro tile bytes */ | ||
2229 | mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb; | ||
2230 | |||
2231 | if (start_level <= 1) { | ||
2232 | unsigned alignment = MAX2(256, mtileb); | ||
2233 | surf->bo_alignment = MAX2(surf->bo_alignment, alignment); | ||
2234 | |||
2235 | if (aligned_offset) { | ||
2236 | aligned_offset = ALIGN(aligned_offset, alignment); | ||
2237 | } | ||
2238 | } | ||
2239 | |||
2240 | /* build mipmap tree */ | ||
2241 | for (i = start_level; i <= surf->last_level; i++) { | ||
2242 | level[i].mode = RADEON_SURF_MODE_2D; | ||
2243 | si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset); | ||
2244 | if (level[i].mode == RADEON_SURF_MODE_1D) { | ||
2245 | switch (tile_mode) { | ||
2246 | case CIK_TILE_MODE_COLOR_2D: | ||
2247 | tile_mode = SI_TILE_MODE_COLOR_1D; | ||
2248 | break; | ||
2249 | case CIK_TILE_MODE_COLOR_2D_SCANOUT: | ||
2250 | tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; | ||
2251 | break; | ||
2252 | case CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64: | ||
2253 | case CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128: | ||
2254 | case CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256: | ||
2255 | case CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512: | ||
2256 | case CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE: | ||
2257 | tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; | ||
2258 | break; | ||
2259 | default: | ||
2260 | return -EINVAL; | ||
2261 | } | ||
2262 | return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); | ||
2263 | } | ||
2264 | /* level0 and first mipmap need to have alignment */ | ||
2265 | aligned_offset = offset = surf->bo_size; | ||
2266 | if (i == 0) { | ||
2267 | aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); | ||
2268 | } | ||
2269 | if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { | ||
2270 | if (surf->level == level) { | ||
2271 | surf->tiling_index[i] = tile_mode; | ||
2272 | /* it's ok because stencil is done after */ | ||
2273 | surf->stencil_tiling_index[i] = tile_mode; | ||
2274 | } else { | ||
2275 | surf->stencil_tiling_index[i] = tile_mode; | ||
2276 | } | ||
2277 | } | ||
2278 | } | ||
2279 | return 0; | ||
2280 | } | ||
2281 | |||
2282 | static int cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, | ||
2283 | struct radeon_surface *surf, | ||
2284 | unsigned tile_mode, unsigned stencil_tile_mode) | ||
2285 | { | ||
2286 | int r; | ||
2287 | uint32_t num_pipes, num_banks; | ||
2288 | |||
2289 | cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, | ||
2290 | !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), tile_mode, | ||
2291 | &num_pipes, NULL, &num_banks, NULL, NULL, NULL); | ||
2292 | |||
2293 | r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, | ||
2294 | surf->tile_split, num_pipes, num_banks, 0, 0); | ||
2295 | if (r) { | ||
2296 | return r; | ||
2297 | } | ||
2298 | |||
2299 | if (surf->flags & RADEON_SURF_SBUFFER) { | ||
2300 | r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, | ||
2301 | surf->stencil_tile_split, num_pipes, num_banks, | ||
2302 | surf->bo_size, 0); | ||
2303 | surf->stencil_offset = surf->stencil_level[0].offset; | ||
2304 | } | ||
2305 | return r; | ||
2306 | } | ||
2307 | |||
2308 | static int cik_surface_init(struct radeon_surface_manager *surf_man, | ||
2309 | struct radeon_surface *surf) | ||
2310 | { | ||
2311 | unsigned mode, tile_mode, stencil_tile_mode; | ||
2312 | int r; | ||
2313 | |||
2314 | /* MSAA surfaces support the 2D mode only. */ | ||
2315 | if (surf->nsamples > 1) { | ||
2316 | surf->flags = RADEON_SURF_CLR(surf->flags, MODE); | ||
2317 | surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); | ||
2318 | } | ||
2319 | |||
2320 | /* tiling mode */ | ||
2321 | mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; | ||
2322 | |||
2323 | if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { | ||
2324 | /* zbuffer only support 1D or 2D tiled surface */ | ||
2325 | switch (mode) { | ||
2326 | case RADEON_SURF_MODE_1D: | ||
2327 | case RADEON_SURF_MODE_2D: | ||
2328 | break; | ||
2329 | default: | ||
2330 | mode = RADEON_SURF_MODE_1D; | ||
2331 | surf->flags = RADEON_SURF_CLR(surf->flags, MODE); | ||
2332 | surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); | ||
2333 | break; | ||
2334 | } | ||
2335 | } | ||
2336 | |||
2337 | r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); | ||
2338 | if (r) { | ||
2339 | return r; | ||
2340 | } | ||
2341 | |||
2342 | surf->stencil_offset = 0; | ||
2343 | surf->bo_alignment = 0; | ||
2344 | |||
2345 | /* check tiling mode */ | ||
2346 | switch (mode) { | ||
2347 | case RADEON_SURF_MODE_LINEAR: | ||
2348 | r = r6_surface_init_linear(surf_man, surf, 0, 0); | ||
2349 | break; | ||
2350 | case RADEON_SURF_MODE_LINEAR_ALIGNED: | ||
2351 | r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); | ||
2352 | break; | ||
2353 | case RADEON_SURF_MODE_1D: | ||
2354 | r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); | ||
2355 | break; | ||
2356 | case RADEON_SURF_MODE_2D: | ||
2357 | r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); | ||
2358 | break; | ||
2359 | default: | ||
2360 | return -EINVAL; | ||
2361 | } | ||
2362 | return r; | ||
2363 | } | ||
2364 | |||
2365 | /* | ||
2366 | * depending on surface | ||
2367 | */ | ||
2368 | static int cik_surface_best(struct radeon_surface_manager *surf_man, | ||
2369 | struct radeon_surface *surf) | ||
2370 | { | ||
2371 | unsigned mode, tile_mode, stencil_tile_mode; | ||
2372 | |||
2373 | /* tiling mode */ | ||
2374 | mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; | ||
2375 | |||
2376 | if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) && | ||
2377 | !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) { | ||
2378 | /* depth/stencil force 1d tiling for old mesa */ | ||
2379 | surf->flags = RADEON_SURF_CLR(surf->flags, MODE); | ||
2380 | surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); | ||
2381 | } | ||
2382 | |||
2383 | return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); | ||
2384 | } | ||
2385 | |||
2386 | |||
2387 | /* =========================================================================== | ||
1795 | * public API | 2388 | * public API |
1796 | */ | 2389 | */ |
1797 | struct radeon_surface_manager *radeon_surface_manager_new(int fd) | 2390 | struct radeon_surface_manager *radeon_surface_manager_new(int fd) |
@@ -1822,12 +2415,18 @@ struct radeon_surface_manager *radeon_surface_manager_new(int fd) | |||
1822 | } | 2415 | } |
1823 | surf_man->surface_init = &eg_surface_init; | 2416 | surf_man->surface_init = &eg_surface_init; |
1824 | surf_man->surface_best = &eg_surface_best; | 2417 | surf_man->surface_best = &eg_surface_best; |
1825 | } else { | 2418 | } else if (surf_man->family < CHIP_BONAIRE) { |
1826 | if (si_init_hw_info(surf_man)) { | 2419 | if (si_init_hw_info(surf_man)) { |
1827 | goto out_err; | 2420 | goto out_err; |
1828 | } | 2421 | } |
1829 | surf_man->surface_init = &si_surface_init; | 2422 | surf_man->surface_init = &si_surface_init; |
1830 | surf_man->surface_best = &si_surface_best; | 2423 | surf_man->surface_best = &si_surface_best; |
2424 | } else { | ||
2425 | if (cik_init_hw_info(surf_man)) { | ||
2426 | goto out_err; | ||
2427 | } | ||
2428 | surf_man->surface_init = &cik_surface_init; | ||
2429 | surf_man->surface_best = &cik_surface_best; | ||
1831 | } | 2430 | } |
1832 | 2431 | ||
1833 | return surf_man; | 2432 | return surf_man; |
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h index bbed56f8..af7cab67 100644 --- a/radeon/radeon_surface.h +++ b/radeon/radeon_surface.h | |||
@@ -54,6 +54,7 @@ | |||
54 | #define RADEON_SURF_SCANOUT (1 << 16) | 54 | #define RADEON_SURF_SCANOUT (1 << 16) |
55 | #define RADEON_SURF_ZBUFFER (1 << 17) | 55 | #define RADEON_SURF_ZBUFFER (1 << 17) |
56 | #define RADEON_SURF_SBUFFER (1 << 18) | 56 | #define RADEON_SURF_SBUFFER (1 << 18) |
57 | #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) | ||
57 | #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) | 58 | #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) |
58 | #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) | 59 | #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) |
59 | #define RADEON_SURF_FMASK (1 << 21) | 60 | #define RADEON_SURF_FMASK (1 << 21) |