diff options
Diffstat (limited to 'etnaviv/etnaviv_drm.h')
-rw-r--r-- | etnaviv/etnaviv_drm.h | 58 |
1 files changed, 57 insertions, 1 deletions
diff --git a/etnaviv/etnaviv_drm.h b/etnaviv/etnaviv_drm.h index 2584c1cc..0d5c49dc 100644 --- a/etnaviv/etnaviv_drm.h +++ b/etnaviv/etnaviv_drm.h | |||
@@ -1,3 +1,4 @@ | |||
1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ | ||
1 | /* | 2 | /* |
2 | * Copyright (C) 2015 Etnaviv Project | 3 | * Copyright (C) 2015 Etnaviv Project |
3 | * | 4 | * |
@@ -54,6 +55,12 @@ struct drm_etnaviv_timespec { | |||
54 | #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 | 55 | #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 |
55 | #define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 | 56 | #define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 |
56 | #define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 | 57 | #define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 |
58 | #define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a | ||
59 | #define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b | ||
60 | #define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c | ||
61 | #define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d | ||
62 | #define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e | ||
63 | #define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f | ||
57 | 64 | ||
58 | #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 | 65 | #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 |
59 | #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 | 66 | #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 |
@@ -150,10 +157,29 @@ struct drm_etnaviv_gem_submit_bo { | |||
150 | __u64 presumed; /* in/out, presumed buffer address */ | 157 | __u64 presumed; /* in/out, presumed buffer address */ |
151 | }; | 158 | }; |
152 | 159 | ||
160 | /* performance monitor request (pmr) */ | ||
161 | #define ETNA_PM_PROCESS_PRE 0x0001 | ||
162 | #define ETNA_PM_PROCESS_POST 0x0002 | ||
163 | struct drm_etnaviv_gem_submit_pmr { | ||
164 | __u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */ | ||
165 | __u8 domain; /* in, pm domain */ | ||
166 | __u8 pad; | ||
167 | __u16 signal; /* in, pm signal */ | ||
168 | __u32 sequence; /* in, sequence number */ | ||
169 | __u32 read_offset; /* in, offset from read_bo */ | ||
170 | __u32 read_idx; /* in, index of read_bo buffer */ | ||
171 | }; | ||
172 | |||
153 | /* Each cmdstream submit consists of a table of buffers involved, and | 173 | /* Each cmdstream submit consists of a table of buffers involved, and |
154 | * one or more cmdstream buffers. This allows for conditional execution | 174 | * one or more cmdstream buffers. This allows for conditional execution |
155 | * (context-restore), and IB buffers needed for per tile/bin draw cmds. | 175 | * (context-restore), and IB buffers needed for per tile/bin draw cmds. |
156 | */ | 176 | */ |
177 | #define ETNA_SUBMIT_NO_IMPLICIT 0x0001 | ||
178 | #define ETNA_SUBMIT_FENCE_FD_IN 0x0002 | ||
179 | #define ETNA_SUBMIT_FENCE_FD_OUT 0x0004 | ||
180 | #define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \ | ||
181 | ETNA_SUBMIT_FENCE_FD_IN | \ | ||
182 | ETNA_SUBMIT_FENCE_FD_OUT) | ||
157 | #define ETNA_PIPE_3D 0x00 | 183 | #define ETNA_PIPE_3D 0x00 |
158 | #define ETNA_PIPE_2D 0x01 | 184 | #define ETNA_PIPE_2D 0x01 |
159 | #define ETNA_PIPE_VG 0x02 | 185 | #define ETNA_PIPE_VG 0x02 |
@@ -167,6 +193,11 @@ struct drm_etnaviv_gem_submit { | |||
167 | __u64 bos; /* in, ptr to array of submit_bo's */ | 193 | __u64 bos; /* in, ptr to array of submit_bo's */ |
168 | __u64 relocs; /* in, ptr to array of submit_reloc's */ | 194 | __u64 relocs; /* in, ptr to array of submit_reloc's */ |
169 | __u64 stream; /* in, ptr to cmdstream */ | 195 | __u64 stream; /* in, ptr to cmdstream */ |
196 | __u32 flags; /* in, mask of ETNA_SUBMIT_x */ | ||
197 | __s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */ | ||
198 | __u64 pmrs; /* in, ptr to array of submit_pmr's */ | ||
199 | __u32 nr_pmrs; /* in, number of submit_pmr's */ | ||
200 | __u32 pad; | ||
170 | }; | 201 | }; |
171 | 202 | ||
172 | /* The normal way to synchronize with the GPU is just to CPU_PREP on | 203 | /* The normal way to synchronize with the GPU is just to CPU_PREP on |
@@ -202,6 +233,27 @@ struct drm_etnaviv_gem_wait { | |||
202 | struct drm_etnaviv_timespec timeout; /* in */ | 233 | struct drm_etnaviv_timespec timeout; /* in */ |
203 | }; | 234 | }; |
204 | 235 | ||
236 | /* | ||
237 | * Performance Monitor (PM): | ||
238 | */ | ||
239 | |||
240 | struct drm_etnaviv_pm_domain { | ||
241 | __u32 pipe; /* in */ | ||
242 | __u8 iter; /* in/out, select pm domain at index iter */ | ||
243 | __u8 id; /* out, id of domain */ | ||
244 | __u16 nr_signals; /* out, how many signals does this domain provide */ | ||
245 | char name[64]; /* out, name of domain */ | ||
246 | }; | ||
247 | |||
248 | struct drm_etnaviv_pm_signal { | ||
249 | __u32 pipe; /* in */ | ||
250 | __u8 domain; /* in, pm domain index */ | ||
251 | __u8 pad; | ||
252 | __u16 iter; /* in/out, select pm source at index iter */ | ||
253 | __u16 id; /* out, id of signal */ | ||
254 | char name[64]; /* out, name of domain */ | ||
255 | }; | ||
256 | |||
205 | #define DRM_ETNAVIV_GET_PARAM 0x00 | 257 | #define DRM_ETNAVIV_GET_PARAM 0x00 |
206 | /* placeholder: | 258 | /* placeholder: |
207 | #define DRM_ETNAVIV_SET_PARAM 0x01 | 259 | #define DRM_ETNAVIV_SET_PARAM 0x01 |
@@ -214,7 +266,9 @@ struct drm_etnaviv_gem_wait { | |||
214 | #define DRM_ETNAVIV_WAIT_FENCE 0x07 | 266 | #define DRM_ETNAVIV_WAIT_FENCE 0x07 |
215 | #define DRM_ETNAVIV_GEM_USERPTR 0x08 | 267 | #define DRM_ETNAVIV_GEM_USERPTR 0x08 |
216 | #define DRM_ETNAVIV_GEM_WAIT 0x09 | 268 | #define DRM_ETNAVIV_GEM_WAIT 0x09 |
217 | #define DRM_ETNAVIV_NUM_IOCTLS 0x0a | 269 | #define DRM_ETNAVIV_PM_QUERY_DOM 0x0a |
270 | #define DRM_ETNAVIV_PM_QUERY_SIG 0x0b | ||
271 | #define DRM_ETNAVIV_NUM_IOCTLS 0x0c | ||
218 | 272 | ||
219 | #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) | 273 | #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) |
220 | #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) | 274 | #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) |
@@ -225,6 +279,8 @@ struct drm_etnaviv_gem_wait { | |||
225 | #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) | 279 | #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) |
226 | #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) | 280 | #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) |
227 | #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) | 281 | #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) |
282 | #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain) | ||
283 | #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal) | ||
228 | 284 | ||
229 | #if defined(__cplusplus) | 285 | #if defined(__cplusplus) |
230 | } | 286 | } |