diff options
Diffstat (limited to 'include/drm/amdgpu_drm.h')
-rw-r--r-- | include/drm/amdgpu_drm.h | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 4c6e8c48..ff018182 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h | |||
@@ -53,6 +53,7 @@ extern "C" { | |||
53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
54 | #define DRM_AMDGPU_VM 0x13 | 54 | #define DRM_AMDGPU_VM 0x13 |
55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 | 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
56 | #define DRM_AMDGPU_SCHED 0x15 | ||
56 | 57 | ||
57 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | 58 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
58 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | 59 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
@@ -69,6 +70,7 @@ extern "C" { | |||
69 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) | 70 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
70 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) | 71 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
71 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) | 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) | ||
72 | 74 | ||
73 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | 75 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
74 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | 76 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 |
@@ -91,6 +93,8 @@ extern "C" { | |||
91 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | 93 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) |
92 | /* Flag that BO is always valid in this VM */ | 94 | /* Flag that BO is always valid in this VM */ |
93 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) | 95 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) |
96 | /* Flag that BO sharing will be explicitly synchronized */ | ||
97 | #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) | ||
94 | 98 | ||
95 | struct drm_amdgpu_gem_create_in { | 99 | struct drm_amdgpu_gem_create_in { |
96 | /** the requested memory size */ | 100 | /** the requested memory size */ |
@@ -166,13 +170,22 @@ union drm_amdgpu_bo_list { | |||
166 | /* unknown cause */ | 170 | /* unknown cause */ |
167 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | 171 | #define AMDGPU_CTX_UNKNOWN_RESET 3 |
168 | 172 | ||
173 | /* Context priority level */ | ||
174 | #define AMDGPU_CTX_PRIORITY_UNSET -2048 | ||
175 | #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 | ||
176 | #define AMDGPU_CTX_PRIORITY_LOW -512 | ||
177 | #define AMDGPU_CTX_PRIORITY_NORMAL 0 | ||
178 | /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ | ||
179 | #define AMDGPU_CTX_PRIORITY_HIGH 512 | ||
180 | #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 | ||
181 | |||
169 | struct drm_amdgpu_ctx_in { | 182 | struct drm_amdgpu_ctx_in { |
170 | /** AMDGPU_CTX_OP_* */ | 183 | /** AMDGPU_CTX_OP_* */ |
171 | __u32 op; | 184 | __u32 op; |
172 | /** For future use, no flags defined so far */ | 185 | /** For future use, no flags defined so far */ |
173 | __u32 flags; | 186 | __u32 flags; |
174 | __u32 ctx_id; | 187 | __u32 ctx_id; |
175 | __u32 _pad; | 188 | __s32 priority; |
176 | }; | 189 | }; |
177 | 190 | ||
178 | union drm_amdgpu_ctx_out { | 191 | union drm_amdgpu_ctx_out { |
@@ -216,6 +229,21 @@ union drm_amdgpu_vm { | |||
216 | struct drm_amdgpu_vm_out out; | 229 | struct drm_amdgpu_vm_out out; |
217 | }; | 230 | }; |
218 | 231 | ||
232 | /* sched ioctl */ | ||
233 | #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 | ||
234 | |||
235 | struct drm_amdgpu_sched_in { | ||
236 | /* AMDGPU_SCHED_OP_* */ | ||
237 | __u32 op; | ||
238 | __u32 fd; | ||
239 | __s32 priority; | ||
240 | __u32 flags; | ||
241 | }; | ||
242 | |||
243 | union drm_amdgpu_sched { | ||
244 | struct drm_amdgpu_sched_in in; | ||
245 | }; | ||
246 | |||
219 | /* | 247 | /* |
220 | * This is not a reliable API and you should expect it to fail for any | 248 | * This is not a reliable API and you should expect it to fail for any |
221 | * number of reasons and have fallback path that do not use userptr to | 249 | * number of reasons and have fallback path that do not use userptr to |
@@ -629,6 +657,7 @@ struct drm_amdgpu_cs_chunk_data { | |||
629 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | 657 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 |
630 | /* Number of VRAM page faults on CPU access. */ | 658 | /* Number of VRAM page faults on CPU access. */ |
631 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E | 659 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E |
660 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F | ||
632 | 661 | ||
633 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | 662 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 |
634 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | 663 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff |