aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat (limited to 'include/drm/i915_drm.h')
-rw-r--r--include/drm/i915_drm.h761
1 files changed, 761 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
new file mode 100644
index 00000000..75b0e1d5
--- /dev/null
+++ b/include/drm/i915_drm.h
@@ -0,0 +1,761 @@
1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30#include "drm.h"
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35
36/* Each region is a minimum of 16k, and there are at most 255 of them.
37 */
38#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40#define I915_LOG_MIN_TEX_REGION_SIZE 14
41
42typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64} drm_i915_init_t;
65
66typedef struct _drm_i915_sarea {
67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
72 int texAge;
73 int pf_enabled; /* is pageflipping allowed? */
74 int pf_active;
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
77 int width, height; /* screen size in pixels */
78
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
82
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
86
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
90
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation; /* 0, 90, 180 or 270 */
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
101
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
107
108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
116
117 /* fill out some space for old userspace triple buffer */
118 drm_handle_t unused_handle;
119 __u32 unused1, unused2, unused3;
120
121 /* buffer object handles for static buffers. May change
122 * over the lifetime of the client.
123 */
124 __u32 front_bo_handle;
125 __u32 back_bo_handle;
126 __u32 unused_bo_handle;
127 __u32 depth_bo_handle;
128
129} drm_i915_sarea_t;
130
131/* due to userspace building against these headers we need some compat here */
132#define planeA_x pipeA_x
133#define planeA_y pipeA_y
134#define planeA_w pipeA_w
135#define planeA_h pipeA_h
136#define planeB_x pipeB_x
137#define planeB_y pipeB_y
138#define planeB_w pipeB_w
139#define planeB_h pipeB_h
140
141/* Flags for perf_boxes
142 */
143#define I915_BOX_RING_EMPTY 0x1
144#define I915_BOX_FLIP 0x2
145#define I915_BOX_WAIT 0x4
146#define I915_BOX_TEXTURE_LOAD 0x8
147#define I915_BOX_LOST_CONTEXT 0x10
148
149/* I915 specific ioctls
150 * The device specific ioctl range is 0x40 to 0x79.
151 */
152#define DRM_I915_INIT 0x00
153#define DRM_I915_FLUSH 0x01
154#define DRM_I915_FLIP 0x02
155#define DRM_I915_BATCHBUFFER 0x03
156#define DRM_I915_IRQ_EMIT 0x04
157#define DRM_I915_IRQ_WAIT 0x05
158#define DRM_I915_GETPARAM 0x06
159#define DRM_I915_SETPARAM 0x07
160#define DRM_I915_ALLOC 0x08
161#define DRM_I915_FREE 0x09
162#define DRM_I915_INIT_HEAP 0x0a
163#define DRM_I915_CMDBUFFER 0x0b
164#define DRM_I915_DESTROY_HEAP 0x0c
165#define DRM_I915_SET_VBLANK_PIPE 0x0d
166#define DRM_I915_GET_VBLANK_PIPE 0x0e
167#define DRM_I915_VBLANK_SWAP 0x0f
168#define DRM_I915_HWS_ADDR 0x11
169#define DRM_I915_GEM_INIT 0x13
170#define DRM_I915_GEM_EXECBUFFER 0x14
171#define DRM_I915_GEM_PIN 0x15
172#define DRM_I915_GEM_UNPIN 0x16
173#define DRM_I915_GEM_BUSY 0x17
174#define DRM_I915_GEM_THROTTLE 0x18
175#define DRM_I915_GEM_ENTERVT 0x19
176#define DRM_I915_GEM_LEAVEVT 0x1a
177#define DRM_I915_GEM_CREATE 0x1b
178#define DRM_I915_GEM_PREAD 0x1c
179#define DRM_I915_GEM_PWRITE 0x1d
180#define DRM_I915_GEM_MMAP 0x1e
181#define DRM_I915_GEM_SET_DOMAIN 0x1f
182#define DRM_I915_GEM_SW_FINISH 0x20
183#define DRM_I915_GEM_SET_TILING 0x21
184#define DRM_I915_GEM_GET_TILING 0x22
185#define DRM_I915_GEM_GET_APERTURE 0x23
186#define DRM_I915_GEM_MMAP_GTT 0x24
187#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
188#define DRM_I915_GEM_MADVISE 0x26
189#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
190#define DRM_I915_OVERLAY_ATTRS 0x28
191
192#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
193#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
194#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
195#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
196#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
197#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
198#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
199#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
200#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
201#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
202#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
203#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
204#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
205#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
206#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
207#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
208#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
209#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
210#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
211#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
212#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
213#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
214#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
215#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
216#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
217#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
218#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
219#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
220#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
221#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
222#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
223#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
224#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
225#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
226#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
227#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
228#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
229#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
230
231/* Allow drivers to submit batchbuffers directly to hardware, relying
232 * on the security mechanisms provided by hardware.
233 */
234typedef struct drm_i915_batchbuffer {
235 int start; /* agp offset */
236 int used; /* nr bytes in use */
237 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
238 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
239 int num_cliprects; /* mulitpass with multiple cliprects? */
240 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
241} drm_i915_batchbuffer_t;
242
243/* As above, but pass a pointer to userspace buffer which can be
244 * validated by the kernel prior to sending to hardware.
245 */
246typedef struct _drm_i915_cmdbuffer {
247 char *buf; /* pointer to userspace command buffer */
248 int sz; /* nr bytes in buf */
249 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
250 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
251 int num_cliprects; /* mulitpass with multiple cliprects? */
252 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
253} drm_i915_cmdbuffer_t;
254
255/* Userspace can request & wait on irq's:
256 */
257typedef struct drm_i915_irq_emit {
258 int *irq_seq;
259} drm_i915_irq_emit_t;
260
261typedef struct drm_i915_irq_wait {
262 int irq_seq;
263} drm_i915_irq_wait_t;
264
265/* Ioctl to query kernel params:
266 */
267#define I915_PARAM_IRQ_ACTIVE 1
268#define I915_PARAM_ALLOW_BATCHBUFFER 2
269#define I915_PARAM_LAST_DISPATCH 3
270#define I915_PARAM_CHIPSET_ID 4
271#define I915_PARAM_HAS_GEM 5
272#define I915_PARAM_NUM_FENCES_AVAIL 6
273#define I915_PARAM_HAS_OVERLAY 7
274#define I915_PARAM_HAS_PAGEFLIPPING 8
275
276typedef struct drm_i915_getparam {
277 int param;
278 int *value;
279} drm_i915_getparam_t;
280
281/* Ioctl to set kernel params:
282 */
283#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
284#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
285#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
286#define I915_SETPARAM_NUM_USED_FENCES 4
287
288typedef struct drm_i915_setparam {
289 int param;
290 int value;
291} drm_i915_setparam_t;
292
293/* A memory manager for regions of shared memory:
294 */
295#define I915_MEM_REGION_AGP 1
296
297typedef struct drm_i915_mem_alloc {
298 int region;
299 int alignment;
300 int size;
301 int *region_offset; /* offset from start of fb or agp */
302} drm_i915_mem_alloc_t;
303
304typedef struct drm_i915_mem_free {
305 int region;
306 int region_offset;
307} drm_i915_mem_free_t;
308
309typedef struct drm_i915_mem_init_heap {
310 int region;
311 int size;
312 int start;
313} drm_i915_mem_init_heap_t;
314
315/* Allow memory manager to be torn down and re-initialized (eg on
316 * rotate):
317 */
318typedef struct drm_i915_mem_destroy_heap {
319 int region;
320} drm_i915_mem_destroy_heap_t;
321
322/* Allow X server to configure which pipes to monitor for vblank signals
323 */
324#define DRM_I915_VBLANK_PIPE_A 1
325#define DRM_I915_VBLANK_PIPE_B 2
326
327typedef struct drm_i915_vblank_pipe {
328 int pipe;
329} drm_i915_vblank_pipe_t;
330
331/* Schedule buffer swap at given vertical blank:
332 */
333typedef struct drm_i915_vblank_swap {
334 drm_drawable_t drawable;
335 enum drm_vblank_seq_type seqtype;
336 unsigned int sequence;
337} drm_i915_vblank_swap_t;
338
339typedef struct drm_i915_hws_addr {
340 __u64 addr;
341} drm_i915_hws_addr_t;
342
343struct drm_i915_gem_init {
344 /**
345 * Beginning offset in the GTT to be managed by the DRM memory
346 * manager.
347 */
348 __u64 gtt_start;
349 /**
350 * Ending offset in the GTT to be managed by the DRM memory
351 * manager.
352 */
353 __u64 gtt_end;
354};
355
356struct drm_i915_gem_create {
357 /**
358 * Requested size for the object.
359 *
360 * The (page-aligned) allocated size for the object will be returned.
361 */
362 __u64 size;
363 /**
364 * Returned handle for the object.
365 *
366 * Object handles are nonzero.
367 */
368 __u32 handle;
369 __u32 pad;
370};
371
372struct drm_i915_gem_pread {
373 /** Handle for the object being read. */
374 __u32 handle;
375 __u32 pad;
376 /** Offset into the object to read from */
377 __u64 offset;
378 /** Length of data to read */
379 __u64 size;
380 /**
381 * Pointer to write the data into.
382 *
383 * This is a fixed-size type for 32/64 compatibility.
384 */
385 __u64 data_ptr;
386};
387
388struct drm_i915_gem_pwrite {
389 /** Handle for the object being written to. */
390 __u32 handle;
391 __u32 pad;
392 /** Offset into the object to write to */
393 __u64 offset;
394 /** Length of data to write */
395 __u64 size;
396 /**
397 * Pointer to read the data from.
398 *
399 * This is a fixed-size type for 32/64 compatibility.
400 */
401 __u64 data_ptr;
402};
403
404struct drm_i915_gem_mmap {
405 /** Handle for the object being mapped. */
406 __u32 handle;
407 __u32 pad;
408 /** Offset in the object to map. */
409 __u64 offset;
410 /**
411 * Length of data to map.
412 *
413 * The value will be page-aligned.
414 */
415 __u64 size;
416 /**
417 * Returned pointer the data was mapped at.
418 *
419 * This is a fixed-size type for 32/64 compatibility.
420 */
421 __u64 addr_ptr;
422};
423
424struct drm_i915_gem_mmap_gtt {
425 /** Handle for the object being mapped. */
426 __u32 handle;
427 __u32 pad;
428 /**
429 * Fake offset to use for subsequent mmap call
430 *
431 * This is a fixed-size type for 32/64 compatibility.
432 */
433 __u64 offset;
434};
435
436struct drm_i915_gem_set_domain {
437 /** Handle for the object */
438 __u32 handle;
439
440 /** New read domains */
441 __u32 read_domains;
442
443 /** New write domain */
444 __u32 write_domain;
445};
446
447struct drm_i915_gem_sw_finish {
448 /** Handle for the object */
449 __u32 handle;
450};
451
452struct drm_i915_gem_relocation_entry {
453 /**
454 * Handle of the buffer being pointed to by this relocation entry.
455 *
456 * It's appealing to make this be an index into the mm_validate_entry
457 * list to refer to the buffer, but this allows the driver to create
458 * a relocation list for state buffers and not re-write it per
459 * exec using the buffer.
460 */
461 __u32 target_handle;
462
463 /**
464 * Value to be added to the offset of the target buffer to make up
465 * the relocation entry.
466 */
467 __u32 delta;
468
469 /** Offset in the buffer the relocation entry will be written into */
470 __u64 offset;
471
472 /**
473 * Offset value of the target buffer that the relocation entry was last
474 * written as.
475 *
476 * If the buffer has the same offset as last time, we can skip syncing
477 * and writing the relocation. This value is written back out by
478 * the execbuffer ioctl when the relocation is written.
479 */
480 __u64 presumed_offset;
481
482 /**
483 * Target memory domains read by this operation.
484 */
485 __u32 read_domains;
486
487 /**
488 * Target memory domains written by this operation.
489 *
490 * Note that only one domain may be written by the whole
491 * execbuffer operation, so that where there are conflicts,
492 * the application will get -EINVAL back.
493 */
494 __u32 write_domain;
495};
496
497/** @{
498 * Intel memory domains
499 *
500 * Most of these just align with the various caches in
501 * the system and are used to flush and invalidate as
502 * objects end up cached in different domains.
503 */
504/** CPU cache */
505#define I915_GEM_DOMAIN_CPU 0x00000001
506/** Render cache, used by 2D and 3D drawing */
507#define I915_GEM_DOMAIN_RENDER 0x00000002
508/** Sampler cache, used by texture engine */
509#define I915_GEM_DOMAIN_SAMPLER 0x00000004
510/** Command queue, used to load batch buffers */
511#define I915_GEM_DOMAIN_COMMAND 0x00000008
512/** Instruction cache, used by shader programs */
513#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
514/** Vertex address cache */
515#define I915_GEM_DOMAIN_VERTEX 0x00000020
516/** GTT domain - aperture and scanout */
517#define I915_GEM_DOMAIN_GTT 0x00000040
518/** @} */
519
520struct drm_i915_gem_exec_object {
521 /**
522 * User's handle for a buffer to be bound into the GTT for this
523 * operation.
524 */
525 __u32 handle;
526
527 /** Number of relocations to be performed on this buffer */
528 __u32 relocation_count;
529 /**
530 * Pointer to array of struct drm_i915_gem_relocation_entry containing
531 * the relocations to be performed in this buffer.
532 */
533 __u64 relocs_ptr;
534
535 /** Required alignment in graphics aperture */
536 __u64 alignment;
537
538 /**
539 * Returned value of the updated offset of the object, for future
540 * presumed_offset writes.
541 */
542 __u64 offset;
543};
544
545struct drm_i915_gem_execbuffer {
546 /**
547 * List of buffers to be validated with their relocations to be
548 * performend on them.
549 *
550 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
551 *
552 * These buffers must be listed in an order such that all relocations
553 * a buffer is performing refer to buffers that have already appeared
554 * in the validate list.
555 */
556 __u64 buffers_ptr;
557 __u32 buffer_count;
558
559 /** Offset in the batchbuffer to start execution from. */
560 __u32 batch_start_offset;
561 /** Bytes used in batchbuffer from batch_start_offset */
562 __u32 batch_len;
563 __u32 DR1;
564 __u32 DR4;
565 __u32 num_cliprects;
566 /** This is a struct drm_clip_rect *cliprects */
567 __u64 cliprects_ptr;
568};
569
570struct drm_i915_gem_pin {
571 /** Handle of the buffer to be pinned. */
572 __u32 handle;
573 __u32 pad;
574
575 /** alignment required within the aperture */
576 __u64 alignment;
577
578 /** Returned GTT offset of the buffer. */
579 __u64 offset;
580};
581
582struct drm_i915_gem_unpin {
583 /** Handle of the buffer to be unpinned. */
584 __u32 handle;
585 __u32 pad;
586};
587
588struct drm_i915_gem_busy {
589 /** Handle of the buffer to check for busy */
590 __u32 handle;
591
592 /** Return busy status (1 if busy, 0 if idle) */
593 __u32 busy;
594};
595
596#define I915_TILING_NONE 0
597#define I915_TILING_X 1
598#define I915_TILING_Y 2
599
600#define I915_BIT_6_SWIZZLE_NONE 0
601#define I915_BIT_6_SWIZZLE_9 1
602#define I915_BIT_6_SWIZZLE_9_10 2
603#define I915_BIT_6_SWIZZLE_9_11 3
604#define I915_BIT_6_SWIZZLE_9_10_11 4
605/* Not seen by userland */
606#define I915_BIT_6_SWIZZLE_UNKNOWN 5
607/* Seen by userland. */
608#define I915_BIT_6_SWIZZLE_9_17 6
609#define I915_BIT_6_SWIZZLE_9_10_17 7
610
611struct drm_i915_gem_set_tiling {
612 /** Handle of the buffer to have its tiling state updated */
613 __u32 handle;
614
615 /**
616 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
617 * I915_TILING_Y).
618 *
619 * This value is to be set on request, and will be updated by the
620 * kernel on successful return with the actual chosen tiling layout.
621 *
622 * The tiling mode may be demoted to I915_TILING_NONE when the system
623 * has bit 6 swizzling that can't be managed correctly by GEM.
624 *
625 * Buffer contents become undefined when changing tiling_mode.
626 */
627 __u32 tiling_mode;
628
629 /**
630 * Stride in bytes for the object when in I915_TILING_X or
631 * I915_TILING_Y.
632 */
633 __u32 stride;
634
635 /**
636 * Returned address bit 6 swizzling required for CPU access through
637 * mmap mapping.
638 */
639 __u32 swizzle_mode;
640};
641
642struct drm_i915_gem_get_tiling {
643 /** Handle of the buffer to get tiling state for. */
644 __u32 handle;
645
646 /**
647 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
648 * I915_TILING_Y).
649 */
650 __u32 tiling_mode;
651
652 /**
653 * Returned address bit 6 swizzling required for CPU access through
654 * mmap mapping.
655 */
656 __u32 swizzle_mode;
657};
658
659struct drm_i915_gem_get_aperture {
660 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
661 __u64 aper_size;
662
663 /**
664 * Available space in the aperture used by i915_gem_execbuffer, in
665 * bytes
666 */
667 __u64 aper_available_size;
668};
669
670struct drm_i915_get_pipe_from_crtc_id {
671 /** ID of CRTC being requested **/
672 __u32 crtc_id;
673
674 /** pipe of requested CRTC **/
675 __u32 pipe;
676};
677
678#define I915_MADV_WILLNEED 0
679#define I915_MADV_DONTNEED 1
680#define __I915_MADV_PURGED 2 /* internal state */
681
682struct drm_i915_gem_madvise {
683 /** Handle of the buffer to change the backing store advice */
684 __u32 handle;
685
686 /* Advice: either the buffer will be needed again in the near future,
687 * or wont be and could be discarded under memory pressure.
688 */
689 __u32 madv;
690
691 /** Whether the backing store still exists. */
692 __u32 retained;
693};
694
695/* flags */
696#define I915_OVERLAY_TYPE_MASK 0xff
697#define I915_OVERLAY_YUV_PLANAR 0x01
698#define I915_OVERLAY_YUV_PACKED 0x02
699#define I915_OVERLAY_RGB 0x03
700
701#define I915_OVERLAY_DEPTH_MASK 0xff00
702#define I915_OVERLAY_RGB24 0x1000
703#define I915_OVERLAY_RGB16 0x2000
704#define I915_OVERLAY_RGB15 0x3000
705#define I915_OVERLAY_YUV422 0x0100
706#define I915_OVERLAY_YUV411 0x0200
707#define I915_OVERLAY_YUV420 0x0300
708#define I915_OVERLAY_YUV410 0x0400
709
710#define I915_OVERLAY_SWAP_MASK 0xff0000
711#define I915_OVERLAY_NO_SWAP 0x000000
712#define I915_OVERLAY_UV_SWAP 0x010000
713#define I915_OVERLAY_Y_SWAP 0x020000
714#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
715
716#define I915_OVERLAY_FLAGS_MASK 0xff000000
717#define I915_OVERLAY_ENABLE 0x01000000
718
719struct drm_intel_overlay_put_image {
720 /* various flags and src format description */
721 __u32 flags;
722 /* source picture description */
723 __u32 bo_handle;
724 /* stride values and offsets are in bytes, buffer relative */
725 __u16 stride_Y; /* stride for packed formats */
726 __u16 stride_UV;
727 __u32 offset_Y; /* offset for packet formats */
728 __u32 offset_U;
729 __u32 offset_V;
730 /* in pixels */
731 __u16 src_width;
732 __u16 src_height;
733 /* to compensate the scaling factors for partially covered surfaces */
734 __u16 src_scan_width;
735 __u16 src_scan_height;
736 /* output crtc description */
737 __u32 crtc_id;
738 __u16 dst_x;
739 __u16 dst_y;
740 __u16 dst_width;
741 __u16 dst_height;
742};
743
744/* flags */
745#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
746#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
747struct drm_intel_overlay_attrs {
748 __u32 flags;
749 __u32 color_key;
750 __s32 brightness;
751 __u32 contrast;
752 __u32 saturation;
753 __u32 gamma0;
754 __u32 gamma1;
755 __u32 gamma2;
756 __u32 gamma3;
757 __u32 gamma4;
758 __u32 gamma5;
759};
760
761#endif /* _I915_DRM_H_ */