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Diffstat (limited to 'include/drm/radeon_drm.h')
-rw-r--r--include/drm/radeon_drm.h128
1 files changed, 64 insertions, 64 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index f09cc04c..a1e385d6 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -797,9 +797,9 @@ typedef struct drm_radeon_surface_free {
797#define RADEON_GEM_DOMAIN_VRAM 0x4 797#define RADEON_GEM_DOMAIN_VRAM 0x4
798 798
799struct drm_radeon_gem_info { 799struct drm_radeon_gem_info {
800 uint64_t gart_size; 800 __u64 gart_size;
801 uint64_t vram_size; 801 __u64 vram_size;
802 uint64_t vram_visible; 802 __u64 vram_visible;
803}; 803};
804 804
805#define RADEON_GEM_NO_BACKING_STORE (1 << 0) 805#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
@@ -811,11 +811,11 @@ struct drm_radeon_gem_info {
811#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) 811#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
812 812
813struct drm_radeon_gem_create { 813struct drm_radeon_gem_create {
814 uint64_t size; 814 __u64 size;
815 uint64_t alignment; 815 __u64 alignment;
816 uint32_t handle; 816 __u32 handle;
817 uint32_t initial_domain; 817 __u32 initial_domain;
818 uint32_t flags; 818 __u32 flags;
819}; 819};
820 820
821/* 821/*
@@ -829,10 +829,10 @@ struct drm_radeon_gem_create {
829#define RADEON_GEM_USERPTR_REGISTER (1 << 3) 829#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
830 830
831struct drm_radeon_gem_userptr { 831struct drm_radeon_gem_userptr {
832 uint64_t addr; 832 __u64 addr;
833 uint64_t size; 833 __u64 size;
834 uint32_t flags; 834 __u32 flags;
835 uint32_t handle; 835 __u32 handle;
836}; 836};
837 837
838#define RADEON_TILING_MACRO 0x1 838#define RADEON_TILING_MACRO 0x1
@@ -855,72 +855,72 @@ struct drm_radeon_gem_userptr {
855#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 855#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
856 856
857struct drm_radeon_gem_set_tiling { 857struct drm_radeon_gem_set_tiling {
858 uint32_t handle; 858 __u32 handle;
859 uint32_t tiling_flags; 859 __u32 tiling_flags;
860 uint32_t pitch; 860 __u32 pitch;
861}; 861};
862 862
863struct drm_radeon_gem_get_tiling { 863struct drm_radeon_gem_get_tiling {
864 uint32_t handle; 864 __u32 handle;
865 uint32_t tiling_flags; 865 __u32 tiling_flags;
866 uint32_t pitch; 866 __u32 pitch;
867}; 867};
868 868
869struct drm_radeon_gem_mmap { 869struct drm_radeon_gem_mmap {
870 uint32_t handle; 870 __u32 handle;
871 uint32_t pad; 871 __u32 pad;
872 uint64_t offset; 872 __u64 offset;
873 uint64_t size; 873 __u64 size;
874 uint64_t addr_ptr; 874 __u64 addr_ptr;
875}; 875};
876 876
877struct drm_radeon_gem_set_domain { 877struct drm_radeon_gem_set_domain {
878 uint32_t handle; 878 __u32 handle;
879 uint32_t read_domains; 879 __u32 read_domains;
880 uint32_t write_domain; 880 __u32 write_domain;
881}; 881};
882 882
883struct drm_radeon_gem_wait_idle { 883struct drm_radeon_gem_wait_idle {
884 uint32_t handle; 884 __u32 handle;
885 uint32_t pad; 885 __u32 pad;
886}; 886};
887 887
888struct drm_radeon_gem_busy { 888struct drm_radeon_gem_busy {
889 uint32_t handle; 889 __u32 handle;
890 uint32_t domain; 890 __u32 domain;
891}; 891};
892 892
893struct drm_radeon_gem_pread { 893struct drm_radeon_gem_pread {
894 /** Handle for the object being read. */ 894 /** Handle for the object being read. */
895 uint32_t handle; 895 __u32 handle;
896 uint32_t pad; 896 __u32 pad;
897 /** Offset into the object to read from */ 897 /** Offset into the object to read from */
898 uint64_t offset; 898 __u64 offset;
899 /** Length of data to read */ 899 /** Length of data to read */
900 uint64_t size; 900 __u64 size;
901 /** Pointer to write the data into. */ 901 /** Pointer to write the data into. */
902 /* void *, but pointers are not 32/64 compatible */ 902 /* void *, but pointers are not 32/64 compatible */
903 uint64_t data_ptr; 903 __u64 data_ptr;
904}; 904};
905 905
906struct drm_radeon_gem_pwrite { 906struct drm_radeon_gem_pwrite {
907 /** Handle for the object being written to. */ 907 /** Handle for the object being written to. */
908 uint32_t handle; 908 __u32 handle;
909 uint32_t pad; 909 __u32 pad;
910 /** Offset into the object to write to */ 910 /** Offset into the object to write to */
911 uint64_t offset; 911 __u64 offset;
912 /** Length of data to write */ 912 /** Length of data to write */
913 uint64_t size; 913 __u64 size;
914 /** Pointer to read the data from. */ 914 /** Pointer to read the data from. */
915 /* void *, but pointers are not 32/64 compatible */ 915 /* void *, but pointers are not 32/64 compatible */
916 uint64_t data_ptr; 916 __u64 data_ptr;
917}; 917};
918 918
919/* Sets or returns a value associated with a buffer. */ 919/* Sets or returns a value associated with a buffer. */
920struct drm_radeon_gem_op { 920struct drm_radeon_gem_op {
921 uint32_t handle; /* buffer */ 921 __u32 handle; /* buffer */
922 uint32_t op; /* RADEON_GEM_OP_* */ 922 __u32 op; /* RADEON_GEM_OP_* */
923 uint64_t value; /* input or return value */ 923 __u64 value; /* input or return value */
924}; 924};
925 925
926#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 926#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
@@ -940,11 +940,11 @@ struct drm_radeon_gem_op {
940#define RADEON_VM_PAGE_SNOOPED (1 << 4) 940#define RADEON_VM_PAGE_SNOOPED (1 << 4)
941 941
942struct drm_radeon_gem_va { 942struct drm_radeon_gem_va {
943 uint32_t handle; 943 __u32 handle;
944 uint32_t operation; 944 __u32 operation;
945 uint32_t vm_id; 945 __u32 vm_id;
946 uint32_t flags; 946 __u32 flags;
947 uint64_t offset; 947 __u64 offset;
948}; 948};
949 949
950#define RADEON_CHUNK_ID_RELOCS 0x01 950#define RADEON_CHUNK_ID_RELOCS 0x01
@@ -966,29 +966,29 @@ struct drm_radeon_gem_va {
966/* 0 = normal, + = higher priority, - = lower priority */ 966/* 0 = normal, + = higher priority, - = lower priority */
967 967
968struct drm_radeon_cs_chunk { 968struct drm_radeon_cs_chunk {
969 uint32_t chunk_id; 969 __u32 chunk_id;
970 uint32_t length_dw; 970 __u32 length_dw;
971 uint64_t chunk_data; 971 __u64 chunk_data;
972}; 972};
973 973
974/* drm_radeon_cs_reloc.flags */ 974/* drm_radeon_cs_reloc.flags */
975#define RADEON_RELOC_PRIO_MASK (0xf << 0) 975#define RADEON_RELOC_PRIO_MASK (0xf << 0)
976 976
977struct drm_radeon_cs_reloc { 977struct drm_radeon_cs_reloc {
978 uint32_t handle; 978 __u32 handle;
979 uint32_t read_domains; 979 __u32 read_domains;
980 uint32_t write_domain; 980 __u32 write_domain;
981 uint32_t flags; 981 __u32 flags;
982}; 982};
983 983
984struct drm_radeon_cs { 984struct drm_radeon_cs {
985 uint32_t num_chunks; 985 __u32 num_chunks;
986 uint32_t cs_id; 986 __u32 cs_id;
987 /* this points to uint64_t * which point to cs chunks */ 987 /* this points to __u64 * which point to cs chunks */
988 uint64_t chunks; 988 __u64 chunks;
989 /* updates to the limits after this CS ioctl */ 989 /* updates to the limits after this CS ioctl */
990 uint64_t gart_limit; 990 __u64 gart_limit;
991 uint64_t vram_limit; 991 __u64 vram_limit;
992}; 992};
993 993
994#define RADEON_INFO_DEVICE_ID 0x00 994#define RADEON_INFO_DEVICE_ID 0x00
@@ -1047,9 +1047,9 @@ struct drm_radeon_cs {
1047#define RADEON_INFO_GPU_RESET_COUNTER 0x26 1047#define RADEON_INFO_GPU_RESET_COUNTER 0x26
1048 1048
1049struct drm_radeon_info { 1049struct drm_radeon_info {
1050 uint32_t request; 1050 __u32 request;
1051 uint32_t pad; 1051 __u32 pad;
1052 uint64_t value; 1052 __u64 value;
1053}; 1053};
1054 1054
1055/* Those correspond to the tile index to use, this is to explicitly state 1055/* Those correspond to the tile index to use, this is to explicitly state