diff options
Diffstat (limited to 'tests/amdgpu/basic_tests.c')
-rw-r--r-- | tests/amdgpu/basic_tests.c | 111 |
1 files changed, 58 insertions, 53 deletions
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 9c918951..837ee9aa 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c | |||
@@ -868,9 +868,10 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) | |||
868 | struct amdgpu_cs_request *ibs_request; | 868 | struct amdgpu_cs_request *ibs_request; |
869 | uint64_t bo_mc; | 869 | uint64_t bo_mc; |
870 | volatile uint32_t *bo_cpu; | 870 | volatile uint32_t *bo_cpu; |
871 | int i, j, r, loop; | 871 | int i, j, r, loop, ring_id; |
872 | uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; | 872 | uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; |
873 | amdgpu_va_handle va_handle; | 873 | amdgpu_va_handle va_handle; |
874 | struct drm_amdgpu_info_hw_ip hw_ip_info; | ||
874 | 875 | ||
875 | pm4 = calloc(pm4_dw, sizeof(*pm4)); | 876 | pm4 = calloc(pm4_dw, sizeof(*pm4)); |
876 | CU_ASSERT_NOT_EQUAL(pm4, NULL); | 877 | CU_ASSERT_NOT_EQUAL(pm4, NULL); |
@@ -881,6 +882,9 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) | |||
881 | ibs_request = calloc(1, sizeof(*ibs_request)); | 882 | ibs_request = calloc(1, sizeof(*ibs_request)); |
882 | CU_ASSERT_NOT_EQUAL(ibs_request, NULL); | 883 | CU_ASSERT_NOT_EQUAL(ibs_request, NULL); |
883 | 884 | ||
885 | r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); | ||
886 | CU_ASSERT_EQUAL(r, 0); | ||
887 | |||
884 | r = amdgpu_cs_ctx_create(device_handle, &context_handle); | 888 | r = amdgpu_cs_ctx_create(device_handle, &context_handle); |
885 | CU_ASSERT_EQUAL(r, 0); | 889 | CU_ASSERT_EQUAL(r, 0); |
886 | 890 | ||
@@ -888,65 +892,66 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) | |||
888 | resources = calloc(1, sizeof(amdgpu_bo_handle)); | 892 | resources = calloc(1, sizeof(amdgpu_bo_handle)); |
889 | CU_ASSERT_NOT_EQUAL(resources, NULL); | 893 | CU_ASSERT_NOT_EQUAL(resources, NULL); |
890 | 894 | ||
891 | loop = 0; | 895 | for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { |
892 | while(loop < 2) { | 896 | loop = 0; |
893 | /* allocate UC bo for sDMA use */ | 897 | while(loop < 2) { |
894 | r = amdgpu_bo_alloc_and_map(device_handle, | 898 | /* allocate UC bo for sDMA use */ |
895 | sdma_write_length * sizeof(uint32_t), | 899 | r = amdgpu_bo_alloc_and_map(device_handle, |
896 | 4096, AMDGPU_GEM_DOMAIN_GTT, | 900 | sdma_write_length * sizeof(uint32_t), |
897 | gtt_flags[loop], &bo, (void**)&bo_cpu, | 901 | 4096, AMDGPU_GEM_DOMAIN_GTT, |
898 | &bo_mc, &va_handle); | 902 | gtt_flags[loop], &bo, (void**)&bo_cpu, |
899 | CU_ASSERT_EQUAL(r, 0); | 903 | &bo_mc, &va_handle); |
904 | CU_ASSERT_EQUAL(r, 0); | ||
900 | 905 | ||
901 | /* clear bo */ | 906 | /* clear bo */ |
902 | memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); | 907 | memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); |
903 | 908 | ||
909 | resources[0] = bo; | ||
904 | 910 | ||
905 | resources[0] = bo; | 911 | /* fulfill PM4: test DMA write-linear */ |
912 | i = j = 0; | ||
913 | if (ip_type == AMDGPU_HW_IP_DMA) { | ||
914 | if (family_id == AMDGPU_FAMILY_SI) | ||
915 | pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, | ||
916 | sdma_write_length); | ||
917 | else | ||
918 | pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, | ||
919 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | ||
920 | pm4[i++] = 0xffffffff & bo_mc; | ||
921 | pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; | ||
922 | if (family_id >= AMDGPU_FAMILY_AI) | ||
923 | pm4[i++] = sdma_write_length - 1; | ||
924 | else if (family_id != AMDGPU_FAMILY_SI) | ||
925 | pm4[i++] = sdma_write_length; | ||
926 | while(j++ < sdma_write_length) | ||
927 | pm4[i++] = 0xdeadbeaf; | ||
928 | } else if ((ip_type == AMDGPU_HW_IP_GFX) || | ||
929 | (ip_type == AMDGPU_HW_IP_COMPUTE)) { | ||
930 | pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); | ||
931 | pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; | ||
932 | pm4[i++] = 0xfffffffc & bo_mc; | ||
933 | pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; | ||
934 | while(j++ < sdma_write_length) | ||
935 | pm4[i++] = 0xdeadbeaf; | ||
936 | } | ||
906 | 937 | ||
907 | /* fulfill PM4: test DMA write-linear */ | 938 | amdgpu_test_exec_cs_helper(context_handle, |
908 | i = j = 0; | 939 | ip_type, ring_id, |
909 | if (ip_type == AMDGPU_HW_IP_DMA) { | 940 | i, pm4, |
910 | if (family_id == AMDGPU_FAMILY_SI) | 941 | 1, resources, |
911 | pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, | 942 | ib_info, ibs_request); |
912 | sdma_write_length); | ||
913 | else | ||
914 | pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, | ||
915 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | ||
916 | pm4[i++] = 0xffffffff & bo_mc; | ||
917 | pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; | ||
918 | if (family_id >= AMDGPU_FAMILY_AI) | ||
919 | pm4[i++] = sdma_write_length - 1; | ||
920 | else if (family_id != AMDGPU_FAMILY_SI) | ||
921 | pm4[i++] = sdma_write_length; | ||
922 | while(j++ < sdma_write_length) | ||
923 | pm4[i++] = 0xdeadbeaf; | ||
924 | } else if ((ip_type == AMDGPU_HW_IP_GFX) || | ||
925 | (ip_type == AMDGPU_HW_IP_COMPUTE)) { | ||
926 | pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); | ||
927 | pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; | ||
928 | pm4[i++] = 0xfffffffc & bo_mc; | ||
929 | pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; | ||
930 | while(j++ < sdma_write_length) | ||
931 | pm4[i++] = 0xdeadbeaf; | ||
932 | } | ||
933 | 943 | ||
934 | amdgpu_test_exec_cs_helper(context_handle, | 944 | /* verify if SDMA test result meets with expected */ |
935 | ip_type, 0, | 945 | i = 0; |
936 | i, pm4, | 946 | while(i < sdma_write_length) { |
937 | 1, resources, | 947 | CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); |
938 | ib_info, ibs_request); | 948 | } |
939 | 949 | ||
940 | /* verify if SDMA test result meets with expected */ | 950 | r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, |
941 | i = 0; | 951 | sdma_write_length * sizeof(uint32_t)); |
942 | while(i < sdma_write_length) { | 952 | CU_ASSERT_EQUAL(r, 0); |
943 | CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); | 953 | loop++; |
944 | } | 954 | } |
945 | |||
946 | r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, | ||
947 | sdma_write_length * sizeof(uint32_t)); | ||
948 | CU_ASSERT_EQUAL(r, 0); | ||
949 | loop++; | ||
950 | } | 955 | } |
951 | /* clean resources */ | 956 | /* clean resources */ |
952 | free(resources); | 957 | free(resources); |