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* Merge remote-tracking branch 'freedesktop/master' into aosp/masterJohn Stultz2018-04-1310-79/+222
|\ | | | | | | | | | | | | This merges the freedesktop/master branch into aosp/master Change-Id: I3104d45924f67d37808154d04c15518394204478 Signed-off-by: John Stultz <john.stultz@linaro.org>
| * Revert "libdrm: intel/Android.mk: Filter libdrm_intel library requirements ↵Emil Velikov2018-03-281-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on x86/x86_64" This reverts commit ed07718ae7bab596297abf210bb0c37c6dba58ed. The commit added a guard since libpciaccess may be missing on some setups. As of last commit there are no traces of the project, from Android POV. Hence, we can revert this workaround - which caused similar breakage to the one it's trying to fix. This time in Mesa. Cc: Rob Herring <rob.herring@linaro.org> Acked-by: John Stultz <john.stultz@linaro.org>
| * intel: Do not use libpciaccess on AndroidTomasz Figa2018-03-282-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the code not rely anymore on libpciaccess when compiled for Android to eliminate ioperm() and iopl() syscalls required by that library. As a side effect, the mappable aperture size is hardcoded to 64 MiB on Android, however nothing seems to rely on this value anyway, as checked be grepping relevant code in drm_gralloc and Mesa. Cc: Rob Herring <rob.herring@linaro.org> Signed-off-by: Tomasz Figa <tfiga@google.com> [Emil Velikov: rebase against master. add missing __func__, Eric] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: John Stultz <john.stultz@linaro.org>
| * meson,configure: include config.h automaticallyEric Engestrom2018-03-207-28/+0
| | | | | | | | | | | | | | | | | | This will prevent any more missing `#include "config.h"` bug, at the cost of having to recompile some files that didn't need to be when changing build options. Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
| * meson,configure: always define HAVE_OPEN_MEMSTREAMEric Engestrom2018-03-201-2/+2
| | | | | | | | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
| * libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64John Stultz2018-03-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building AOSP after updating libdrm project to the freedesktop/master branch, I've seen the following build errors: external/libdrm/intel/Android.mk: error: libdrm_intel (SHARED_LIBRARIES android-arm64) missing libpciaccess (SHARED_LIBRARIES android-arm64) You can set ALLOW_MISSING_DEPENDENCIES=true in your environment if this is intentional, but that may defer real problems until later in the build. Using ALLOW_MISSING_DEPENDENCIES=true when building allows things to function properly, but is not ideal. So basically, while I'm not including the libdrm_intel package into the build, just the fact that the Android.mk file references libpciaccess which isn't a repo included in AOSP causes the build failure. So it seems we need some sort of conditional filter in the Android.mk to skip over it if we're not building for intel. Cc: Chad Versace <chad.versace@linux.intel.com> Cc: Marissa Wall <marissaw@google.com> Cc: Sean Paul <seanpaul@google.com> Cc: Dan Willemsen <dwillemsen@google.com> Cc: Tomasz Figa <tfiga@google.com> Cc: Robert Foss <robert.foss@collabora.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
| * meson: use pkg-config to detect libatomic_opsEric Engestrom2018-03-091-1/+1
| | | | | | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
| * intel/intel_chipset.h: Sync Cannonlake IDs.Rodrigo Vivi2018-03-051-24/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's sync CNL ids with Spec and kernel. Sync with kernel commit '3f43031b1693 ("drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.")' and commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")' Cc: James Ausmus <james.ausmus@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
| * *-symbol-check: Don't hard-code nm executableHeiko Becker2018-02-232-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Helpful if your nm executable has a prefix based on the architecture, for example. Signed-off-by: Heiko Becker <heirecka@exherbo.org> Cc: Timo Gurr <timo.gurr@gmail.com> [Eric: v2: rebase and add Meson support] Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
| * always define HAVE_VALGRINDEric Engestrom2018-01-291-2/+2
| | | | | | | | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
| * Add meson build systemDylan Baker2018-01-121-0/+105
| | | | | | | | | | | | | | | | | | | | This patch adds a complete meson build system, including tests and install. It has the necessary hooks to allow it be used as a subproject for other meson based builds such as mesa. Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-and-tested-by: Igor Gnatenko <i.gnatenko.brain@gmail.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
| * intel: Add more Coffeelake PCI IDsAnuj Phogat2018-01-111-7/+23
| | | | | | | | | | | | | | | | Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel: Change a KBL pci id to GT2 from GT1.5Anuj Phogat2017-09-211-2/+2
| | | | | | | | | | | | | | | | | | | | See Mesa commit 9c588ff Cc: Matt Turner <mattst88@gmail.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel/intel_chipset: Move IS_9XX below IS_GEN10.Rodrigo Vivi2017-06-301-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | No functional change. Just organizing the code so it gets clear for future platforms. Paulo deserves credits becuase he was the one that just noticed this IS_9XX was in the wrong position after CNL patches got introduced. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel: add GEN10 to IS_9XX.Paulo Zanoni2017-06-301-1/+2
| | | | | | | | | | | | | | As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel/gen10: Add missed gen10 stuffBen Widawsky2017-06-302-1/+5
| | | | | | | | | | | | | | This got lost on rebase, I believe Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel: Add Cannonlake PCI IDs for Y-skus.Rodrigo Vivi2017-06-301-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
| * intel: Add Cannonlake PCI IDs for U-skus.Rodrigo Vivi2017-06-301-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for SKU not mentioned in spec. v3: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
| * intel: PCI Ids for U SKU in CFLAnusha Srivatsa2017-06-291-1/+11
| | | | | | | | | | | | | | | | | | | | | | Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel: PCI Ids for H SKU in CFLAnusha Srivatsa2017-06-291-1/+7
| | | | | | | | | | | | | | | | | | | | | | Add the PCI IDs for H SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel: PCI Ids for S SKU in CFLAnusha Srivatsa2017-06-291-1/+16
| | | | | | | | | | | | | | | | | | | | | | Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| * intel: remove dead codeEric Engestrom2017-04-101-1/+0
| | | | | | | | Signed-off-by: Eric Engestrom <eric@engestrom.ch>
| * intel: Add handle to hashtable before freeing along an error pathChris Wilson2017-03-081-4/+4
| | | | | | | | | | | | | | | | | | drm_intel_gem_bo_free() unconditionally attempts to remove the handle from the hashtable. This goes horribly wrong if we haven't already added the bo to the hashtable. Reported-by: Michael Thayer <michael.thayer@oracle.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: avoid null pointer dereferenceThomas Hindoe Paaboel Andersen2017-02-281-1/+2
| | | | | | | | | | | | | | Move the dereference after the null check. Fixes: 028715ee707469189505 ("intel: Avoid the need for most overflow checks by using a scratch page.") Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
| * intel: Move 48b support to bo_gem->kflagsChris Wilson2017-02-111-16/+5
| | | | | | | | | | | | | | Another boolean that can be set and used along side the other execobject flags. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: Move is_softpin to obj->kflagsChris Wilson2017-02-111-18/+11
| | | | | | | | | | | | | | | | Use obj->kflags to set EXEC_OBJECT_PINNED when the object is softpinned, and so remember to clear the softpin status when the object is freed (and reused). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | Convert to Android.bpDan Willemsen2017-10-233-39/+48
| | | | | | | | | | | | | | | | | | | | | | | | See build/soong/README.md for more information about Soong. Removes BOARD_GPU_DRIVERS, which wasn't affecting anything, since none of the HAVE_* macros are defined. Even if they were, we'd prefer to compile all of them so that a single library can support multiple boards. Test: mmma external/libdrm Change-Id: Ie01736bce6cf41e3da5040fe5341ade0634b5111
* | Build libdrm* modules with BOARD_VNDK_VERSIONJiyong Park2017-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | They are marked as vendor module since they all are depending on libdrm, which is a vendor lib. Also, libdrm_platform is newly introduced as the platform version of libdrm. Bug: 37342627 Bug: 63741047 Test: BOARD_VNDK_VERSION=current m -j libdrm_amdgpu libdrm_etnaviv libdrm_freedreno libdrm_intel libdrm_nouveau libdrm_radeon libdrm_rockchip libdrm_tegra libkms modetest atomictest planetest Change-Id: Ic1ff6fb616f406f1c5e005d3e6f6039758d62315 Merged-In: Ic1ff6fb616f406f1c5e005d3e6f6039758d62315
* | Merge tag libdrm-2.4.75 into aosp/masterRichard Yoo2017-05-0912-138/+1624
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Below is a brief summary of patches pulled in: 0da99b8a (m/master, aosp/master) Move libdrm.so to vendor partition d4b83443 (tag: libdrm-2.4.75) Bump version for 2.4.75 release dae413e4 (tag: libdrm-2.4.74) Bump version for release 317bdff1 (tag: libdrm-2.4.73) Bump version for release 8cf43127 (tag: libdrm-2.4.72) Bump version for release a44c9c31 (tag: libdrm-2.4.71) Bump version for release 20208455 (tag: android-o-preview-1, tag: android-n-mr2-preview-2, tag: android-n-mr2-preview-1, aosp/sdk-release, aosp/o-preview) add a flag control that private libdrm can be chosen Bug: 35871718 Test: aosp_arm-eng compiles Change-Id: I81985fd41d5c0d8a732705dc2a4bee8eb5d459bb
| * intel: fix make distcheckDave Airlie2017-01-271-0/+4
| | | | | | | | Signed-off-by: Dave Airlie <airlied@redhat.com>
| * intel: Export a function to re-enable implicit synchronisationChris Wilson2017-01-272-0/+20
| | | | | | | | | | | | | | | | | | Implicit synchronisation is the default behaviour of the kernel when rendering with an execobject. It may be disabled with drm_intel_gem_bo_disable_implicit_sync(), and then to restore it use drm_intel_gem_bo_enable_implicit_sync(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: Clear execobject flags before preserving object in reuse cacheChris Wilson2017-01-271-0/+2
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: Support passing of explicit fencing from execbufChris Wilson2017-01-272-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | Allow the caller to pass in an fd to an array of fences to control serialisation of the execbuf in the kernel and on the GPU, and in return allow creation of a fence fd for signaling the completion (and flushing) of the batch. When the returned fence is signaled, all writes to the buffers inside the batch will be complete and coherent from the cpu, or other consumers. The return fence is a sync_file object and can be passed to other users (such as atomic modesetting, or other drivers). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: Allow the client to control implicit synchronisationChris Wilson2017-01-272-4/+49
| | | | | | | | | | | | | | The kernel allows implicit synchronisation to be disabled on individual buffers. Use at your own risk. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * android: introduce Android.common.mk to reduce boilerplateEmil Velikov2017-01-271-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... across the makefiles. Currently this isn't much but that will change shortly. As an added bonus this fixes all present and future cases where we've forgotten to strip out the headers from LOCAL_SRC_FILES. In a couple of cases (the tests) we start setting LOCAL_EXPORT_C_INCLUDE_DIRS, which shouldn't be an issue. Cc: Chih-Wei Huang <cwhuang@android-x86.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * android: remove LOCAL_MODULE_TAGS := optional tagEmil Velikov2017-01-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Seems to be the default option since ~2009 with commit 2f31293ba78 "auto import from //branches/cupcake/...@137197". Fleshed out from a larger commit in the AOSP repo/fork. Cc: Dan Willemsen <dwillemsen@google.com> Cc: Chih-Wei Huang <cwhuang@android-x86.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * intel: update global_name before HASH_ADDDongwon Kim2017-01-151-2/+3
| | | | | | | | | | | | | | | | bo->global_name should be updated first before a hash value for the entry is calculated with it by HASH_ADD macro. Signed-off-by: Dongwon Kim <dongwon.kim@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * libdrm: random typo fixesGrazvydas Ignotas2016-11-222-5/+5
| | | | | | | | | | | | | | | | | | Just some trivial boring typo fixes all over the tree. READMEs and comments only. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
| * intel: Add drm_intel_gem_context_get_id to intel-symbols-checkMichel Dänzer2016-11-221-0/+1
| | | | | | | | Fixes make check. Trivial.
| * intel: Add a getter for the intel_context ctx_idRobert Bragg2016-11-212-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exposing the u32 context ID makes it possible to define new drm kernel interfaces based on the same IDs that e.g. execbuf uses to identify a gem context, that aren't themselves abstracted by libdrm but need to be used by libdrm/drm_intel_context based clients such as (parts of) i-g-t or Mesa. For example this can be used to configure an i915-perf stream to collect metrics for a specific context. v2: s/drm_intel_gem_context_get_context_id/drm_intel_gem_context_get_id/ Signed-off-by: Robert Bragg <robert@sixbynine.org> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
| * intel: Add Geminilake PCI IDsBen Widawsky2016-11-181-3/+10
| | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
| * intel: Add uthash.h to Makefile.sources.Matt Turner2016-11-141-1/+2
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| * intel: Allow some codenames in INTEL_DEVID_OVERRIDENeil Roberts2016-11-141-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | As well as allowing a hexadecimal PCI ID number, the INTEL_DEVID_OVERRIDE environment variable can now contain one of a few short codenames. The codenames are stored in a small table to map them to a corresponding PCI ID. This makes it easier to use without having to look up the PCI IDs manually. The PCI IDs used are the same as those chosen for the -p option of run.c in shader-db but SKL has been added as well. Reviewed-by: Matt Turner <mattst88@gmail.com>
| * intel: Look prime handle up in handle hash tableChris Wilson2016-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | A slightly confused copy'n'paste from the open path where we pass in handle but use it as a global name, in the prime handle-from-fd pass we pass in handle and do mean handle! References: https://bugs.freedesktop.org/show_bug.cgi?id=98416 Fixes: 2f23bf1b7b89 ("intel: Migrate handle/name lookups from linear lists...") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: Add new symbols to intel-symbol-checkMichel Dänzer2016-10-231-0/+3
| | | | | | | | | | | | Fixes make check. Trivial.
| * intel: Migrate handle/name lookups from linear lists to hashtablesChris Wilson2016-10-222-101/+1181
| | | | | | | | | | | | | | | | | | | | Walking a linear list to find a matching PRIME handle or flinked name does not scale and becomes a major burden with just a few objects. That said, the fixed size hash is not much better, it just buckets the look into a few separate chains rather than one long one. References: https://bugs.freedesktop.org/show_bug.cgi?id=94631 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: Export raw GEM mmap interfacesChris Wilson2016-10-222-0/+158
| | | | | | | | | | | | | | | | Export a set of interfaces to allow the caller to have precise control over mapping the buffer - but still provide caching of the mmaps between callers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * intel: Add new symbols to intel-symbol-checkMichel Dänzer2016-09-081-0/+2
| | | | | | | | | | | | Fixes make check. Trivial.
| * intel: Export pooled EU and min no. of eus in a pool.Yang Rong2016-09-072-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update kernel interface with new I915_GETPARAM ioctl entries for pooled EU and min no. of eus in a pool. Add a wrapping function for each parameter. Userspace drivers need these values when decide the thread count. This kernel enabled pooled eu by default for BXT and for fused down 2x6 parts it is advised to turn it off. But there is another HW issue in these parts (fused down 2x6 parts) before C0 that requires Pooled EU to be enabled as a workaround. In this case the pool configuration changes depending upon which subslice is disabled and the no. of eus in a pool is different, So userspace need to know min no. of eus in a pool. V2: use return value as the query results. ret < 0 when error, ret = 0 when not support, and ret > 0 indicate query results.(Chris) V3: Correct V2 errors. Signed-off-by: Yang Rong <rong.r.yang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
| * automake: Don't include Android Makefiles in the release tarballAndreas Boll2016-07-231-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only some Android Makefiles are included in the release tarball. To be more consistent one could either add the remaining files or don't ship Android Makefiles altogether. According to Emil the Android folk doesn't use our release tarballs. Thus it makes sense to remove those files from distribution which also means less work for maintenance in the future. Suggested-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
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