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* radeon: implement 2D tiling for CIKMarek Olšák2013-11-221-0/+1
| | | | | | | | | Bug fixes and simplification by Marek. We have to use the tile index of 0 for non-MSAA depth-stencil after all. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transitionMarek Olšák2013-05-151-0/+1
| | | | | Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeon: add si tiling support v5Jerome Glisse2013-04-121-0/+31
| | | | | | | | | | v2: Only writte tile index if flags for it is set v3: Remove useless allow2d scanout flags v4: Split radeon_drm.h update to its own patch v5: update against lastest next tree for radeon Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeon: fix stencil miptree allocation of combined ZS buffers on EG and SIMarek Olšák2012-10-051-0/+2
| | | | | | | | | This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeon: fix surface API for good before anyone start relying on itJerome Glisse2012-02-031-3/+3
| | | | | | | | | The mipmap level computation was wrong, we need to know the block width, height, depth of compressed texture to properly compute this. Change API to provide block width, height, depth instead of nblk_x, nblk_y, nblk_z. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
* radeon: add surface allocator helper v10Jerome Glisse2012-02-011-0/+114
The surface allocator is able to build complete miptree when allocating surface for r600/r700/evergreen/northern islands GPU family. It also compute bo size and alignment for render buffer, depth buffer and scanout buffer. v2 fix r6xx/r7xx 2D tiling width align computation v3 add tile split support and fix 1d texture alignment v4 rework to more properly support compressed format, split surface pixel size and surface element size in separate fields v5 support texture array (still issue on r6xx) v6 split surface value computation and mipmap tree building, rework eg and newer computation v7 add a check for tile split and 2d tiled v8 initialize mode value before testing it in all case, reenable 2D macro tile mode on r6xx for cubemap and array. Fix cubemap to force array size to the number of face. v9 fix handling of stencil buffer on evergreen v10 on evergreen depth buffer need to have enough room for a stencil buffer just after depth one Signed-off-by: Jerome Glisse <jglisse@redhat.com>