From 07edf5d905fffb908f48996a4fcc6eac63b9c3ae Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Wed, 1 Feb 2017 15:29:38 +0000 Subject: Remove unused tests/drmstat.c Earlier commit removed all the legacy 'tests' but a file was left danglig. Fixes: 0c80fddd1d0 "tests: remove useless legacy tests" Signed-off-by: Emil Velikov Reported-by: Andreas Boll Reviewed-by: Andreas Boll Acked-by: Daniel Vetter --- tests/drmstat.c | 419 -------------------------------------------------------- 1 file changed, 419 deletions(-) delete mode 100644 tests/drmstat.c diff --git a/tests/drmstat.c b/tests/drmstat.c deleted file mode 100644 index 023aa069..00000000 --- a/tests/drmstat.c +++ /dev/null @@ -1,419 +0,0 @@ -/* drmstat.c -- DRM device status and testing program - * Created: Tue Jan 5 08:19:24 1999 by faith@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: Rickard E. (Rik) Faith - * - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef HAVE_ALLOCA_H -# include -#endif -#include "xf86drm.h" - -int sigio_fd; - -static double usec(struct timeval *end, struct timeval *start) -{ - double e = end->tv_sec * 1000000 + end->tv_usec; - double s = start->tv_sec * 1000000 + start->tv_usec; - - return e - s; -} - -static void getversion(int fd) -{ - drmVersionPtr version; - - version = drmGetVersion(fd); - if (version) { - printf( "Name: %s\n", version->name ? version->name : "?" ); - printf( " Version: %d.%d.%d\n", - version->version_major, - version->version_minor, - version->version_patchlevel ); - printf( " Date: %s\n", version->date ? version->date : "?" ); - printf( " Desc: %s\n", version->desc ? version->desc : "?" ); - drmFreeVersion(version); - } else { - printf( "No driver available\n" ); - } -} - -static void process_sigio(char *device) -{ - int fd; - - if ((fd = open(device, 0)) < 0) { - drmError(-errno, __func__); - exit(1); - } - - sigio_fd = fd; - for (;;) sleep(60); -} - -int main(int argc, char **argv) -{ - int c; - int r = 0; - int fd = -1; - drm_handle_t handle; - void *address; - char *pt; - unsigned long count; - unsigned long offset; - unsigned long size; - drm_context_t context; - int loops; - char buf[1024]; - int i; - drmBufInfoPtr info; - drmBufMapPtr bufs; - drmLockPtr lock; - int secs; - - while ((c = getopt(argc, argv, - "lc:vo:O:f:s:w:W:b:r:R:P:L:C:XS:B:F:")) != EOF) - switch (c) { - case 'F': - count = strtoul(optarg, NULL, 0); - if (!fork()) { - dup(fd); - sleep(count); - } - close(fd); - break; - case 'v': getversion(fd); break; - case 'X': - if ((r = drmCreateContext(fd, &context))) { - drmError(r, argv[0]); - return 1; - } - printf( "Got %d\n", context); - break; - case 'S': - process_sigio(optarg); - break; - case 'C': - if ((r = drmSwitchToContext(fd, strtoul(optarg, NULL, 0)))) { - drmError(r, argv[0]); - return 1; - } - break; - case 'c': - if ((r = drmSetBusid(fd,optarg))) { - drmError(r, argv[0]); - return 1; - } - break; - case 'o': - if ((fd = drmOpen(optarg, NULL)) < 0) { - drmError(fd, argv[0]); - return 1; - } - break; - case 'O': - if ((fd = drmOpen(NULL, optarg)) < 0) { - drmError(fd, argv[0]); - return 1; - } - break; - case 'B': /* Test buffer allocation */ - count = strtoul(optarg, &pt, 0); - size = strtoul(pt+1, &pt, 0); - secs = strtoul(pt+1, NULL, 0); - { - drmDMAReq dma; - int *indices, *sizes; - - indices = alloca(sizeof(*indices) * count); - sizes = alloca(sizeof(*sizes) * count); - dma.context = context; - dma.send_count = 0; - dma.request_count = count; - dma.request_size = size; - dma.request_list = indices; - dma.request_sizes = sizes; - dma.flags = DRM_DMA_WAIT; - if ((r = drmDMA(fd, &dma))) { - drmError(r, argv[0]); - return 1; - } - for (i = 0; i < dma.granted_count; i++) { - printf("%5d: index = %d, size = %d\n", - i, dma.request_list[i], dma.request_sizes[i]); - } - sleep(secs); - drmFreeBufs(fd, dma.granted_count, indices); - } - break; - case 'b': - count = strtoul(optarg, &pt, 0); - size = strtoul(pt+1, NULL, 0); - if ((r = drmAddBufs(fd, count, size, 0, 65536)) < 0) { - drmError(r, argv[0]); - return 1; - } - if (!(info = drmGetBufInfo(fd))) { - drmError(0, argv[0]); - return 1; - } - for (i = 0; i < info->count; i++) { - printf("%5d buffers of size %6d (low = %d, high = %d)\n", - info->list[i].count, - info->list[i].size, - info->list[i].low_mark, - info->list[i].high_mark); - } - if ((r = drmMarkBufs(fd, 0.50, 0.80))) { - drmError(r, argv[0]); - return 1; - } - if (!(info = drmGetBufInfo(fd))) { - drmError(0, argv[0]); - return 1; - } - for (i = 0; i < info->count; i++) { - printf("%5d buffers of size %6d (low = %d, high = %d)\n", - info->list[i].count, - info->list[i].size, - info->list[i].low_mark, - info->list[i].high_mark); - } - printf("===== /proc/dri/0/mem =====\n"); - sprintf(buf, "cat /proc/dri/0/mem"); - system(buf); -#if 1 - if (!(bufs = drmMapBufs(fd))) { - drmError(0, argv[0]); - return 1; - } - printf("===============================\n"); - printf( "%d bufs\n", bufs->count); - for (i = 0; i < bufs->count; i++) { - printf( " %4d: %8d bytes at %p\n", - i, - bufs->list[i].total, - bufs->list[i].address); - } - printf("===== /proc/dri/0/vma =====\n"); - sprintf(buf, "cat /proc/dri/0/vma"); - system(buf); -#endif - break; - case 'f': - offset = strtoul(optarg, &pt, 0); - size = strtoul(pt+1, NULL, 0); - handle = 0; - if ((r = drmAddMap(fd, offset, size, - DRM_FRAME_BUFFER, 0, &handle))) { - drmError(r, argv[0]); - return 1; - } - printf("0x%08lx:0x%04lx added\n", offset, size); - printf("===== /proc/dri/0/mem =====\n"); - sprintf(buf, "cat /proc/dri/0/mem"); - system(buf); - break; - case 'r': - case 'R': - offset = strtoul(optarg, &pt, 0); - size = strtoul(pt+1, NULL, 0); - handle = 0; - if ((r = drmAddMap(fd, offset, size, - DRM_REGISTERS, - c == 'R' ? DRM_READ_ONLY : 0, - &handle))) { - drmError(r, argv[0]); - return 1; - } - printf("0x%08lx:0x%04lx added\n", offset, size); - printf("===== /proc/dri/0/mem =====\n"); - sprintf(buf, "cat /proc/dri/0/mem"); - system(buf); - break; - case 's': - size = strtoul(optarg, &pt, 0); - handle = 0; - if ((r = drmAddMap(fd, 0, size, - DRM_SHM, DRM_CONTAINS_LOCK, - &handle))) { - drmError(r, argv[0]); - return 1; - } - printf("0x%04lx byte shm added at 0x%08lx\n", size, handle); - sprintf(buf, "cat /proc/dri/0/vm"); - system(buf); - break; - case 'P': - offset = strtoul(optarg, &pt, 0); - size = strtoul(pt+1, NULL, 0); - address = NULL; - if ((r = drmMap(fd, offset, size, &address))) { - drmError(r, argv[0]); - return 1; - } - printf("0x%08lx:0x%04lx mapped at %p for pid %d\n", - offset, size, address, getpid()); - printf("===== /proc/dri/0/vma =====\n"); - sprintf(buf, "cat /proc/dri/0/vma"); - system(buf); - mprotect((void *)offset, size, PROT_READ); - printf("===== /proc/dri/0/vma =====\n"); - sprintf(buf, "cat /proc/dri/0/vma"); - system(buf); - break; - case 'w': - case 'W': - offset = strtoul(optarg, &pt, 0); - size = strtoul(pt+1, NULL, 0); - address = NULL; - if ((r = drmMap(fd, offset, size, &address))) { - drmError(r, argv[0]); - return 1; - } - printf("0x%08lx:0x%04lx mapped at %p for pid %d\n", - offset, size, address, getpid()); - printf("===== /proc/%d/maps =====\n", getpid()); - sprintf(buf, "cat /proc/%d/maps", getpid()); - system(buf); - printf("===== /proc/dri/0/mem =====\n"); - sprintf(buf, "cat /proc/dri/0/mem"); - system(buf); - printf("===== /proc/dri/0/vma =====\n"); - sprintf(buf, "cat /proc/dri/0/vma"); - system(buf); - printf("===== READING =====\n"); - for (i = 0; i < 0x10; i++) - printf("%02x ", (unsigned int)((unsigned char *)address)[i]); - printf("\n"); - if (c == 'w') { - printf("===== WRITING =====\n"); - for (i = 0; i < size; i+=2) { - ((char *)address)[i] = i & 0xff; - ((char *)address)[i+1] = i & 0xff; - } - } - printf("===== READING =====\n"); - for (i = 0; i < 0x10; i++) - printf("%02x ", (unsigned int)((unsigned char *)address)[i]); - printf("\n"); - printf("===== /proc/dri/0/vma =====\n"); - sprintf(buf, "cat /proc/dri/0/vma"); - system(buf); - break; - case 'L': - context = strtoul(optarg, &pt, 0); - offset = strtoul(pt+1, &pt, 0); - size = strtoul(pt+1, &pt, 0); - loops = strtoul(pt+1, NULL, 0); - address = NULL; - if ((r = drmMap(fd, offset, size, &address))) { - drmError(r, argv[0]); - return 1; - } - lock = address; -#if 1 - { - int counter = 0; - struct timeval loop_start, loop_end; - struct timeval lock_start, lock_end; - double wt; -#define HISTOSIZE 9 - int histo[HISTOSIZE]; - int output = 0; - int fast = 0; - - if (loops < 0) { - loops = -loops; - ++output; - } - - for (i = 0; i < HISTOSIZE; i++) histo[i] = 0; - - gettimeofday(&loop_start, NULL); - for (i = 0; i < loops; i++) { - gettimeofday(&lock_start, NULL); - DRM_LIGHT_LOCK_COUNT(fd,lock,context,fast); - gettimeofday(&lock_end, NULL); - DRM_UNLOCK(fd,lock,context); - ++counter; - wt = usec(&lock_end, &lock_start); - if (wt <= 2.5) ++histo[8]; - if (wt < 5.0) ++histo[0]; - else if (wt < 50.0) ++histo[1]; - else if (wt < 500.0) ++histo[2]; - else if (wt < 5000.0) ++histo[3]; - else if (wt < 50000.0) ++histo[4]; - else if (wt < 500000.0) ++histo[5]; - else if (wt < 5000000.0) ++histo[6]; - else ++histo[7]; - if (output) printf( "%.2f uSec, %d fast\n", wt, fast); - } - gettimeofday(&loop_end, NULL); - printf( "Average wait time = %.2f usec, %d fast\n", - usec(&loop_end, &loop_start) / counter, fast); - printf( "%9d <= 2.5 uS\n", histo[8]); - printf( "%9d < 5 uS\n", histo[0]); - printf( "%9d < 50 uS\n", histo[1]); - printf( "%9d < 500 uS\n", histo[2]); - printf( "%9d < 5000 uS\n", histo[3]); - printf( "%9d < 50000 uS\n", histo[4]); - printf( "%9d < 500000 uS\n", histo[5]); - printf( "%9d < 5000000 uS\n", histo[6]); - printf( "%9d >= 5000000 uS\n", histo[7]); - } -#else - printf( "before lock: 0x%08x\n", lock->lock); - printf( "lock: 0x%08x\n", lock->lock); - sleep(5); - printf( "unlock: 0x%08x\n", lock->lock); -#endif - break; - default: - fprintf( stderr, "Usage: drmstat [options]\n" ); - return 1; - } - - return r; -} - -int xf86ConfigDRI[10]; -- cgit v1.2.3-54-g00ecf From 7a03cdf6a703911d2a8e8ab0781f1e6b88412329 Mon Sep 17 00:00:00 2001 From: Alex Xie Date: Sat, 28 Jan 2017 21:49:30 +0200 Subject: amdgpu: Free/uninit vamgr_32 in theoretically correct order vamgr_32 is a region inside general VAM range. It is better to free and deinitialize it before general VAM range. Reviewed-by: Edward O'Callaghan Reviewed-by: Emil Velikov Signed-off-by: Alex Xie Reviewed-by: Christian König Signed-off-by: Alex Deucher --- amdgpu/amdgpu_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index f4ede031..cad7133d 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -131,10 +131,10 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); amdgpu_vamgr_deinit(dev->vamgr_32); free(dev->vamgr_32); + amdgpu_vamgr_deinit(dev->vamgr); + free(dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); util_hash_table_destroy(dev->bo_handles); pthread_mutex_destroy(&dev->bo_table_mutex); -- cgit v1.2.3-54-g00ecf From 067e9a1d47a8373b3145481a70fec84ce8e76441 Mon Sep 17 00:00:00 2001 From: Alex Xie Date: Sat, 28 Jan 2017 21:50:36 +0200 Subject: amdgpu: vamgr_32 can be a struct instead of a pointer vamgr_32 is an integral part of amdgpu_device. We don't need to calloc and free it. This can save CPU time, reduce heap fragmentation. Reviewed-by: Edward O'Callaghan Reviewed-by: Emil Velikov Signed-off-by: Alex Xie Reviewed-by: Christian König [Grazvydas Ignotas: rebase, correct a typo in commit message] Signed-off-by: Alex Deucher --- amdgpu/amdgpu_device.c | 8 ++------ amdgpu/amdgpu_internal.h | 2 +- amdgpu/amdgpu_vamgr.c | 4 ++-- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index cad7133d..11714e47 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -131,8 +131,7 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - amdgpu_vamgr_deinit(dev->vamgr_32); - free(dev->vamgr_32); + amdgpu_vamgr_deinit(&dev->vamgr_32); amdgpu_vamgr_deinit(dev->vamgr); free(dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); @@ -270,10 +269,7 @@ int amdgpu_device_initialize(int fd, if (start > 0xffffffff) goto free_va; /* shouldn't get here */ - dev->vamgr_32 = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); - if (dev->vamgr_32 == NULL) - goto free_va; - amdgpu_vamgr_init(dev->vamgr_32, start, max, + amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); *major_version = dev->major_version; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 4f039b68..7e237ac1 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -87,7 +87,7 @@ struct amdgpu_device { /** The global VA manager for the whole virtual address space */ struct amdgpu_bo_va_mgr *vamgr; /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr *vamgr_32; + struct amdgpu_bo_va_mgr vamgr_32; }; struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 8a707cbc..4dc4253c 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -236,7 +236,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, struct amdgpu_bo_va_mgr *vamgr; if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = dev->vamgr_32; + vamgr = &dev->vamgr_32; else vamgr = dev->vamgr; @@ -249,7 +249,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, if (!(flags & AMDGPU_VA_RANGE_32_BIT) && (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { /* fallback to 32bit address */ - vamgr = dev->vamgr_32; + vamgr = &dev->vamgr_32; *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, va_base_alignment, va_base_required); } -- cgit v1.2.3-54-g00ecf From fe7cb34eda1855ac9770bc9f3e582897000e41b0 Mon Sep 17 00:00:00 2001 From: Alex Xie Date: Sat, 28 Jan 2017 21:50:44 +0200 Subject: amdgpu: vamgr can be a struct instead of a pointer vamgr is an integral part of amdgpu_device. We don't need to calloc and free it. This can save CPU time, reduce heap fragmentation. Reviewed-by: Edward O'Callaghan Reviewed-by: Emil Velikov Signed-off-by: Alex Xie Reviewed-by: Christian König [Grazvydas Ignotas: rebase, correct a typo in commit message] Signed-off-by: Alex Deucher --- amdgpu/amdgpu_device.c | 16 +++++----------- amdgpu/amdgpu_internal.h | 2 +- amdgpu/amdgpu_vamgr.c | 2 +- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 11714e47..f473d2da 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -132,8 +132,7 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { amdgpu_vamgr_deinit(&dev->vamgr_32); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); + amdgpu_vamgr_deinit(&dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); util_hash_table_destroy(dev->bo_handles); pthread_mutex_destroy(&dev->bo_table_mutex); @@ -254,16 +253,12 @@ int amdgpu_device_initialize(int fd, if (r) goto cleanup; - dev->vamgr = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); - if (dev->vamgr == NULL) - goto cleanup; - - amdgpu_vamgr_init(dev->vamgr, dev->dev_info.virtual_address_offset, + amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset, dev->dev_info.virtual_address_max, dev->dev_info.virtual_address_alignment); max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); - start = amdgpu_vamgr_find_va(dev->vamgr, + start = amdgpu_vamgr_find_va(&dev->vamgr, max - dev->dev_info.virtual_address_offset, dev->dev_info.virtual_address_alignment, 0); if (start > 0xffffffff) @@ -282,10 +277,9 @@ int amdgpu_device_initialize(int fd, free_va: r = -ENOMEM; - amdgpu_vamgr_free_va(dev->vamgr, start, + amdgpu_vamgr_free_va(&dev->vamgr, start, max - dev->dev_info.virtual_address_offset); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); + amdgpu_vamgr_deinit(&dev->vamgr); cleanup: if (dev->fd >= 0) diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 7e237ac1..cf119a53 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -85,7 +85,7 @@ struct amdgpu_device { struct drm_amdgpu_info_device dev_info; struct amdgpu_gpu_info info; /** The global VA manager for the whole virtual address space */ - struct amdgpu_bo_va_mgr *vamgr; + struct amdgpu_bo_va_mgr vamgr; /** The VA manager for the 32bit address space */ struct amdgpu_bo_va_mgr vamgr_32; }; diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 4dc4253c..2b1388ed 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -238,7 +238,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, if (flags & AMDGPU_VA_RANGE_32_BIT) vamgr = &dev->vamgr_32; else - vamgr = dev->vamgr; + vamgr = &dev->vamgr; va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); size = ALIGN(size, vamgr->va_alignment); -- cgit v1.2.3-54-g00ecf From e0f05b2fad60f04971f05b4dcd7b219b1b21bd5e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 28 Jan 2017 16:32:23 +0000 Subject: intel: Move is_softpin to obj->kflags Use obj->kflags to set EXEC_OBJECT_PINNED when the object is softpinned, and so remember to clear the softpin status when the object is freed (and reused). Signed-off-by: Chris Wilson --- intel/intel_bufmgr_gem.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index a6656003..0b66e152 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -278,11 +278,6 @@ struct _drm_intel_bo_gem { */ bool use_48b_address_range; - /** - * Whether this buffer is softpinned at offset specified by the user - */ - bool is_softpin; - /** * Size in bytes of this buffer and its relocation descendents. * @@ -438,7 +433,7 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) { DBG("%2d: %d %s(%s)\n", i, bo_gem->gem_handle, - bo_gem->is_softpin ? "*" : "", + bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "", bo_gem->name); continue; } @@ -452,7 +447,7 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) "%d (%s)@0x%08x %08x + 0x%08x\n", i, bo_gem->gem_handle, - bo_gem->is_softpin ? "*" : "", + bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "", bo_gem->name, upper_32_bits(bo_gem->relocs[j].offset), lower_32_bits(bo_gem->relocs[j].offset), @@ -471,7 +466,7 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) "%d *(%s)@0x%08x %08x\n", i, bo_gem->gem_handle, - bo_gem->is_softpin ? "*" : "", + bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "", bo_gem->name, target_gem->gem_handle, target_gem->name, @@ -541,14 +536,13 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; int index; - int flags = 0; + unsigned long flags; + flags = 0; if (need_fence) flags |= EXEC_OBJECT_NEEDS_FENCE; if (bo_gem->use_48b_address_range) flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - if (bo_gem->is_softpin) - flags |= EXEC_OBJECT_PINNED; if (bo_gem->validate_index != -1) { bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= flags; @@ -579,7 +573,7 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs; bufmgr_gem->exec2_objects[index].alignment = bo->align; bufmgr_gem->exec2_objects[index].offset = bo->offset64; - bufmgr_gem->exec2_objects[index].flags = flags | bo_gem->kflags; + bufmgr_gem->exec2_objects[index].flags = bo_gem->kflags | flags; bufmgr_gem->exec2_objects[index].rsvd1 = 0; bufmgr_gem->exec2_objects[index].rsvd2 = 0; bufmgr_gem->exec_bos[index] = bo; @@ -1411,8 +1405,6 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) bo_gem->name = NULL; bo_gem->validate_index = -1; - bo_gem->kflags = 0; - DRMLISTADDTAIL(&bo_gem->head, &bucket->head); } else { drm_intel_gem_bo_free(bo); @@ -2071,7 +2063,7 @@ drm_intel_gem_bo_add_softpin_target(drm_intel_bo *bo, drm_intel_bo *target_bo) return -ENOMEM; } - if (!target_bo_gem->is_softpin) + if (!(target_bo_gem->kflags & EXEC_OBJECT_PINNED)) return -EINVAL; if (target_bo_gem == bo_gem) return -EINVAL; @@ -2103,7 +2095,7 @@ drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)target_bo; - if (target_bo_gem->is_softpin) + if (target_bo_gem->kflags & EXEC_OBJECT_PINNED) return drm_intel_gem_bo_add_softpin_target(bo, target_bo); else return do_bo_emit_reloc(bo, offset, target_bo, target_offset, @@ -2287,7 +2279,7 @@ drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem) /* If we're seeing softpinned object here it means that the kernel * has relocated our object... Indicating a programming error */ - assert(!bo_gem->is_softpin); + assert(!(bo_gem->kflags & EXEC_OBJECT_PINNED)); DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n", bo_gem->gem_handle, bo_gem->name, upper_32_bits(bo->offset64), @@ -2643,9 +2635,10 @@ drm_intel_gem_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset) { drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; - bo_gem->is_softpin = true; bo->offset64 = offset; bo->offset = offset; + bo_gem->kflags |= EXEC_OBJECT_PINNED; + return 0; } -- cgit v1.2.3-54-g00ecf From ec80fd36a752960f28c5c900c8c68e201ce07093 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 11 Feb 2017 11:04:50 +0000 Subject: intel: Move 48b support to bo_gem->kflags Another boolean that can be set and used along side the other execobject flags. Signed-off-by: Chris Wilson --- intel/intel_bufmgr_gem.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 0b66e152..b1e69070 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -269,15 +269,6 @@ struct _drm_intel_bo_gem { */ bool is_userptr; - /** - * Boolean of whether this buffer can be placed in the full 48-bit - * address range on gen8+. - * - * By default, buffers will be keep in a 32-bit range, unless this - * flag is explicitly set. - */ - bool use_48b_address_range; - /** * Size in bytes of this buffer and its relocation descendents. * @@ -541,8 +532,6 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) flags = 0; if (need_fence) flags |= EXEC_OBJECT_NEEDS_FENCE; - if (bo_gem->use_48b_address_range) - flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS; if (bo_gem->validate_index != -1) { bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= flags; @@ -851,7 +840,6 @@ retry: bo_gem->used_as_reloc_target = false; bo_gem->has_error = false; bo_gem->reusable = true; - bo_gem->use_48b_address_range = false; drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, alignment); pthread_mutex_unlock(&bufmgr_gem->lock); @@ -1010,7 +998,6 @@ drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr, bo_gem->used_as_reloc_target = false; bo_gem->has_error = false; bo_gem->reusable = false; - bo_gem->use_48b_address_range = false; drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0); pthread_mutex_unlock(&bufmgr_gem->lock); @@ -1158,7 +1145,6 @@ drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, bo_gem->bo.handle = open_arg.handle; bo_gem->global_name = handle; bo_gem->reusable = false; - bo_gem->use_48b_address_range = false; HASH_ADD(handle_hh, bufmgr_gem->handle_table, gem_handle, sizeof(bo_gem->gem_handle), bo_gem); @@ -2046,7 +2032,11 @@ static void drm_intel_gem_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable) { drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; - bo_gem->use_48b_address_range = enable; + + if (enable) + bo_gem->kflags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + else + bo_gem->kflags &= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS; } static int @@ -2702,7 +2692,6 @@ drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int s bo_gem->used_as_reloc_target = false; bo_gem->has_error = false; bo_gem->reusable = false; - bo_gem->use_48b_address_range = false; memclear(get_tiling); get_tiling.handle = bo_gem->gem_handle; -- cgit v1.2.3-54-g00ecf From f6499b11534450b0f8c2b20529ebedaae924c156 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Tue, 14 Feb 2017 01:34:14 +0000 Subject: headers: add explicit note against local changes in the README Even with the step by step guide people sometimes get confused. Signed-off-by: Emil Velikov --- include/drm/README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/README b/include/drm/README index a50b02c0..f3cdf5da 100644 --- a/include/drm/README +++ b/include/drm/README @@ -67,6 +67,8 @@ That said, it's up-to the individual developers to sync with newer version When and how to update these files ---------------------------------- +Note: One should not do _any_ changes to the files apart from the steps below. + In order to update the files do the following: - Switch to a Linux kernel tree/branch which is not rebased. For example: airlied/drm-next -- cgit v1.2.3-54-g00ecf From a6cdfa5cd8cc953ffec4497cd8262059c4b14675 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 3 Feb 2017 18:21:09 +0000 Subject: autogen.sh: don't print old git-config values Old values are of no interest to the user, so let's reduce the spam a bit by hiding those. Signed-off-by: Eric Engestrom Reviewed-by: Chad Versace Reviewed-by: Emil Velikov --- autogen.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/autogen.sh b/autogen.sh index d82ab180..d0030969 100755 --- a/autogen.sh +++ b/autogen.sh @@ -9,10 +9,10 @@ cd "$srcdir" autoreconf --force --verbose --install || exit 1 cd "$ORIGDIR" || exit $? -git config --local --get format.subjectPrefix || +git config --local --get format.subjectPrefix >/dev/null || git config --local format.subjectPrefix "PATCH libdrm" 2>/dev/null -git config --local --get sendemail.to || +git config --local --get sendemail.to >/dev/null || git config --local sendemail.to "dri-devel@lists.freedesktop.org" 2>/dev/null if test -z "$NOCONFIGURE"; then -- cgit v1.2.3-54-g00ecf From 1bf96af525436d3727d44d137fe922b491512b14 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 3 Feb 2017 18:21:10 +0000 Subject: autogen.sh: run git commands in the (potentially) git dir If the build dir is outside of the git dir, the order matters :) Signed-off-by: Eric Engestrom Reviewed-by: Chad Versace Reviewed-by: Emil Velikov --- autogen.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/autogen.sh b/autogen.sh index d0030969..13d6991e 100755 --- a/autogen.sh +++ b/autogen.sh @@ -6,15 +6,15 @@ test -z "$srcdir" && srcdir=. ORIGDIR=`pwd` cd "$srcdir" -autoreconf --force --verbose --install || exit 1 -cd "$ORIGDIR" || exit $? - git config --local --get format.subjectPrefix >/dev/null || git config --local format.subjectPrefix "PATCH libdrm" 2>/dev/null git config --local --get sendemail.to >/dev/null || git config --local sendemail.to "dri-devel@lists.freedesktop.org" 2>/dev/null +autoreconf --force --verbose --install || exit 1 +cd "$ORIGDIR" || exit $? + if test -z "$NOCONFIGURE"; then "$srcdir"/configure "$@" fi -- cgit v1.2.3-54-g00ecf From 5ee9cb4b4b6964bcd463b0490f3027e6ccfbf45a Mon Sep 17 00:00:00 2001 From: Thomas Hindoe Paaboel Andersen Date: Thu, 2 Feb 2017 23:57:29 +0100 Subject: intel: avoid null pointer dereference Move the dereference after the null check. Fixes: 028715ee707469189505 ("intel: Avoid the need for most overflow checks by using a scratch page.") Reviewed-by: Eric Engestrom --- intel/intel_decode.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 803d2029..2721ffd7 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3899,7 +3899,7 @@ drm_intel_decode(struct drm_intel_decode *ctx) int ret; unsigned int index = 0; uint32_t devid; - int size = ctx->base_count * 4; + int size; void *temp; if (!ctx) @@ -3909,6 +3909,7 @@ drm_intel_decode(struct drm_intel_decode *ctx) * the batchbuffer. This lets us avoid a bunch of length * checking in statically sized packets. */ + size = ctx->base_count * 4; temp = malloc(size + 4096); memcpy(temp, ctx->base_data, size); memset((char *)temp + size, 0xd0, 4096); -- cgit v1.2.3-54-g00ecf From 19c4cfc54918d361f2535aec16650e9f0be667cd Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 8 Mar 2017 21:00:59 +0000 Subject: intel: Add handle to hashtable before freeing along an error path drm_intel_gem_bo_free() unconditionally attempts to remove the handle from the hashtable. This goes horribly wrong if we haven't already added the bo to the hashtable. Reported-by: Michael Thayer Signed-off-by: Chris Wilson --- intel/intel_bufmgr_gem.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index b1e69070..e260f2dc 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -815,6 +815,10 @@ retry: } bo_gem->gem_handle = create.handle; + HASH_ADD(handle_hh, bufmgr_gem->handle_table, + gem_handle, sizeof(bo_gem->gem_handle), + bo_gem); + bo_gem->bo.handle = bo_gem->gem_handle; bo_gem->bo.bufmgr = bufmgr; bo_gem->bo.align = alignment; @@ -827,10 +831,6 @@ retry: tiling_mode, stride)) goto err_free; - - HASH_ADD(handle_hh, bufmgr_gem->handle_table, - gem_handle, sizeof(bo_gem->gem_handle), - bo_gem); } bo_gem->name = name; -- cgit v1.2.3-54-g00ecf From 2b7453f47862b0ae8032ba269b40830a34a6fb43 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 21 Mar 2017 10:01:02 -0400 Subject: freedreno: fix potential use-after-free on a5xx+ Something that valgrind spotted: ==8441== Invalid read of size 4 ==8441== at 0x5DEE168: msm_ringbuffer_emit_reloc (msm_ringbuffer.c:506) ==8441== by 0x5B48F0F: OUT_RELOCW (freedreno_util.h:241) ==8441== by 0x5B48F0F: fd5_emit_blit (fd5_emit.h:131) ==8441== by 0x5B48F0F: emit_gmem2mem_surf.isra.12 (fd5_gmem.c:450) ==8441== by 0x5B4910F: fd5_emit_tile_gmem2mem (fd5_gmem.c:477) ==8441== by 0x5B14943: render_tiles (freedreno_gmem.c:342) ==8441== by 0x5B14943: fd_gmem_render_tiles (freedreno_gmem.c:416) ==8441== by 0x5B0FBA7: batch_flush (freedreno_batch.c:281) ==8441== by 0x5B0FBA7: fd_batch_flush (freedreno_batch.c:306) ==8441== by 0x5B11FE7: fd_context_flush (freedreno_context.c:52) ==8441== by 0x58AD783: st_glFlush (st_cb_flush.c:121) ==8441== by 0x5751EE7: _mesa_make_current (context.c:1652) ==8441== by 0x58E6A97: st_api_make_current (st_manager.c:811) ==8441== by 0x5A2CE43: dri_unbind_context (dri_context.c:207) ==8441== by 0x5A2C77F: driUnbindContext (dri_util.c:589) ==8441== by 0x4AC8A67: MakeContextCurrent (glxcurrent.c:214) ==8441== Address 0x6f5eb1c is 204 bytes inside a block of size 240 free'd ==8441== at 0x4868F44: realloc (vg_replace_malloc.c:785) ==8441== by 0x5DEE143: msm_ringbuffer_emit_reloc (msm_ringbuffer.c:502) ==8441== by 0x5B48F0F: OUT_RELOCW (freedreno_util.h:241) ==8441== by 0x5B48F0F: fd5_emit_blit (fd5_emit.h:131) ==8441== by 0x5B48F0F: emit_gmem2mem_surf.isra.12 (fd5_gmem.c:450) ==8441== by 0x5B4910F: fd5_emit_tile_gmem2mem (fd5_gmem.c:477) ==8441== by 0x5B14943: render_tiles (freedreno_gmem.c:342) ==8441== by 0x5B14943: fd_gmem_render_tiles (freedreno_gmem.c:416) ==8441== by 0x5B0FBA7: batch_flush (freedreno_batch.c:281) ==8441== by 0x5B0FBA7: fd_batch_flush (freedreno_batch.c:306) ==8441== by 0x5B11FE7: fd_context_flush (freedreno_context.c:52) ==8441== by 0x58AD783: st_glFlush (st_cb_flush.c:121) ==8441== by 0x5751EE7: _mesa_make_current (context.c:1652) ==8441== by 0x58E6A97: st_api_make_current (st_manager.c:811) ==8441== by 0x5A2CE43: dri_unbind_context (dri_context.c:207) ==8441== by 0x5A2C77F: driUnbindContext (dri_util.c:589) ==8441== Block was alloc'd at ==8441== at 0x4868F44: realloc (vg_replace_malloc.c:785) ==8441== by 0x5DEE08B: msm_ringbuffer_emit_reloc (msm_ringbuffer.c:481) ==8441== by 0x5B48F0F: OUT_RELOCW (freedreno_util.h:241) ==8441== by 0x5B48F0F: fd5_emit_blit (fd5_emit.h:131) ==8441== by 0x5B48F0F: emit_gmem2mem_surf.isra.12 (fd5_gmem.c:450) ==8441== by 0x5B4909F: fd5_emit_tile_gmem2mem (fd5_gmem.c:465) ==8441== by 0x5B14943: render_tiles (freedreno_gmem.c:342) ==8441== by 0x5B14943: fd_gmem_render_tiles (freedreno_gmem.c:416) ==8441== by 0x5B0FBA7: batch_flush (freedreno_batch.c:281) ==8441== by 0x5B0FBA7: fd_batch_flush (freedreno_batch.c:306) ==8441== by 0x5B11FE7: fd_context_flush (freedreno_context.c:52) ==8441== by 0x58AD783: st_glFlush (st_cb_flush.c:121) ==8441== by 0x5751EE7: _mesa_make_current (context.c:1652) ==8441== by 0x58E6A97: st_api_make_current (st_manager.c:811) ==8441== by 0x5A2CE43: dri_unbind_context (dri_context.c:207) ==8441== by 0x5A2C77F: driUnbindContext (dri_util.c:589) Signed-off-by: Rob Clark --- freedreno/msm/msm_ringbuffer.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index 17194f4c..c3b2eded 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c @@ -496,11 +496,16 @@ static void msm_ringbuffer_emit_reloc(struct fd_ringbuffer *ring, if (ring->pipe->gpu_id >= 500) { struct drm_msm_gem_submit_reloc *reloc_hi; + /* NOTE: grab reloc_idx *before* APPEND() since that could + * realloc() meaning that 'reloc' ptr is no longer valid: + */ + uint32_t reloc_idx = reloc->reloc_idx; + idx = APPEND(cmd, relocs); reloc_hi = &cmd->relocs[idx]; - reloc_hi->reloc_idx = reloc->reloc_idx; + reloc_hi->reloc_idx = reloc_idx; reloc_hi->reloc_offset = r->offset; reloc_hi->or = r->orhi; reloc_hi->shift = r->shift - 32; -- cgit v1.2.3-54-g00ecf From b983b054d4f1a6be67105e90f0ae2064f91a762c Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Thu, 23 Mar 2017 12:07:03 -0400 Subject: configure: Explicitly check for pkg-config at the top level If you don't, then the first place the m4 expands is: if test "x$INTEL" != "xno"; then PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10]) fi So on non-Intel architectures we never find it in the path, and all subsequent PKG_CHECK_MODULESes fail. Boo autoconf. Signed-off-by: Adam Jackson --- configure.ac | 1 + 1 file changed, 1 insertion(+) diff --git a/configure.ac b/configure.ac index 8e593324..2e50d3ef 100644 --- a/configure.ac +++ b/configure.ac @@ -28,6 +28,7 @@ AC_CONFIG_HEADERS([config.h]) AC_CONFIG_SRCDIR([Makefile.am]) AC_CONFIG_MACRO_DIR([m4]) AC_CONFIG_AUX_DIR([build-aux]) +PKG_PROG_PKG_CONFIG # Require xorg-macros minimum of 1.12 for XORG_WITH_XSLTPROC m4_ifndef([XORG_MACROS_VERSION], -- cgit v1.2.3-54-g00ecf From d0dae26ca4e743933f50c1bf4a742e0db8e1994b Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 21 Mar 2017 19:44:57 -0400 Subject: freedreno: valgrind support Signed-off-by: Rob Clark --- freedreno/Makefile.am | 1 + freedreno/freedreno_bo.c | 12 ++++++++- freedreno/freedreno_bo_cache.c | 4 ++- freedreno/freedreno_priv.h | 56 ++++++++++++++++++++++++++++++++++++++++++ freedreno/kgsl/kgsl_device.c | 2 ++ freedreno/msm/msm_device.c | 2 ++ 6 files changed, 75 insertions(+), 2 deletions(-) diff --git a/freedreno/Makefile.am b/freedreno/Makefile.am index 0771d146..cbb0d031 100644 --- a/freedreno/Makefile.am +++ b/freedreno/Makefile.am @@ -5,6 +5,7 @@ AM_CFLAGS = \ $(WARN_CFLAGS) \ -I$(top_srcdir) \ $(PTHREADSTUBS_CFLAGS) \ + $(VALGRIND_CFLAGS) \ -I$(top_srcdir)/include/drm libdrm_freedreno_la_LTLIBRARIES = libdrm_freedreno.la diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index 996d6b95..10949ebf 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -102,6 +102,8 @@ fd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags) bo->bo_reuse = TRUE; pthread_mutex_unlock(&table_lock); + VG_BO_ALLOC(bo); + return bo; } @@ -118,6 +120,8 @@ fd_bo_from_handle(struct fd_device *dev, uint32_t handle, uint32_t size) bo = bo_from_handle(dev, size, handle); + VG_BO_ALLOC(bo); + out_unlock: pthread_mutex_unlock(&table_lock); @@ -147,6 +151,8 @@ fd_bo_from_dmabuf(struct fd_device *dev, int fd) bo = bo_from_handle(dev, size, handle); + VG_BO_ALLOC(bo); + out_unlock: pthread_mutex_unlock(&table_lock); @@ -177,8 +183,10 @@ struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name) goto out_unlock; bo = bo_from_handle(dev, req.size, req.handle); - if (bo) + if (bo) { set_name(bo, name); + VG_BO_ALLOC(bo); + } out_unlock: pthread_mutex_unlock(&table_lock); @@ -213,6 +221,8 @@ out: /* Called under table_lock */ drm_private void bo_del(struct fd_bo *bo) { + VG_BO_FREE(bo); + if (bo->map) drm_munmap(bo->map, bo->size); diff --git a/freedreno/freedreno_bo_cache.c b/freedreno/freedreno_bo_cache.c index 7becb0d6..d922f3a9 100644 --- a/freedreno/freedreno_bo_cache.c +++ b/freedreno/freedreno_bo_cache.c @@ -33,7 +33,6 @@ #include "freedreno_drmif.h" #include "freedreno_priv.h" - drm_private void bo_del(struct fd_bo *bo); drm_private extern pthread_mutex_t table_lock; @@ -102,6 +101,7 @@ fd_bo_cache_cleanup(struct fd_bo_cache *cache, time_t time) if (time && ((time - bo->free_time) <= 1)) break; + VG_BO_OBTAIN(bo); list_del(&bo->list); bo_del(bo); } @@ -177,6 +177,7 @@ retry: *size = bucket->size; bo = find_in_bucket(bucket, flags); if (bo) { + VG_BO_OBTAIN(bo); if (bo->funcs->madvise(bo, TRUE) <= 0) { /* we've lost the backing pages, delete and try again: */ pthread_mutex_lock(&table_lock); @@ -207,6 +208,7 @@ fd_bo_cache_free(struct fd_bo_cache *cache, struct fd_bo *bo) clock_gettime(CLOCK_MONOTONIC, &time); bo->free_time = time.tv_sec; + VG_BO_RELEASE(bo); list_addtail(&bo->list, &bucket->list); fd_bo_cache_cleanup(cache, time.tv_sec); diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index 32170391..8dd3ee69 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -102,6 +102,9 @@ struct fd_device { struct fd_bo_cache bo_cache; int closefd; /* call close(fd) upon destruction */ + + /* just for valgrind: */ + int bo_size; }; drm_private void fd_bo_cache_init(struct fd_bo_cache *cache, int coarse); @@ -196,4 +199,57 @@ offset_bytes(void *end, void *start) return ((char *)end) - ((char *)start); } +#ifdef HAVE_VALGRIND +# include + +/* + * For tracking the backing memory (if valgrind enabled, we force a mmap + * for the purposes of tracking) + */ +static inline void VG_BO_ALLOC(struct fd_bo *bo) +{ + if (bo && RUNNING_ON_VALGRIND) { + VALGRIND_MALLOCLIKE_BLOCK(fd_bo_map(bo), bo->size, 0, 1); + } +} + +static inline void VG_BO_FREE(struct fd_bo *bo) +{ + VALGRIND_FREELIKE_BLOCK(bo->map, 0); +} + +/* + * For tracking bo structs that are in the buffer-cache, so that valgrind + * doesn't attribute ownership to the first one to allocate the recycled + * bo. + * + * Note that the list_head in fd_bo is used to track the buffers in cache + * so disable error reporting on the range while they are in cache so + * valgrind doesn't squawk about list traversal. + * + */ +static inline void VG_BO_RELEASE(struct fd_bo *bo) +{ + if (RUNNING_ON_VALGRIND) { + VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size); + VALGRIND_MAKE_MEM_NOACCESS(bo, bo->dev->bo_size); + VALGRIND_FREELIKE_BLOCK(bo->map, 0); + } +} +static inline void VG_BO_OBTAIN(struct fd_bo *bo) +{ + if (RUNNING_ON_VALGRIND) { + VALGRIND_MAKE_MEM_DEFINED(bo, bo->dev->bo_size); + VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size); + VALGRIND_MALLOCLIKE_BLOCK(bo->map, bo->size, 0, 1); + } +} +#else +static inline void VG_BO_ALLOC(struct fd_bo *bo) {} +static inline void VG_BO_FREE(struct fd_bo *bo) {} +static inline void VG_BO_RELEASE(struct fd_bo *bo) {} +static inline void VG_BO_OBTAIN(struct fd_bo *bo) {} +#endif + + #endif /* FREEDRENO_PRIV_H_ */ diff --git a/freedreno/kgsl/kgsl_device.c b/freedreno/kgsl/kgsl_device.c index 175e8378..958e8a72 100644 --- a/freedreno/kgsl/kgsl_device.c +++ b/freedreno/kgsl/kgsl_device.c @@ -61,5 +61,7 @@ drm_private struct fd_device * kgsl_device_new(int fd) dev = &kgsl_dev->base; dev->funcs = &funcs; + dev->bo_size = sizeof(struct kgsl_bo); + return dev; } diff --git a/freedreno/msm/msm_device.c b/freedreno/msm/msm_device.c index 727baa44..c454938d 100644 --- a/freedreno/msm/msm_device.c +++ b/freedreno/msm/msm_device.c @@ -64,5 +64,7 @@ drm_private struct fd_device * msm_device_new(int fd) fd_bo_cache_init(&msm_dev->ring_cache, TRUE); + dev->bo_size = sizeof(struct msm_bo); + return dev; } -- cgit v1.2.3-54-g00ecf From a07ae97c75ca45c08327b53df5d8d53e56a46a8a Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 23 Mar 2017 14:58:38 -0400 Subject: freedreno: fix device close issues Move closing the fd to after subclass ->destroy() (since it might want to delete gem bo's, etc), and actually free() the fd_device object. Signed-off-by: Rob Clark --- freedreno/freedreno_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c index fcbf1402..dba7ec47 100644 --- a/freedreno/freedreno_device.c +++ b/freedreno/freedreno_device.c @@ -115,9 +115,10 @@ static void fd_device_del_impl(struct fd_device *dev) fd_bo_cache_cleanup(&dev->bo_cache, 0); drmHashDestroy(dev->handle_table); drmHashDestroy(dev->name_table); + dev->funcs->destroy(dev); if (dev->closefd) close(dev->fd); - dev->funcs->destroy(dev); + free(dev); } drm_private void fd_device_del_locked(struct fd_device *dev) -- cgit v1.2.3-54-g00ecf From 3dc002df3e5607a3ae0a194b35e1f2fb2cd36697 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 21 Mar 2017 20:31:53 +0100 Subject: amdgpu: sync amdgpu_drm.h with kernel 4.11-rc2 Reviewed-by: Alex Deucher --- include/drm/amdgpu_drm.h | 396 ++++++++++++++++++++++++++++++----------------- 1 file changed, 251 insertions(+), 145 deletions(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index d8f24976..5797283c 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -50,6 +50,7 @@ extern "C" { #define DRM_AMDGPU_WAIT_CS 0x09 #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 +#define DRM_AMDGPU_WAIT_FENCES 0x12 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -63,6 +64,7 @@ extern "C" { #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) +#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -79,22 +81,26 @@ extern "C" { #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) /* Flag that the memory should be in VRAM and cleared */ #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) +/* Flag that create shadow bo(GTT) while allocating vram bo */ +#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) +/* Flag that allocating the BO should use linear VRAM */ +#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) struct drm_amdgpu_gem_create_in { /** the requested memory size */ - uint64_t bo_size; + __u64 bo_size; /** physical start_addr alignment in bytes for some HW requirements */ - uint64_t alignment; + __u64 alignment; /** the requested memory domains */ - uint64_t domains; + __u64 domains; /** allocation flags */ - uint64_t domain_flags; + __u64 domain_flags; }; struct drm_amdgpu_gem_create_out { /** returned GEM object handle */ - uint32_t handle; - uint32_t _pad; + __u32 handle; + __u32 _pad; }; union drm_amdgpu_gem_create { @@ -111,28 +117,28 @@ union drm_amdgpu_gem_create { struct drm_amdgpu_bo_list_in { /** Type of operation */ - uint32_t operation; + __u32 operation; /** Handle of list or 0 if we want to create one */ - uint32_t list_handle; + __u32 list_handle; /** Number of BOs in list */ - uint32_t bo_number; + __u32 bo_number; /** Size of each element describing BO */ - uint32_t bo_info_size; + __u32 bo_info_size; /** Pointer to array describing BOs */ - uint64_t bo_info_ptr; + __u64 bo_info_ptr; }; struct drm_amdgpu_bo_list_entry { /** Handle of BO */ - uint32_t bo_handle; + __u32 bo_handle; /** New (if specified) BO priority to be used during migration */ - uint32_t bo_priority; + __u32 bo_priority; }; struct drm_amdgpu_bo_list_out { /** Handle of resource list */ - uint32_t list_handle; - uint32_t _pad; + __u32 list_handle; + __u32 _pad; }; union drm_amdgpu_bo_list { @@ -156,26 +162,26 @@ union drm_amdgpu_bo_list { struct drm_amdgpu_ctx_in { /** AMDGPU_CTX_OP_* */ - uint32_t op; + __u32 op; /** For future use, no flags defined so far */ - uint32_t flags; - uint32_t ctx_id; - uint32_t _pad; + __u32 flags; + __u32 ctx_id; + __u32 _pad; }; union drm_amdgpu_ctx_out { struct { - uint32_t ctx_id; - uint32_t _pad; + __u32 ctx_id; + __u32 _pad; } alloc; struct { /** For future use, no flags defined so far */ - uint64_t flags; + __u64 flags; /** Number of resets caused by this context so far. */ - uint32_t hangs; + __u32 hangs; /** Reset status since the last call of the ioctl. */ - uint32_t reset_status; + __u32 reset_status; } state; }; @@ -195,12 +201,12 @@ union drm_amdgpu_ctx { #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) struct drm_amdgpu_gem_userptr { - uint64_t addr; - uint64_t size; + __u64 addr; + __u64 size; /* AMDGPU_GEM_USERPTR_* */ - uint32_t flags; + __u32 flags; /* Resulting GEM handle */ - uint32_t handle; + __u32 handle; }; /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ @@ -232,28 +238,28 @@ struct drm_amdgpu_gem_userptr { /** The same structure is shared for input/output */ struct drm_amdgpu_gem_metadata { /** GEM Object handle */ - uint32_t handle; + __u32 handle; /** Do we want get or set metadata */ - uint32_t op; + __u32 op; struct { /** For future use, no flags defined so far */ - uint64_t flags; + __u64 flags; /** family specific tiling info */ - uint64_t tiling_info; - uint32_t data_size_bytes; - uint32_t data[64]; + __u64 tiling_info; + __u32 data_size_bytes; + __u32 data[64]; } data; }; struct drm_amdgpu_gem_mmap_in { /** the GEM object handle */ - uint32_t handle; - uint32_t _pad; + __u32 handle; + __u32 _pad; }; struct drm_amdgpu_gem_mmap_out { /** mmap offset from the vma offset manager */ - uint64_t addr_ptr; + __u64 addr_ptr; }; union drm_amdgpu_gem_mmap { @@ -263,18 +269,18 @@ union drm_amdgpu_gem_mmap { struct drm_amdgpu_gem_wait_idle_in { /** GEM object handle */ - uint32_t handle; + __u32 handle; /** For future use, no flags defined so far */ - uint32_t flags; + __u32 flags; /** Absolute timeout to wait */ - uint64_t timeout; + __u64 timeout; }; struct drm_amdgpu_gem_wait_idle_out { /** BO status: 0 - BO is idle, 1 - BO is busy */ - uint32_t status; + __u32 status; /** Returned current memory domain */ - uint32_t domain; + __u32 domain; }; union drm_amdgpu_gem_wait_idle { @@ -284,18 +290,18 @@ union drm_amdgpu_gem_wait_idle { struct drm_amdgpu_wait_cs_in { /** Command submission handle */ - uint64_t handle; + __u64 handle; /** Absolute timeout to wait */ - uint64_t timeout; - uint32_t ip_type; - uint32_t ip_instance; - uint32_t ring; - uint32_t ctx_id; + __u64 timeout; + __u32 ip_type; + __u32 ip_instance; + __u32 ring; + __u32 ctx_id; }; struct drm_amdgpu_wait_cs_out { /** CS status: 0 - CS completed, 1 - CS still busy */ - uint64_t status; + __u64 status; }; union drm_amdgpu_wait_cs { @@ -303,17 +309,43 @@ union drm_amdgpu_wait_cs { struct drm_amdgpu_wait_cs_out out; }; +struct drm_amdgpu_fence { + __u32 ctx_id; + __u32 ip_type; + __u32 ip_instance; + __u32 ring; + __u64 seq_no; +}; + +struct drm_amdgpu_wait_fences_in { + /** This points to uint64_t * which points to fences */ + __u64 fences; + __u32 fence_count; + __u32 wait_all; + __u64 timeout_ns; +}; + +struct drm_amdgpu_wait_fences_out { + __u32 status; + __u32 first_signaled; +}; + +union drm_amdgpu_wait_fences { + struct drm_amdgpu_wait_fences_in in; + struct drm_amdgpu_wait_fences_out out; +}; + #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 /* Sets or returns a value associated with a buffer. */ struct drm_amdgpu_gem_op { /** GEM object handle */ - uint32_t handle; + __u32 handle; /** AMDGPU_GEM_OP_* */ - uint32_t op; + __u32 op; /** Input or return value */ - uint64_t value; + __u64 value; }; #define AMDGPU_VA_OP_MAP 1 @@ -332,18 +364,18 @@ struct drm_amdgpu_gem_op { struct drm_amdgpu_gem_va { /** GEM object handle */ - uint32_t handle; - uint32_t _pad; + __u32 handle; + __u32 _pad; /** AMDGPU_VA_OP_* */ - uint32_t operation; + __u32 operation; /** AMDGPU_VM_PAGE_* */ - uint32_t flags; + __u32 flags; /** va address to assign . Must be correctly aligned.*/ - uint64_t va_address; + __u64 va_address; /** Specify offset inside of BO to assign. Must be correctly aligned.*/ - uint64_t offset_in_bo; + __u64 offset_in_bo; /** Specify mapping size. Must be correctly aligned. */ - uint64_t map_size; + __u64 map_size; }; #define AMDGPU_HW_IP_GFX 0 @@ -360,24 +392,24 @@ struct drm_amdgpu_gem_va { #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 struct drm_amdgpu_cs_chunk { - uint32_t chunk_id; - uint32_t length_dw; - uint64_t chunk_data; + __u32 chunk_id; + __u32 length_dw; + __u64 chunk_data; }; struct drm_amdgpu_cs_in { /** Rendering context id */ - uint32_t ctx_id; + __u32 ctx_id; /** Handle of resource list associated with CS */ - uint32_t bo_list_handle; - uint32_t num_chunks; - uint32_t _pad; - /** this points to uint64_t * which point to cs chunks */ - uint64_t chunks; + __u32 bo_list_handle; + __u32 num_chunks; + __u32 _pad; + /** this points to __u64 * which point to cs chunks */ + __u64 chunks; }; struct drm_amdgpu_cs_out { - uint64_t handle; + __u64 handle; }; union drm_amdgpu_cs { @@ -394,32 +426,32 @@ union drm_amdgpu_cs { #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) struct drm_amdgpu_cs_chunk_ib { - uint32_t _pad; + __u32 _pad; /** AMDGPU_IB_FLAG_* */ - uint32_t flags; + __u32 flags; /** Virtual address to begin IB execution */ - uint64_t va_start; + __u64 va_start; /** Size of submission */ - uint32_t ib_bytes; + __u32 ib_bytes; /** HW IP to submit to */ - uint32_t ip_type; + __u32 ip_type; /** HW IP index of the same type to submit to */ - uint32_t ip_instance; + __u32 ip_instance; /** Ring index to submit to */ - uint32_t ring; + __u32 ring; }; struct drm_amdgpu_cs_chunk_dep { - uint32_t ip_type; - uint32_t ip_instance; - uint32_t ring; - uint32_t ctx_id; - uint64_t handle; + __u32 ip_type; + __u32 ip_instance; + __u32 ring; + __u32 ctx_id; + __u64 handle; }; struct drm_amdgpu_cs_chunk_fence { - uint32_t handle; - uint32_t offset; + __u32 handle; + __u32 offset; }; struct drm_amdgpu_cs_chunk_data { @@ -434,6 +466,7 @@ struct drm_amdgpu_cs_chunk_data { * */ #define AMDGPU_IDS_FLAGS_FUSION 0x1 +#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 @@ -483,6 +516,20 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_DEV_INFO 0x16 /* visible vram usage */ #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 +/* number of TTM buffer evictions */ +#define AMDGPU_INFO_NUM_EVICTIONS 0x18 +/* Query memory about VRAM and GTT domains */ +#define AMDGPU_INFO_MEMORY 0x19 +/* Query vce clock table */ +#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A +/* Query vbios related information */ +#define AMDGPU_INFO_VBIOS 0x1B + /* Subquery id: Query vbios size */ + #define AMDGPU_INFO_VBIOS_SIZE 0x1 + /* Subquery id: Query vbios image */ + #define AMDGPU_INFO_VBIOS_IMAGE 0x2 +/* Query UVD handles */ +#define AMDGPU_INFO_NUM_HANDLES 0x1C #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -491,86 +538,119 @@ struct drm_amdgpu_cs_chunk_data { struct drm_amdgpu_query_fw { /** AMDGPU_INFO_FW_* */ - uint32_t fw_type; + __u32 fw_type; /** * Index of the IP if there are more IPs of * the same type. */ - uint32_t ip_instance; + __u32 ip_instance; /** * Index of the engine. Whether this is used depends * on the firmware type. (e.g. MEC, SDMA) */ - uint32_t index; - uint32_t _pad; + __u32 index; + __u32 _pad; }; /* Input structure for the INFO ioctl */ struct drm_amdgpu_info { /* Where the return value will be stored */ - uint64_t return_pointer; + __u64 return_pointer; /* The size of the return value. Just like "size" in "snprintf", * it limits how many bytes the kernel can write. */ - uint32_t return_size; + __u32 return_size; /* The query request id. */ - uint32_t query; + __u32 query; union { struct { - uint32_t id; - uint32_t _pad; + __u32 id; + __u32 _pad; } mode_crtc; struct { /** AMDGPU_HW_IP_* */ - uint32_t type; + __u32 type; /** * Index of the IP if there are more IPs of the same * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. */ - uint32_t ip_instance; + __u32 ip_instance; } query_hw_ip; struct { - uint32_t dword_offset; + __u32 dword_offset; /** number of registers to read */ - uint32_t count; - uint32_t instance; + __u32 count; + __u32 instance; /** For future use, no flags defined so far */ - uint32_t flags; + __u32 flags; } read_mmr_reg; struct drm_amdgpu_query_fw query_fw; + + struct { + __u32 type; + __u32 offset; + } vbios_info; }; }; struct drm_amdgpu_info_gds { /** GDS GFX partition size */ - uint32_t gds_gfx_partition_size; + __u32 gds_gfx_partition_size; /** GDS compute partition size */ - uint32_t compute_partition_size; + __u32 compute_partition_size; /** total GDS memory size */ - uint32_t gds_total_size; + __u32 gds_total_size; /** GWS size per GFX partition */ - uint32_t gws_per_gfx_partition; + __u32 gws_per_gfx_partition; /** GSW size per compute partition */ - uint32_t gws_per_compute_partition; + __u32 gws_per_compute_partition; /** OA size per GFX partition */ - uint32_t oa_per_gfx_partition; + __u32 oa_per_gfx_partition; /** OA size per compute partition */ - uint32_t oa_per_compute_partition; - uint32_t _pad; + __u32 oa_per_compute_partition; + __u32 _pad; }; struct drm_amdgpu_info_vram_gtt { - uint64_t vram_size; - uint64_t vram_cpu_accessible_size; - uint64_t gtt_size; + __u64 vram_size; + __u64 vram_cpu_accessible_size; + __u64 gtt_size; +}; + +struct drm_amdgpu_heap_info { + /** max. physical memory */ + __u64 total_heap_size; + + /** Theoretical max. available memory in the given heap */ + __u64 usable_heap_size; + + /** + * Number of bytes allocated in the heap. This includes all processes + * and private allocations in the kernel. It changes when new buffers + * are allocated, freed, and moved. It cannot be larger than + * heap_size. + */ + __u64 heap_usage; + + /** + * Theoretical possible max. size of buffer which + * could be allocated in the given heap + */ + __u64 max_allocation; +}; + +struct drm_amdgpu_memory_info { + struct drm_amdgpu_heap_info vram; + struct drm_amdgpu_heap_info cpu_accessible_vram; + struct drm_amdgpu_heap_info gtt; }; struct drm_amdgpu_info_firmware { - uint32_t ver; - uint32_t feature; + __u32 ver; + __u32 feature; }; #define AMDGPU_VRAM_TYPE_UNKNOWN 0 @@ -584,67 +664,93 @@ struct drm_amdgpu_info_firmware { struct drm_amdgpu_info_device { /** PCI Device ID */ - uint32_t device_id; + __u32 device_id; /** Internal chip revision: A0, A1, etc.) */ - uint32_t chip_rev; - uint32_t external_rev; + __u32 chip_rev; + __u32 external_rev; /** Revision id in PCI Config space */ - uint32_t pci_rev; - uint32_t family; - uint32_t num_shader_engines; - uint32_t num_shader_arrays_per_engine; + __u32 pci_rev; + __u32 family; + __u32 num_shader_engines; + __u32 num_shader_arrays_per_engine; /* in KHz */ - uint32_t gpu_counter_freq; - uint64_t max_engine_clock; - uint64_t max_memory_clock; + __u32 gpu_counter_freq; + __u64 max_engine_clock; + __u64 max_memory_clock; /* cu information */ - uint32_t cu_active_number; - uint32_t cu_ao_mask; - uint32_t cu_bitmap[4][4]; + __u32 cu_active_number; + __u32 cu_ao_mask; + __u32 cu_bitmap[4][4]; /** Render backend pipe mask. One render backend is CB+DB. */ - uint32_t enabled_rb_pipes_mask; - uint32_t num_rb_pipes; - uint32_t num_hw_gfx_contexts; - uint32_t _pad; - uint64_t ids_flags; + __u32 enabled_rb_pipes_mask; + __u32 num_rb_pipes; + __u32 num_hw_gfx_contexts; + __u32 _pad; + __u64 ids_flags; /** Starting virtual address for UMDs. */ - uint64_t virtual_address_offset; + __u64 virtual_address_offset; /** The maximum virtual address */ - uint64_t virtual_address_max; + __u64 virtual_address_max; /** Required alignment of virtual addresses. */ - uint32_t virtual_address_alignment; + __u32 virtual_address_alignment; /** Page table entry - fragment size */ - uint32_t pte_fragment_size; - uint32_t gart_page_size; + __u32 pte_fragment_size; + __u32 gart_page_size; /** constant engine ram size*/ - uint32_t ce_ram_size; + __u32 ce_ram_size; /** video memory type info*/ - uint32_t vram_type; + __u32 vram_type; /** video memory bit width*/ - uint32_t vram_bit_width; + __u32 vram_bit_width; /* vce harvesting instance */ - uint32_t vce_harvest_config; + __u32 vce_harvest_config; }; struct drm_amdgpu_info_hw_ip { /** Version of h/w IP */ - uint32_t hw_ip_version_major; - uint32_t hw_ip_version_minor; + __u32 hw_ip_version_major; + __u32 hw_ip_version_minor; /** Capabilities */ - uint64_t capabilities_flags; + __u64 capabilities_flags; /** command buffer address start alignment*/ - uint32_t ib_start_alignment; + __u32 ib_start_alignment; /** command buffer size alignment*/ - uint32_t ib_size_alignment; + __u32 ib_size_alignment; /** Bitmask of available rings. Bit 0 means ring 0, etc. */ - uint32_t available_rings; - uint32_t _pad; + __u32 available_rings; + __u32 _pad; +}; + +struct drm_amdgpu_info_num_handles { + /** Max handles as supported by firmware for UVD */ + __u32 uvd_max_handles; + /** Handles currently in use for UVD */ + __u32 uvd_used_handles; +}; + +#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 + +struct drm_amdgpu_info_vce_clock_table_entry { + /** System clock */ + __u32 sclk; + /** Memory clock */ + __u32 mclk; + /** VCE clock */ + __u32 eclk; + __u32 pad; +}; + +struct drm_amdgpu_info_vce_clock_table { + struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; + __u32 num_valid_entries; + __u32 pad; }; /* * Supported GPU families */ #define AMDGPU_FAMILY_UNKNOWN 0 +#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ -- cgit v1.2.3-54-g00ecf From c34b28ae9bac7a20e60482a2bf72f16ad5e28c67 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 21 Mar 2017 20:14:45 +0100 Subject: amdgpu: update amdgpu_drm.h for Vega10 Reviewed-by: Alex Deucher --- include/drm/amdgpu_drm.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 5797283c..1e25a87d 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -209,6 +209,7 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; +/* SI-CI-VI: */ /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf @@ -227,10 +228,14 @@ struct drm_amdgpu_gem_userptr { #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 +/* GFX9 and later: */ +#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 +#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f + #define AMDGPU_TILING_SET(field, value) \ - (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) + (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) #define AMDGPU_TILING_GET(value, field) \ - (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) + (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 @@ -755,6 +760,7 @@ struct drm_amdgpu_info_vce_clock_table { #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ +#define AMDGPU_FAMILY_AI 141 /* Vega10 */ #if defined(__cplusplus) } -- cgit v1.2.3-54-g00ecf From 99908bfd4ce3132e99aabc96c1ee4946b1246fa5 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Tue, 8 Nov 2016 14:00:45 +0800 Subject: amdgpu: don't read registers not present on Vega10 Reviewed-by: Alex Deucher --- amdgpu/amdgpu_gpu_info.c | 48 ++++++++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index 66c7e0e1..cd31e1b0 100644 --- a/amdgpu/amdgpu_gpu_info.c +++ b/amdgpu/amdgpu_gpu_info.c @@ -182,40 +182,44 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) dev->info.backend_disable[i] = (dev->info.backend_disable[i] >> 16) & 0xff; - r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0, - &dev->info.pa_sc_raster_cfg[i]); - if (r) - return r; - - if (dev->info.family_id >= AMDGPU_FAMILY_CI) { - r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0, - &dev->info.pa_sc_raster_cfg1[i]); + if (dev->info.family_id < AMDGPU_FAMILY_AI) { + r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0, + &dev->info.pa_sc_raster_cfg[i]); if (r) return r; + + if (dev->info.family_id >= AMDGPU_FAMILY_CI) { + r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0, + &dev->info.pa_sc_raster_cfg1[i]); + if (r) + return r; + } } } - r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0, - dev->info.gb_tile_mode); + r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0, + &dev->info.gb_addr_cfg); if (r) return r; - if (dev->info.family_id >= AMDGPU_FAMILY_CI) { - r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0, - dev->info.gb_macro_tile_mode); + if (dev->info.family_id < AMDGPU_FAMILY_AI) { + r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0, + dev->info.gb_tile_mode); if (r) return r; - } - r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0, - &dev->info.gb_addr_cfg); - if (r) - return r; + if (dev->info.family_id >= AMDGPU_FAMILY_CI) { + r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0, + dev->info.gb_macro_tile_mode); + if (r) + return r; + } - r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0, - &dev->info.mc_arb_ramcfg); - if (r) - return r; + r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0, + &dev->info.mc_arb_ramcfg); + if (r) + return r; + } dev->info.cu_active_number = dev->dev_info.cu_active_number; dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask; -- cgit v1.2.3-54-g00ecf From fee173dc77295c8624291a4336075361d5dafd67 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Wed, 9 Nov 2016 11:28:45 +0800 Subject: tests/amdgpu: fix the count number for vega10 Signed-off-by: Huang Rui Reviewed-by: Ken Wang Reviewed-by: Christian König Reviewed-by: Alex Deucher --- tests/amdgpu/basic_tests.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index bfda21b1..4dce67e9 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -803,12 +803,16 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) uint32_t *pm4; struct amdgpu_cs_ib_info *ib_info; struct amdgpu_cs_request *ibs_request; + struct amdgpu_gpu_info gpu_info = {0}; uint64_t bo_mc; volatile uint32_t *bo_cpu; int i, j, r, loop; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -848,7 +852,10 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) SDMA_WRITE_SUB_OPCODE_LINEAR, 0); pm4[i++] = 0xffffffff & bo_mc; pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; + if (gpu_info.family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; while(j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; } else if ((ip_type == AMDGPU_HW_IP_GFX) || @@ -904,12 +911,16 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) uint32_t *pm4; struct amdgpu_cs_ib_info *ib_info; struct amdgpu_cs_request *ibs_request; + struct amdgpu_gpu_info gpu_info = {0}; uint64_t bo_mc; volatile uint32_t *bo_cpu; int i, j, r, loop; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -949,7 +960,10 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) pm4[i++] = 0xffffffff & bo_mc; pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; pm4[i++] = 0xdeadbeaf; - pm4[i++] = sdma_write_length; + if (gpu_info.family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; } else if ((ip_type == AMDGPU_HW_IP_GFX) || (ip_type == AMDGPU_HW_IP_COMPUTE)) { pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); @@ -1007,12 +1021,16 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) uint32_t *pm4; struct amdgpu_cs_ib_info *ib_info; struct amdgpu_cs_request *ibs_request; + struct amdgpu_gpu_info gpu_info = {0}; uint64_t bo1_mc, bo2_mc; volatile unsigned char *bo1_cpu, *bo2_cpu; int i, j, r, loop1, loop2; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle bo1_va_handle, bo2_va_handle; + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -1064,7 +1082,10 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) i = j = 0; if (ip_type == AMDGPU_HW_IP_DMA) { pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - pm4[i++] = sdma_write_length; + if (gpu_info.family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; pm4[i++] = 0; pm4[i++] = 0xffffffff & bo1_mc; pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; -- cgit v1.2.3-54-g00ecf From 5a44f9e6c6a460a5ea0b698fb64d02b359927999 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Mon, 5 Dec 2016 11:18:09 -0500 Subject: tests/amdgpu: add uvd unit test support for vega10 Signed-off-by: Leo Liu Reviewed-by: Alex Deucher --- tests/amdgpu/cs_tests.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 82c55aa8..0885d974 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -175,11 +175,11 @@ static int submit(unsigned ndw, unsigned ip) static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx) { - ib_cpu[(*idx)++] = 0x3BC4; + ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4; ib_cpu[(*idx)++] = addr; - ib_cpu[(*idx)++] = 0x3BC5; + ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5; ib_cpu[(*idx)++] = addr >> 32; - ib_cpu[(*idx)++] = 0x3BC3; + ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3; ib_cpu[(*idx)++] = cmd << 1; } @@ -211,10 +211,12 @@ static void amdgpu_cs_uvd_create(void) CU_ASSERT_EQUAL(r, 0); memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); + if (family_id >= AMDGPU_FAMILY_VI) { ((uint8_t*)msg)[0x10] = 7; - /* chip polaris 10/11 */ - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { + /* chip beyond polaris 10/11 */ + if ((family_id == AMDGPU_FAMILY_AI) || + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { /* dpb size */ ((uint8_t*)msg)[0x28] = 0x00; ((uint8_t*)msg)[0x29] = 0x94; @@ -287,13 +289,15 @@ static void amdgpu_cs_uvd_decode(void) CU_ASSERT_EQUAL(r, 0); memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg)); + if (family_id >= AMDGPU_FAMILY_VI) { ptr[0x10] = 7; ptr[0x98] = 0x00; ptr[0x99] = 0x02; - /* chip polaris10/11 */ - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { - /*dpb size */ + /* chip beyond polaris10/11 */ + if ((family_id == AMDGPU_FAMILY_AI) || + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { + /* dpb size */ ptr[0x24] = 0x00; ptr[0x25] = 0x94; ptr[0x26] = 0x6B; @@ -335,9 +339,11 @@ static void amdgpu_cs_uvd_decode(void) bs_addr = fb_addr + 4*1024; dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); - if ((family_id >= AMDGPU_FAMILY_VI) && - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { - ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); + if (family_id >= AMDGPU_FAMILY_VI) { + if ((family_id == AMDGPU_FAMILY_AI) || + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { + ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); + } } dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); @@ -348,12 +354,15 @@ static void amdgpu_cs_uvd_decode(void) uvd_cmd(dt_addr, 0x2, &i); uvd_cmd(fb_addr, 0x3, &i); uvd_cmd(bs_addr, 0x100, &i); + if (family_id >= AMDGPU_FAMILY_VI) { uvd_cmd(it_addr, 0x204, &i); - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) + if ((family_id == AMDGPU_FAMILY_AI) || + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) uvd_cmd(ctx_addr, 0x206, &i); -} - ib_cpu[i++] = 0x3BC6; + } + + ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6; ib_cpu[i++] = 0x1; for (; i % 16; ++i) ib_cpu[i] = 0x80000000; -- cgit v1.2.3-54-g00ecf From f810e31bcf686a156b7b5be6298cd52247a98189 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Tue, 13 Dec 2016 15:24:05 -0500 Subject: tests/amdgpu: add vce unit test support for vega10 swizzle mode needs reference and input picture luma and chroma pitch aligned with 256 Signed-off-by: Leo Liu Reviewed-by: Alex Deucher --- tests/amdgpu/vce_tests.c | 54 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c index de63aa15..b03807b2 100644 --- a/tests/amdgpu/vce_tests.c +++ b/tests/amdgpu/vce_tests.c @@ -234,6 +234,7 @@ static void free_resource(struct amdgpu_vce_bo *vce_bo) static void amdgpu_cs_vce_create(void) { + unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; int len, r; enc.width = vce_create[6]; @@ -250,6 +251,8 @@ static void amdgpu_cs_vce_create(void) memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); len += sizeof(vce_taskinfo) / 4; memcpy((ib_cpu + len), vce_create, sizeof(vce_create)); + ib_cpu[len + 8] = ALIGN(enc.width, align); + ib_cpu[len + 9] = ALIGN(enc.width, align); len += sizeof(vce_create) / 4; memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); ib_cpu[len + 2] = enc.fb[0].addr >> 32; @@ -291,10 +294,12 @@ static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) { uint64_t luma_offset, chroma_offset; - int len = 0, r; + unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; + unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); + int len = 0, i, r; luma_offset = enc->vbuf.addr; - chroma_offset = luma_offset + enc->width * enc->height; + chroma_offset = luma_offset + luma_size; memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); len += sizeof(vce_session) / 4; @@ -309,6 +314,10 @@ static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) ib_cpu[len + 3] = enc->cpb.addr; len += sizeof(vce_context_buffer) / 4; memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); + for (i = 0; i < 8; ++i) + ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); + for (i = 0; i < 8; ++i) + ib_cpu[len + 10 + i] = luma_size * 1.5; len += sizeof(vce_aux_buffer) / 4; memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); ib_cpu[len + 2] = enc->fb[0].addr >> 32; @@ -319,8 +328,10 @@ static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) ib_cpu[len + 10] = luma_offset; ib_cpu[len + 11] = chroma_offset >> 32; ib_cpu[len + 12] = chroma_offset; - ib_cpu[len + 73] = 0x7800; - ib_cpu[len + 74] = 0x7800 + 0x5000; + ib_cpu[len + 14] = ALIGN(enc->width, align); + ib_cpu[len + 15] = ALIGN(enc->width, align); + ib_cpu[len + 73] = luma_size * 1.5; + ib_cpu[len + 74] = luma_size * 2.5; len += sizeof(vce_encode) / 4; enc->ib_len = len; if (!enc->two_instance) { @@ -332,11 +343,13 @@ static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) { uint64_t luma_offset, chroma_offset; - int len, r; + int len, i, r; + unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; + unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); len = (enc->two_instance) ? enc->ib_len : 0; luma_offset = enc->vbuf.addr; - chroma_offset = luma_offset + enc->width * enc->height; + chroma_offset = luma_offset + luma_size; if (!enc->two_instance) { memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); @@ -353,6 +366,10 @@ static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) ib_cpu[len + 3] = enc->cpb.addr; len += sizeof(vce_context_buffer) / 4; memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); + for (i = 0; i < 8; ++i) + ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); + for (i = 0; i < 8; ++i) + ib_cpu[len + 10 + i] = luma_size * 1.5; len += sizeof(vce_aux_buffer) / 4; memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); ib_cpu[len + 2] = enc->fb[1].addr >> 32; @@ -364,15 +381,17 @@ static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) ib_cpu[len + 10] = luma_offset; ib_cpu[len + 11] = chroma_offset >> 32; ib_cpu[len + 12] = chroma_offset; + ib_cpu[len + 14] = ALIGN(enc->width, align); + ib_cpu[len + 15] = ALIGN(enc->width, align); ib_cpu[len + 18] = 0; ib_cpu[len + 19] = 0; ib_cpu[len + 56] = 3; ib_cpu[len + 57] = 0; ib_cpu[len + 58] = 0; - ib_cpu[len + 59] = 0x7800; - ib_cpu[len + 60] = 0x7800 + 0x5000; + ib_cpu[len + 59] = luma_size * 1.5; + ib_cpu[len + 60] = luma_size * 2.5; ib_cpu[len + 73] = 0; - ib_cpu[len + 74] = 0x5000; + ib_cpu[len + 74] = luma_size; ib_cpu[len + 81] = 1; ib_cpu[len + 82] = 1; len += sizeof(vce_encode) / 4; @@ -408,9 +427,10 @@ static void check_result(struct amdgpu_vce_encode *enc) static void amdgpu_cs_vce_encode(void) { uint32_t vbuf_size, bs_size = 0x154000, cpb_size; - int r; + unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; + int i, r; - vbuf_size = enc.width * enc.height * 1.5; + vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; cpb_size = vbuf_size * 10; num_resources = 0; alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); @@ -429,7 +449,17 @@ static void amdgpu_cs_vce_encode(void) r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); CU_ASSERT_EQUAL(r, 0); - memcpy(enc.vbuf.ptr, frame, sizeof(frame)); + + memset(enc.vbuf.ptr, 0, vbuf_size); + for (i = 0; i < enc.height; ++i) { + memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); + enc.vbuf.ptr += ALIGN(enc.width, align); + } + for (i = 0; i < enc.height / 2; ++i) { + memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); + enc.vbuf.ptr += ALIGN(enc.width, align); + } + r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); CU_ASSERT_EQUAL(r, 0); -- cgit v1.2.3-54-g00ecf From a784c38af77714b9e878a7ff97ba18553697304c Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Tue, 20 Dec 2016 09:52:32 +0800 Subject: tests/amdgpu: add Polaris12 support for cs test Signed-off-by: Junwei Zhang Reviewed-by: Ken Wang Reviewed-by: Alex Deucher --- tests/amdgpu/cs_tests.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 0885d974..342815de 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -216,7 +216,8 @@ static void amdgpu_cs_uvd_create(void) ((uint8_t*)msg)[0x10] = 7; /* chip beyond polaris 10/11 */ if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || + chip_id == chip_rev+0x64)) { /* dpb size */ ((uint8_t*)msg)[0x28] = 0x00; ((uint8_t*)msg)[0x29] = 0x94; @@ -296,7 +297,8 @@ static void amdgpu_cs_uvd_decode(void) ptr[0x99] = 0x02; /* chip beyond polaris10/11 */ if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || + chip_id == chip_rev+0x64)) { /* dpb size */ ptr[0x24] = 0x00; ptr[0x25] = 0x94; @@ -341,7 +343,8 @@ static void amdgpu_cs_uvd_decode(void) if (family_id >= AMDGPU_FAMILY_VI) { if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || + chip_id == chip_rev+0x64)) { ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); } } @@ -358,7 +361,8 @@ static void amdgpu_cs_uvd_decode(void) if (family_id >= AMDGPU_FAMILY_VI) { uvd_cmd(it_addr, 0x204, &i); if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || + chip_id == chip_rev+0x64)) uvd_cmd(ctx_addr, 0x206, &i); } -- cgit v1.2.3-54-g00ecf From f684bb109fcdb85faa1b212bb6efcc352d8cbcdc Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 27 Mar 2017 15:44:14 +0200 Subject: amdgpu: stop reading CC_RB_BACKEND_DISABLE on Vega10 Follow up to 'drm: don't access deprecated register on Vega10'. The same information is available in enabled_rb_pipes_mask and reading that register can cause GRBM bus problems. Signed-off-by: Christian König Signed-off-by: Marek Olšák --- amdgpu/amdgpu_gpu_info.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index cd31e1b0..c5f5f6f4 100644 --- a/amdgpu/amdgpu_gpu_info.c +++ b/amdgpu/amdgpu_gpu_info.c @@ -169,20 +169,20 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) dev->info.vce_harvest_config = dev->dev_info.vce_harvest_config; dev->info.pci_rev_id = dev->dev_info.pci_rev; - for (i = 0; i < (int)dev->info.num_shader_engines; i++) { - unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) | - (AMDGPU_INFO_MMR_SH_INDEX_MASK << - AMDGPU_INFO_MMR_SH_INDEX_SHIFT); + if (dev->info.family_id < AMDGPU_FAMILY_AI) { + for (i = 0; i < (int)dev->info.num_shader_engines; i++) { + unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) | + (AMDGPU_INFO_MMR_SH_INDEX_MASK << + AMDGPU_INFO_MMR_SH_INDEX_SHIFT); - r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0, - &dev->info.backend_disable[i]); - if (r) - return r; - /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */ - dev->info.backend_disable[i] = - (dev->info.backend_disable[i] >> 16) & 0xff; + r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0, + &dev->info.backend_disable[i]); + if (r) + return r; + /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */ + dev->info.backend_disable[i] = + (dev->info.backend_disable[i] >> 16) & 0xff; - if (dev->info.family_id < AMDGPU_FAMILY_AI) { r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0, &dev->info.pa_sc_raster_cfg[i]); if (r) -- cgit v1.2.3-54-g00ecf From c7b5aaeb1f77a53a46c091b1ba999a76baa6c3fb Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Thu, 23 Mar 2017 10:43:40 -0400 Subject: amdgpu_drm: add AMDGPU_HW_IP_UVD_ENC Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Marek Olšák --- include/drm/amdgpu_drm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 1e25a87d..fa56499f 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -388,7 +388,8 @@ struct drm_amdgpu_gem_va { #define AMDGPU_HW_IP_DMA 2 #define AMDGPU_HW_IP_UVD 3 #define AMDGPU_HW_IP_VCE 4 -#define AMDGPU_HW_IP_NUM 5 +#define AMDGPU_HW_IP_UVD_ENC 5 +#define AMDGPU_HW_IP_NUM 6 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 -- cgit v1.2.3-54-g00ecf From 8d61a9a923c1ced974180609611ef615034fd484 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 29 Mar 2017 20:06:22 +0200 Subject: configure.ac: bump version for release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 2e50d3ef..6a60ffc6 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.75], + [2.4.76], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 18fbd7f0899d4e67a6902813a46be2983986c21c Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Sun, 26 Mar 2017 15:57:28 +0200 Subject: etnaviv: remove struct etna_specs There is no need to cache spec values directly as library users will cache them anyway. Signed-off-by: Christian Gmeiner --- etnaviv/etnaviv_gpu.c | 72 ++++++++++++++++++++------------------------------ etnaviv/etnaviv_priv.h | 22 ++------------- 2 files changed, 30 insertions(+), 64 deletions(-) diff --git a/etnaviv/etnaviv_gpu.c b/etnaviv/etnaviv_gpu.c index 35dec6cd..bc355e8f 100644 --- a/etnaviv/etnaviv_gpu.c +++ b/etnaviv/etnaviv_gpu.c @@ -61,32 +61,13 @@ struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core) gpu->dev = dev; gpu->core = core; - /* get specs from kernel space */ - gpu->specs.model = get_param(dev, core, ETNAVIV_PARAM_GPU_MODEL); - gpu->specs.revision = get_param(dev, core, ETNAVIV_PARAM_GPU_REVISION); - gpu->specs.features[0] = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_0); - gpu->specs.features[1] = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_1); - gpu->specs.features[2] = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_2); - gpu->specs.features[3] = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_3); - gpu->specs.features[4] = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_4); - gpu->specs.features[5] = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_5); - gpu->specs.features[6] = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_6); - gpu->specs.stream_count = get_param(dev, core, ETNA_GPU_STREAM_COUNT); - gpu->specs.register_max = get_param(dev, core, ETNA_GPU_REGISTER_MAX); - gpu->specs.thread_count = get_param(dev, core, ETNA_GPU_THREAD_COUNT); - gpu->specs.vertex_cache_size = get_param(dev, core, ETNA_GPU_VERTEX_CACHE_SIZE); - gpu->specs.shader_core_count = get_param(dev, core, ETNA_GPU_SHADER_CORE_COUNT); - gpu->specs.pixel_pipes = get_param(dev, core, ETNA_GPU_PIXEL_PIPES); - gpu->specs.vertex_output_buffer_size = get_param(dev, core, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE); - gpu->specs.buffer_size = get_param(dev, core, ETNA_GPU_BUFFER_SIZE); - gpu->specs.instruction_count = get_param(dev, core, ETNA_GPU_INSTRUCTION_COUNT); - gpu->specs.num_constants = get_param(dev, core, ETNA_GPU_NUM_CONSTANTS); - gpu->specs.num_varyings = get_param(dev, core, ETNA_GPU_NUM_VARYINGS); - - if (!gpu->specs.model) + gpu->model = get_param(dev, core, ETNAVIV_PARAM_GPU_MODEL); + gpu->revision = get_param(dev, core, ETNAVIV_PARAM_GPU_REVISION); + + if (!gpu->model) goto fail; - INFO_MSG(" GPU model: 0x%x (rev %x)", gpu->specs.model, gpu->specs.revision); + INFO_MSG(" GPU model: 0x%x (rev %x)", gpu->model, gpu->revision); return gpu; fail: @@ -104,66 +85,69 @@ void etna_gpu_del(struct etna_gpu *gpu) int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param, uint64_t *value) { + struct etna_device *dev = gpu->dev; + unsigned int core = gpu->core; + switch(param) { case ETNA_GPU_MODEL: - *value = gpu->specs.model; + *value = gpu->model; return 0; case ETNA_GPU_REVISION: - *value = gpu->specs.revision; + *value = gpu->revision; return 0; case ETNA_GPU_FEATURES_0: - *value = gpu->specs.features[0]; + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_0); return 0; case ETNA_GPU_FEATURES_1: - *value = gpu->specs.features[1]; + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_1); return 0; case ETNA_GPU_FEATURES_2: - *value = gpu->specs.features[2]; + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_2); return 0; case ETNA_GPU_FEATURES_3: - *value = gpu->specs.features[3]; + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_3); return 0; case ETNA_GPU_FEATURES_4: - *value = gpu->specs.features[4]; + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_4); return 0; case ETNA_GPU_FEATURES_5: - *value = gpu->specs.features[5]; + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_5); return 0; case ETNA_GPU_FEATURES_6: - *value = gpu->specs.features[6]; + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_6); return 0; case ETNA_GPU_STREAM_COUNT: - *value = gpu->specs.stream_count; + *value = get_param(dev, core, ETNA_GPU_STREAM_COUNT); return 0; case ETNA_GPU_REGISTER_MAX: - *value = gpu->specs.register_max; + *value = get_param(dev, core, ETNA_GPU_REGISTER_MAX); return 0; case ETNA_GPU_THREAD_COUNT: - *value = gpu->specs.thread_count; + *value = get_param(dev, core, ETNA_GPU_THREAD_COUNT); return 0; case ETNA_GPU_VERTEX_CACHE_SIZE: - *value = gpu->specs.vertex_cache_size; + *value = get_param(dev, core, ETNA_GPU_VERTEX_CACHE_SIZE); return 0; case ETNA_GPU_SHADER_CORE_COUNT: - *value = gpu->specs.shader_core_count; + *value = get_param(dev, core, ETNA_GPU_SHADER_CORE_COUNT); return 0; case ETNA_GPU_PIXEL_PIPES: - *value = gpu->specs.pixel_pipes; + *value = get_param(dev, core, ETNA_GPU_PIXEL_PIPES); return 0; case ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE: - *value = gpu->specs.vertex_output_buffer_size; + *value = get_param(dev, core, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE); return 0; case ETNA_GPU_BUFFER_SIZE: - *value = gpu->specs.buffer_size; + *value = get_param(dev, core, ETNA_GPU_BUFFER_SIZE); return 0; case ETNA_GPU_INSTRUCTION_COUNT: - *value = gpu->specs.instruction_count; + *value = get_param(dev, core, ETNA_GPU_INSTRUCTION_COUNT); return 0; case ETNA_GPU_NUM_CONSTANTS: - *value = gpu->specs.num_constants; + *value = get_param(dev, core, ETNA_GPU_NUM_CONSTANTS); return 0; case ETNA_GPU_NUM_VARYINGS: - *value = gpu->specs.num_varyings; + *value = get_param(dev, core, ETNA_GPU_NUM_VARYINGS); return 0; default: diff --git a/etnaviv/etnaviv_priv.h b/etnaviv/etnaviv_priv.h index feaa5ad9..1334ba3f 100644 --- a/etnaviv/etnaviv_priv.h +++ b/etnaviv/etnaviv_priv.h @@ -47,25 +47,6 @@ #include "etnaviv_drmif.h" #include "etnaviv_drm.h" -#define VIV_FEATURES_WORD_COUNT 7 - -struct etna_specs { - uint32_t model; - uint32_t revision; - uint32_t features[VIV_FEATURES_WORD_COUNT]; - uint32_t stream_count; - uint32_t register_max; - uint32_t thread_count; - uint32_t shader_core_count; - uint32_t vertex_cache_size; - uint32_t vertex_output_buffer_size; - uint32_t pixel_pipes; - uint32_t instruction_count; - uint32_t num_constants; - uint32_t num_varyings; - uint32_t buffer_size; -}; - struct etna_bo_bucket { uint32_t size; struct list_head list; @@ -134,8 +115,9 @@ struct etna_bo { struct etna_gpu { struct etna_device *dev; - struct etna_specs specs; uint32_t core; + uint32_t model; + uint32_t revision; }; struct etna_pipe { -- cgit v1.2.3-54-g00ecf From 4e369f25a942837454f1c127a7a440571af4f486 Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Wed, 8 Feb 2017 13:02:56 +0100 Subject: amdgpu: add amdgpu_bo_va_op_raw This variant allows the caller full control over flags and size, and allows passing a NULL bo (for PRT support). Cc: Bas Nieuwenhuizen Cc: Jerry Zhang Signed-off-by: Nicolai Hähnle Reviewed-by: Christian König --- amdgpu/amdgpu.h | 28 ++++++++++++++++++++++++++++ amdgpu/amdgpu_bo.c | 25 ++++++++++++++++++++----- 2 files changed, 48 insertions(+), 5 deletions(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 7b26a04c..6b2ded83 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1185,6 +1185,34 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, uint64_t flags, uint32_t ops); +/** + * VA mapping/unmapping for a buffer object or PRT region. + * + * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all + * parameters are treated "raw", i.e. size is not automatically aligned, and + * all flags must be specified explicitly. + * + * \param dev - \c [in] device handle + * \param bo - \c [in] BO handle (may be NULL) + * \param offset - \c [in] Start offset to map + * \param size - \c [in] Size to map + * \param addr - \c [in] Start virtual address. + * \param flags - \c [in] Supported flags for mapping/unmapping + * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ + +int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, + amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops); + /** * create semaphore * diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index d30fd1e7..f725bfd8 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -683,6 +683,23 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, uint32_t ops) { amdgpu_device_handle dev = bo->dev; + + size = ALIGN(size, getpagesize()); + + return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr, + AMDGPU_VM_PAGE_READABLE | + AMDGPU_VM_PAGE_WRITEABLE | + AMDGPU_VM_PAGE_EXECUTABLE, ops); +} + +int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, + amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops) +{ struct drm_amdgpu_gem_va va; int r; @@ -690,14 +707,12 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, return -EINVAL; memset(&va, 0, sizeof(va)); - va.handle = bo->handle; + va.handle = bo ? bo->handle : 0; va.operation = ops; - va.flags = AMDGPU_VM_PAGE_READABLE | - AMDGPU_VM_PAGE_WRITEABLE | - AMDGPU_VM_PAGE_EXECUTABLE; + va.flags = flags; va.va_address = addr; va.offset_in_bo = offset; - va.map_size = ALIGN(size, getpagesize()); + va.map_size = size; r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va)); -- cgit v1.2.3-54-g00ecf From f104148e40d6285a04698f0fa5f4ef76383bee6f Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Mon, 3 Apr 2017 10:22:59 +0200 Subject: headers: sync amdgpu_drm.h from airlied/drm-next Changes include: PRT and preemption flags, sensor info, and some more changes for Vega10. Generated using make headers_install from airlied/drm-next commit 320d8c3d38739fa8e31a076b86cbdafcf8897d5e. Signed-off-by: Nicolai Hähnle Reviewed-by: Marek Olšák Acked-by: Emil Velikov --- include/drm/amdgpu_drm.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index fa56499f..516a9f28 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -232,6 +232,7 @@ struct drm_amdgpu_gem_userptr { #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f +/* Set/Get helpers for tiling flags. */ #define AMDGPU_TILING_SET(field, value) \ (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) #define AMDGPU_TILING_GET(value, field) \ @@ -355,6 +356,8 @@ struct drm_amdgpu_gem_op { #define AMDGPU_VA_OP_MAP 1 #define AMDGPU_VA_OP_UNMAP 2 +#define AMDGPU_VA_OP_CLEAR 3 +#define AMDGPU_VA_OP_REPLACE 4 /* Delay the page table update till the next CS */ #define AMDGPU_VM_DELAY_UPDATE (1 << 0) @@ -366,6 +369,20 @@ struct drm_amdgpu_gem_op { #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) /* executable mapping, new for VI */ #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) +/* partially resident texture */ +#define AMDGPU_VM_PAGE_PRT (1 << 4) +/* MTYPE flags use bit 5 to 8 */ +#define AMDGPU_VM_MTYPE_MASK (0xf << 5) +/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ +#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) +/* Use NC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_NC (1 << 5) +/* Use WC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_WC (2 << 5) +/* Use CC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_CC (3 << 5) +/* Use UC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_UC (4 << 5) struct drm_amdgpu_gem_va { /** GEM object handle */ @@ -428,9 +445,12 @@ union drm_amdgpu_cs { /* This IB should be submitted to CE */ #define AMDGPU_IB_FLAG_CE (1<<0) -/* CE Preamble */ +/* Preamble flag, which means the IB could be dropped if no context switch */ #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) +/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ +#define AMDGPU_IB_FLAG_PREEMPT (1<<2) + struct drm_amdgpu_cs_chunk_ib { __u32 _pad; /** AMDGPU_IB_FLAG_* */ @@ -506,6 +526,10 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_FW_SMC 0x0a /* Subquery id: Query SDMA firmware version */ #define AMDGPU_INFO_FW_SDMA 0x0b + /* Subquery id: Query PSP SOS firmware version */ + #define AMDGPU_INFO_FW_SOS 0x0c + /* Subquery id: Query PSP ASD firmware version */ + #define AMDGPU_INFO_FW_ASD 0x0d /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f /* the used VRAM size */ @@ -536,6 +560,22 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_VBIOS_IMAGE 0x2 /* Query UVD handles */ #define AMDGPU_INFO_NUM_HANDLES 0x1C +/* Query sensor related information */ +#define AMDGPU_INFO_SENSOR 0x1D + /* Subquery id: Query GPU shader clock */ + #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 + /* Subquery id: Query GPU memory clock */ + #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 + /* Subquery id: Query GPU temperature */ + #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 + /* Subquery id: Query GPU load */ + #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 + /* Subquery id: Query average GPU power */ + #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 + /* Subquery id: Query northbridge voltage */ + #define AMDGPU_INFO_SENSOR_VDDNB 0x6 + /* Subquery id: Query graphics voltage */ + #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -599,6 +639,10 @@ struct drm_amdgpu_info { __u32 type; __u32 offset; } vbios_info; + + struct { + __u32 type; + } sensor_info; }; }; @@ -710,6 +754,16 @@ struct drm_amdgpu_info_device { __u32 vram_bit_width; /* vce harvesting instance */ __u32 vce_harvest_config; + /* gfx double offchip LDS buffers */ + __u32 gc_double_offchip_lds_buf; + /* NGG Primitive Buffer */ + __u64 prim_buf_gpu_addr; + /* NGG Position Buffer */ + __u64 pos_buf_gpu_addr; + /* NGG Control Sideband */ + __u64 cntl_sb_buf_gpu_addr; + /* NGG Parameter Cache */ + __u64 param_buf_gpu_addr; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3-54-g00ecf From 0a4626fead67f228bd7fad3c8b00812ab2613ec8 Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Mon, 3 Apr 2017 10:23:03 +0200 Subject: headers: the uint*_t vs. __u* discrepancy in amdgpu_drm is fixed This was already done in commit 3dc002df3e5 ("amdgpu: sync amdgpu_drm.h with kernel 4.11-rc2"), now update the README accordingly. Signed-off-by: Nicolai Hähnle Reviewed-by: Marek Olšák Acked-by: Emil Velikov --- include/drm/README | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/drm/README b/include/drm/README index f3cdf5da..870b0b5b 100644 --- a/include/drm/README +++ b/include/drm/README @@ -96,10 +96,6 @@ Status: ? Promote to fixed size ints, which match the current (32bit) ones. -amdgpu_drm.h - - Using the stdint.h uint*_t over the respective __u* ones -Status: Trivial. - drm_mode.h - Missing DPI encode/connector pair. Status: Trivial. -- cgit v1.2.3-54-g00ecf From eead59110771e617096d554ffd92360e023174e1 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 22 Mar 2017 11:14:00 +0800 Subject: amdgpu: add REPLACE and CLEAR checking for VA op (v2) v2: fix indent Signed-off-by: Junwei Zhang Reviewed-by: Nicolai Hähnle Reviewed-by: Christian König Reviewed-by: Marek Olšák Acked-by: Emil Velikov --- amdgpu/amdgpu_bo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index f725bfd8..9adfffa2 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -703,7 +703,8 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, struct drm_amdgpu_gem_va va; int r; - if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP) + if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP && + ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR) return -EINVAL; memset(&va, 0, sizeof(va)); -- cgit v1.2.3-54-g00ecf From f5995751b0722bdd3789b1afb48b86d8f075b1e7 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Mon, 3 Apr 2017 17:40:59 +0100 Subject: amdgpu: add amdgpu_bo_va_op_raw to the symbol check Otherwise the make check will rightfully fail. Fixes: 4e369f25a94 ("amdgpu: add amdgpu_bo_va_op_raw") Signed-off-by: Emil Velikov --- amdgpu/amdgpu-symbol-check | 1 + 1 file changed, 1 insertion(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 87f4fd2c..8e06474d 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -22,6 +22,7 @@ amdgpu_bo_list_update amdgpu_bo_query_info amdgpu_bo_set_metadata amdgpu_bo_va_op +amdgpu_bo_va_op_raw amdgpu_bo_wait_for_idle amdgpu_create_bo_from_user_mem amdgpu_cs_create_semaphore -- cgit v1.2.3-54-g00ecf From c9ef5c4a1c691ebcdfa4261b406b8b81f7b5a18f Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 31 Mar 2017 12:30:55 +0900 Subject: exynos: fix type-punned pointer build warning As like the commit ecc2a097294d ("xf86drm: Fix type-punned pointer build warning"), this fixes following build warning. exynos_drm.c: In function 'exynos_handle_event': exynos_drm.c:420:15: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] e = (struct drm_event *) &buffer[i]; ^ Signed-off-by: Seung-Woo Kim Reviewed-by: Tobias Jakobi Reviewed-by: Emil Velikov --- exynos/exynos_drm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/exynos/exynos_drm.c b/exynos/exynos_drm.c index b961e520..f6204f1c 100644 --- a/exynos/exynos_drm.c +++ b/exynos/exynos_drm.c @@ -417,7 +417,7 @@ exynos_handle_event(struct exynos_device *dev, struct exynos_event_context *ctx) i = 0; while (i < len) { - e = (struct drm_event *) &buffer[i]; + e = (struct drm_event *)(buffer + i); switch (e->type) { case DRM_EVENT_VBLANK: if (evctx->version < 1 || -- cgit v1.2.3-54-g00ecf From 762be6c2102de0ec99659838a1423c4a131432ff Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 31 Mar 2017 12:30:56 +0900 Subject: exynos/fimg2d: remove unused-function build warning The function g2d_reset() is not anymore used after the commit e3c97d1a2473 ("exynos/fimg2d: add g2d_validate_xyz() functions"), so it should be removed. Signed-off-by: Seung-Woo Kim Reviewed-by: Tobias Jakobi Reviewed-by: Emil Velikov --- exynos/exynos_fimg2d.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c index 7f1d105a..61340c36 100644 --- a/exynos/exynos_fimg2d.c +++ b/exynos/exynos_fimg2d.c @@ -292,20 +292,6 @@ static void g2d_set_direction(struct g2d_context *ctx, g2d_add_cmd(ctx, DST_PAT_DIRECT_REG, dir->val[1]); } -/* - * g2d_reset - reset fimg2d hardware. - * - * @ctx: a pointer to g2d_context structure. - * - */ -static void g2d_reset(struct g2d_context *ctx) -{ - ctx->cmd_nr = 0; - ctx->cmd_buf_nr = 0; - - g2d_add_cmd(ctx, SOFT_RESET_REG, 0x01); -} - /* * g2d_flush - submit all commands and values in user side command buffer * to command queue aware of fimg2d dma. -- cgit v1.2.3-54-g00ecf From a398adba7c845fe248ab1e5c338789ca2882644b Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 31 Mar 2017 12:30:57 +0900 Subject: tests/exynos: remove unused-function build warning The function g2d_blend_test() is blocked to call because of feature unsafety. This patch blocks with proper feature name and also blocks the function itself to remove build warning. Signed-off-by: Seung-Woo Kim Reviewed-by: Emil Velikov --- tests/exynos/exynos_fimg2d_test.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index 797fb6eb..3495c626 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -523,6 +523,7 @@ fail: return 0; } +#if EXYNOS_G2D_USERPTR_TEST static int g2d_blend_test(struct exynos_device *dev, struct exynos_bo *src, struct exynos_bo *dst, @@ -621,6 +622,7 @@ fail: return 0; } +#endif static int g2d_checkerboard_test(struct exynos_device *dev, struct exynos_bo *src, @@ -864,7 +866,7 @@ int main(int argc, char **argv) * * Disable the test for now, until the kernel code has been sanitized. */ -#if 0 +#if EXYNOS_G2D_USERPTR_TEST ret = g2d_blend_test(dev, src, bo, G2D_IMGBUF_USERPTR); if (ret < 0) fprintf(stderr, "failed to test blend operation.\n"); -- cgit v1.2.3-54-g00ecf From 2dc30dd5279fea1838f181724fb699a3689f582b Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Mon, 20 Mar 2017 09:52:49 +0900 Subject: tests/exynos: fix invalid code of error path in g2d test This patch fixes invalid code of error path including NULL deference and leak in g2d test. Signed-off-by: Seung-Woo Kim Reviewed-by: Emil Velikov --- tests/exynos/exynos_fimg2d_test.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index 3495c626..ab1028e8 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -59,7 +59,6 @@ static void connector_find_mode(int fd, struct connector *c, if (!connector) { fprintf(stderr, "could not get connector %i: %s\n", resources->connectors[i], strerror(errno)); - drmModeFreeConnector(connector); continue; } @@ -98,7 +97,6 @@ static void connector_find_mode(int fd, struct connector *c, if (!c->encoder) { fprintf(stderr, "could not get encoder %i: %s\n", resources->encoders[i], strerror(errno)); - drmModeFreeEncoder(c->encoder); continue; } @@ -264,7 +262,8 @@ static int g2d_copy_test(struct exynos_device *dev, struct exynos_bo *src, userptr = (unsigned long)malloc(size); if (!userptr) { fprintf(stderr, "failed to allocate userptr.\n"); - return -EFAULT; + ret = -EFAULT; + goto fail; } src_img.user_ptr[0].userptr = userptr; @@ -469,7 +468,8 @@ static int g2d_copy_with_scale_test(struct exynos_device *dev, userptr = (unsigned long)malloc(size); if (!userptr) { fprintf(stderr, "failed to allocate userptr.\n"); - return -EFAULT; + ret = -EFAULT; + goto fail; } src_img.user_ptr[0].userptr = userptr; @@ -520,7 +520,7 @@ err_free_userptr: fail: g2d_fini(ctx); - return 0; + return ret;; } #if EXYNOS_G2D_USERPTR_TEST @@ -558,7 +558,8 @@ static int g2d_blend_test(struct exynos_device *dev, userptr = (unsigned long)malloc(size); if (!userptr) { fprintf(stderr, "failed to allocate userptr.\n"); - return -EFAULT; + ret = -EFAULT; + goto fail; } src_img.user_ptr[0].userptr = userptr; @@ -620,7 +621,7 @@ err_free_userptr: fail: g2d_fini(ctx); - return 0; + return ret; } #endif @@ -647,8 +648,8 @@ static int g2d_checkerboard_test(struct exynos_device *dev, dst_y = 0; checkerboard = create_checkerboard_pattern(screen_width / 32, screen_height / 32, 32); - if (checkerboard == NULL) { - ret = -1; + if (!checkerboard) { + ret = -EFAULT; goto fail; } @@ -757,8 +758,8 @@ int main(int argc, char **argv) dev = exynos_device_create(fd); if (!dev) { - drmClose(dev->fd); - return -EFAULT; + ret = -EFAULT; + goto err_drm_close; } resources = drmModeGetResources(dev->fd); @@ -766,7 +767,7 @@ int main(int argc, char **argv) fprintf(stderr, "drmModeGetResources failed: %s\n", strerror(errno)); ret = -EFAULT; - goto err_drm_close; + goto err_dev_destory; } connector_find_mode(dev->fd, &con, resources); @@ -775,7 +776,7 @@ int main(int argc, char **argv) if (!con.mode) { fprintf(stderr, "failed to find usable connector\n"); ret = -EFAULT; - goto err_drm_close; + goto err_dev_destory; } screen_width = con.mode->hdisplay; @@ -784,7 +785,7 @@ int main(int argc, char **argv) if (screen_width == 0 || screen_height == 0) { fprintf(stderr, "failed to find sane resolution on connector\n"); ret = -EFAULT; - goto err_drm_close; + goto err_dev_destory; } printf("screen width = %d, screen height = %d\n", screen_width, @@ -793,7 +794,7 @@ int main(int argc, char **argv) bo = exynos_create_buffer(dev, screen_width * screen_height * 4, 0); if (!bo) { ret = -EFAULT; - goto err_drm_close; + goto err_dev_destory; } handles[0] = bo->handle; @@ -884,9 +885,11 @@ err_rm_fb: err_destroy_buffer: exynos_destroy_buffer(bo); -err_drm_close: - drmClose(dev->fd); +err_dev_destory: exynos_device_destroy(dev); - return 0; +err_drm_close: + drmClose(fd); + + return ret; } -- cgit v1.2.3-54-g00ecf From 7b806e87890182ac1b6181a848e03cd5c7db97ec Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Mon, 27 Mar 2017 11:09:29 +0900 Subject: xf86drm: remove memory leaks in drmGetBusid/drmGetReservedContextList In error path of drmGetBusid() and drmGetReservedContextList(), there are memory leaks for error path. So this removes them. Signed-off-by: Seung-Woo Kim Reviewed-by: Nicolai Hähnle Reviewed-by: Emil Velikov --- xf86drm.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/xf86drm.c b/xf86drm.c index 88f86ed5..685cf69d 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -994,8 +994,10 @@ char *drmGetBusid(int fd) if (drmIoctl(fd, DRM_IOCTL_GET_UNIQUE, &u)) return NULL; u.unique = drmMalloc(u.unique_len + 1); - if (drmIoctl(fd, DRM_IOCTL_GET_UNIQUE, &u)) + if (drmIoctl(fd, DRM_IOCTL_GET_UNIQUE, &u)) { + drmFree(u.unique); return NULL; + } u.unique[u.unique_len] = '\0'; return u.unique; @@ -1523,14 +1525,12 @@ drm_context_t *drmGetReservedContextList(int fd, int *count) if (!(list = drmMalloc(res.count * sizeof(*list)))) return NULL; - if (!(retval = drmMalloc(res.count * sizeof(*retval)))) { - drmFree(list); - return NULL; - } + if (!(retval = drmMalloc(res.count * sizeof(*retval)))) + goto err_free_list; res.contexts = list; if (drmIoctl(fd, DRM_IOCTL_RES_CTX, &res)) - return NULL; + goto err_free_context; for (i = 0; i < res.count; i++) retval[i] = list[i].handle; @@ -1538,6 +1538,12 @@ drm_context_t *drmGetReservedContextList(int fd, int *count) *count = res.count; return retval; + +err_free_list: + drmFree(list); +err_free_context: + drmFree(retval); + return NULL; } void drmFreeReservedContextList(drm_context_t *pt) -- cgit v1.2.3-54-g00ecf From c4d673acdcf1add753aa53d359f29bb44bc057db Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 22 Mar 2017 14:05:24 -0500 Subject: Android: fix building of modetest and proptest These tests depend on tests/util/ headers, but expect the include path to be tests/. Signed-off-by: Rob Herring Reviewed-by: Emil Velikov --- Android.mk | 2 ++ tests/util/Android.mk | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Android.mk b/Android.mk index 5209059e..292be236 100644 --- a/Android.mk +++ b/Android.mk @@ -24,6 +24,8 @@ LIBDRM_COMMON_MK := $(call my-dir)/Android.common.mk LOCAL_PATH := $(call my-dir) +LIBDRM_TOP := $(LOCAL_PATH) + include $(CLEAR_VARS) # Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES diff --git a/tests/util/Android.mk b/tests/util/Android.mk index 7656c4c2..12eccb42 100644 --- a/tests/util/Android.mk +++ b/tests/util/Android.mk @@ -32,5 +32,7 @@ LOCAL_SHARED_LIBRARIES := libdrm LOCAL_SRC_FILES := $(UTIL_FILES) +LOCAL_EXPORT_C_INCLUDE_DIRS := $(LIBDRM_TOP)/tests + include $(LIBDRM_COMMON_MK) include $(BUILD_STATIC_LIBRARY) -- cgit v1.2.3-54-g00ecf From 51a514c43f607c7f3c1231d1fcac15d450f98e5c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 22 Mar 2017 14:05:25 -0500 Subject: Android: disable pointer-arith and enum-conversion Disable some more warnings from clang. These don't appear to be warnings worth fixing. Signed-off-by: Rob Herring Reviewed-by: Emil Velikov --- Android.common.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Android.common.mk b/Android.common.mk index f57b8d37..35c0f02c 100644 --- a/Android.common.mk +++ b/Android.common.mk @@ -5,7 +5,9 @@ LOCAL_CFLAGS += \ LOCAL_CFLAGS += \ -Wno-unused-parameter \ - -Wno-missing-field-initializers + -Wno-missing-field-initializers \ + -Wno-pointer-arith \ + -Wno-enum-conversion # Quiet down the build system and remove any .h files from the sources LOCAL_SRC_FILES := $(patsubst %.h, , $(LOCAL_SRC_FILES)) -- cgit v1.2.3-54-g00ecf From e5053343de6f910882a43214ce5c7b69a9b07927 Mon Sep 17 00:00:00 2001 From: Erik Faye-Lund Date: Wed, 29 Mar 2017 22:24:24 +0000 Subject: tegra: update symbol-check I get a few more symbols in my build tegra-libraries, so let's include these in the whitelist as well. While we're at it, update the comment at the top. Signed-off-by: Erik Faye-Lund Reviewed-by: Emil Velikov --- tegra/tegra-symbol-check | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tegra/tegra-symbol-check b/tegra/tegra-symbol-check index 40208311..420469f4 100755 --- a/tegra/tegra-symbol-check +++ b/tegra/tegra-symbol-check @@ -1,11 +1,14 @@ #!/bin/bash -# The following symbols (past the first five) are taken from the public headers. -# A list of the latter should be available Makefile.sources/LIBDRM_FREEDRENO_H_FILES +# The following symbols (past the first nine) are taken from tegra.h. FUNCS=$(nm -D --format=bsd --defined-only ${1-.libs/libdrm_tegra.so} | awk '{print $3}'| while read func; do ( grep -q "^$func$" || echo $func ) < Reviewed-by: Emil Velikov --- tests/etnaviv/Makefile.am | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/etnaviv/Makefile.am b/tests/etnaviv/Makefile.am index 06318643..226baee2 100644 --- a/tests/etnaviv/Makefile.am +++ b/tests/etnaviv/Makefile.am @@ -28,6 +28,7 @@ etnaviv_2d_test_SOURCES = \ write_bmp.h etnaviv_cmd_stream_test_LDADD = \ + $(top_builddir)/libdrm.la \ $(top_builddir)/etnaviv/libdrm_etnaviv.la etnaviv_cmd_stream_test_SOURCES = \ -- cgit v1.2.3-54-g00ecf From 63120172668610cebfd01e89f67e73037037dfd9 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Thu, 30 Mar 2017 18:01:12 +0100 Subject: configure.ac: bring back pthread-stubs check Accidentally removed with earlier commit. Although rather than simply adding the check for all platforms, use the same heuristics as we do in mesa. Namely: pthread-stubs is a thing only for BSD platforms. Everyone else should have lightweight pthread API in their C runtime library. Fixes: 4ecd1ef010b ("xf86drm: fix null termination of string buffer") Signed-off-by: Emil Velikov Reviewed-by: Eric Engestrom --- configure.ac | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index 6a60ffc6..f1a13090 100644 --- a/configure.ac +++ b/configure.ac @@ -61,10 +61,22 @@ AC_CHECK_HEADERS([sys/sysctl.h sys/select.h]) LT_PREREQ([2.2]) LT_INIT([disable-static]) - - -AC_SUBST(PTHREADSTUBS_CFLAGS) -AC_SUBST(PTHREADSTUBS_LIBS) +dnl pthread-stubs is mandatory on BSD platforms, due to the nature of the +dnl project. Even then there's a notable issue as described in the project README +case "$host_os" in +linux* | cygwin* | darwin* | solaris* | gnu*) + pthread_stubs_possible="no" + ;; +* ) + pthread_stubs_possible="yes" + ;; +esac + +if test "x$pthread_stubs_possible" = xyes; then + PKG_CHECK_MODULES(PTHREADSTUBS, pthread-stubs >= 0.4) + AC_SUBST(PTHREADSTUBS_CFLAGS) + AC_SUBST(PTHREADSTUBS_LIBS) +fi pkgconfigdir=${libdir}/pkgconfig AC_SUBST(pkgconfigdir) -- cgit v1.2.3-54-g00ecf From e61e999838faa65f1c5cbddfbda06125be19e353 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 4 Apr 2017 11:36:00 +0200 Subject: configure.ac: bump the version to 2.4.77 --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index f1a13090..036f65a2 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.76], + [2.4.77], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 64423a70361eec1b855022550b1c13cc4807ce0e Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 4 Apr 2017 16:58:46 +0100 Subject: man/drm(7): fix typo Reported-by: Oliver Kisielius Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100559 Signed-off-by: Eric Engestrom --- man/drm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/man/drm.xml b/man/drm.xml index 5a49fe13..07f17719 100644 --- a/man/drm.xml +++ b/man/drm.xml @@ -50,7 +50,7 @@ In earlier days, the kernel framework was solely used to provide raw hardware access to priviledged user-space processes which implement - all the hardware abstraction layers. But more and more tasks where + all the hardware abstraction layers. But more and more tasks were moved into the kernel. All these interfaces are based on ioctl2 commands on the DRM character device. The libdrm -- cgit v1.2.3-54-g00ecf From 33312e42a777d23f00febc0ece83c91429ef4bf9 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 4 Apr 2017 17:09:01 +0100 Subject: man: fix bug report instruction Component "libdrm" doesn't exist (anymore?) Signed-off-by: Eric Engestrom --- man/drm-kms.xml | 4 ++-- man/drm-memory.xml | 4 ++-- man/drm.xml | 4 ++-- man/drmAvailable.xml | 4 ++-- man/drmHandleEvent.xml | 4 ++-- man/drmModeGetResources.xml | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/man/drm-kms.xml b/man/drm-kms.xml index ae38dc8d..4423ade1 100644 --- a/man/drm-kms.xml +++ b/man/drm-kms.xml @@ -309,8 +309,8 @@ static int modeset_find_crtc(int fd, drmModeRes *res, drmModeConnector *conn) Reporting Bugs Bugs in this manual should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" or - "libdrm" as the component. + http://bugs.freedesktop.org under the "Mesa" product, with "Other" + as the component. diff --git a/man/drm-memory.xml b/man/drm-memory.xml index 6b4f0759..daca9cf2 100644 --- a/man/drm-memory.xml +++ b/man/drm-memory.xml @@ -410,8 +410,8 @@ memset(map, 0, creq.size); Reporting Bugs Bugs in this manual should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" or - "libdrm" as the component. + http://bugs.freedesktop.org under the "Mesa" product, with "Other" + as the component. diff --git a/man/drm.xml b/man/drm.xml index 07f17719..bd354166 100644 --- a/man/drm.xml +++ b/man/drm.xml @@ -119,8 +119,8 @@ Reporting Bugs Bugs in this manual should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" or - "libdrm" as the component. + http://bugs.freedesktop.org under the "Mesa" product, with "Other" + as the component. diff --git a/man/drmAvailable.xml b/man/drmAvailable.xml index 55bef94a..37a5b494 100644 --- a/man/drmAvailable.xml +++ b/man/drmAvailable.xml @@ -61,8 +61,8 @@ Reporting Bugs Bugs in this function should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" or - "libdrm" as the component. + http://bugs.freedesktop.org under the "Mesa" product, with "Other" + as the component. diff --git a/man/drmHandleEvent.xml b/man/drmHandleEvent.xml index b1006e51..1de566b1 100644 --- a/man/drmHandleEvent.xml +++ b/man/drmHandleEvent.xml @@ -86,8 +86,8 @@ typedef struct _drmEventContext { Reporting Bugs Bugs in this function should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" or - "libdrm" as the component. + http://bugs.freedesktop.org under the "Mesa" product, with "Other" + as the component. diff --git a/man/drmModeGetResources.xml b/man/drmModeGetResources.xml index 2f5e8c2c..aba34220 100644 --- a/man/drmModeGetResources.xml +++ b/man/drmModeGetResources.xml @@ -116,8 +116,8 @@ typedef struct _drmModeRes { Reporting Bugs Bugs in this function should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" or - "libdrm" as the component. + http://bugs.freedesktop.org under the "Mesa" product, with "Other" + as the component. -- cgit v1.2.3-54-g00ecf From 294be2616e1eda4e558253ae498f1503be347028 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 4 Apr 2017 17:37:02 +0100 Subject: man: fix bug report instructions (for real this time) /me derped, component libdrm doesn't exist under Mesa because it's in DRI. While at it, give the full URL and make it https. Signed-off-by: Eric Engestrom --- man/drm-kms.xml | 4 ++-- man/drm-memory.xml | 4 ++-- man/drm.xml | 4 ++-- man/drmAvailable.xml | 4 ++-- man/drmHandleEvent.xml | 4 ++-- man/drmModeGetResources.xml | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/man/drm-kms.xml b/man/drm-kms.xml index 4423ade1..dc471bfb 100644 --- a/man/drm-kms.xml +++ b/man/drm-kms.xml @@ -309,8 +309,8 @@ static int modeset_find_crtc(int fd, drmModeRes *res, drmModeConnector *conn) Reporting Bugs Bugs in this manual should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" - as the component. + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + under the "DRI" product, component "libdrm" diff --git a/man/drm-memory.xml b/man/drm-memory.xml index daca9cf2..aab7ee77 100644 --- a/man/drm-memory.xml +++ b/man/drm-memory.xml @@ -410,8 +410,8 @@ memset(map, 0, creq.size); Reporting Bugs Bugs in this manual should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" - as the component. + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + under the "DRI" product, component "libdrm" diff --git a/man/drm.xml b/man/drm.xml index bd354166..22bf0aa6 100644 --- a/man/drm.xml +++ b/man/drm.xml @@ -119,8 +119,8 @@ Reporting Bugs Bugs in this manual should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" - as the component. + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + under the "DRI" product, component "libdrm" diff --git a/man/drmAvailable.xml b/man/drmAvailable.xml index 37a5b494..4442a0ab 100644 --- a/man/drmAvailable.xml +++ b/man/drmAvailable.xml @@ -61,8 +61,8 @@ Reporting Bugs Bugs in this function should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" - as the component. + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + under the "DRI" product, component "libdrm" diff --git a/man/drmHandleEvent.xml b/man/drmHandleEvent.xml index 1de566b1..7064c1d1 100644 --- a/man/drmHandleEvent.xml +++ b/man/drmHandleEvent.xml @@ -86,8 +86,8 @@ typedef struct _drmEventContext { Reporting Bugs Bugs in this function should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" - as the component. + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + under the "DRI" product, component "libdrm" diff --git a/man/drmModeGetResources.xml b/man/drmModeGetResources.xml index aba34220..a18f9c52 100644 --- a/man/drmModeGetResources.xml +++ b/man/drmModeGetResources.xml @@ -116,8 +116,8 @@ typedef struct _drmModeRes { Reporting Bugs Bugs in this function should be reported to - http://bugs.freedesktop.org under the "Mesa" product, with "Other" - as the component. + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + under the "DRI" product, component "libdrm" -- cgit v1.2.3-54-g00ecf From 10ca5e13a8357dfa5562102ae94b9fa7f535f4df Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 4 Apr 2017 18:05:53 +0100 Subject: man: fix bug report instructions (third time's the charm) Compile- and run-tested this time. Signed-off-by: Eric Engestrom --- man/drm-kms.xml | 2 +- man/drm-memory.xml | 2 +- man/drm.xml | 2 +- man/drmAvailable.xml | 2 +- man/drmHandleEvent.xml | 2 +- man/drmModeGetResources.xml | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/man/drm-kms.xml b/man/drm-kms.xml index dc471bfb..eb04c263 100644 --- a/man/drm-kms.xml +++ b/man/drm-kms.xml @@ -309,7 +309,7 @@ static int modeset_find_crtc(int fd, drmModeRes *res, drmModeConnector *conn) Reporting Bugs Bugs in this manual should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm under the "DRI" product, component "libdrm" diff --git a/man/drm-memory.xml b/man/drm-memory.xml index aab7ee77..3aa7cf25 100644 --- a/man/drm-memory.xml +++ b/man/drm-memory.xml @@ -410,7 +410,7 @@ memset(map, 0, creq.size); Reporting Bugs Bugs in this manual should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm under the "DRI" product, component "libdrm" diff --git a/man/drm.xml b/man/drm.xml index 22bf0aa6..1f559669 100644 --- a/man/drm.xml +++ b/man/drm.xml @@ -119,7 +119,7 @@ Reporting Bugs Bugs in this manual should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm under the "DRI" product, component "libdrm" diff --git a/man/drmAvailable.xml b/man/drmAvailable.xml index 4442a0ab..1e5d7873 100644 --- a/man/drmAvailable.xml +++ b/man/drmAvailable.xml @@ -61,7 +61,7 @@ Reporting Bugs Bugs in this function should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm under the "DRI" product, component "libdrm" diff --git a/man/drmHandleEvent.xml b/man/drmHandleEvent.xml index 7064c1d1..83304428 100644 --- a/man/drmHandleEvent.xml +++ b/man/drmHandleEvent.xml @@ -86,7 +86,7 @@ typedef struct _drmEventContext { Reporting Bugs Bugs in this function should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm under the "DRI" product, component "libdrm" diff --git a/man/drmModeGetResources.xml b/man/drmModeGetResources.xml index a18f9c52..0ab6a68b 100644 --- a/man/drmModeGetResources.xml +++ b/man/drmModeGetResources.xml @@ -116,7 +116,7 @@ typedef struct _drmModeRes { Reporting Bugs Bugs in this function should be reported to - https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm + https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=libdrm under the "DRI" product, component "libdrm" -- cgit v1.2.3-54-g00ecf From 0010d312dbf0dae05652b75cdef7cd361f686623 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Wed, 5 Apr 2017 17:21:29 +0100 Subject: configure.ac: pthread-stubs is not a thing on GNU/kFreeBSD As mentioned on the xcb mailing list, the platform uses the GLIBC forwarding mechanism. https://lists.freedesktop.org/archives/xcb/2016-November/010896.html Reported-by: Andreas Boll Signed-off-by: Emil Velikov Reviewed-by: Eric Engestrom Reviewed-by: Andreas Boll --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 036f65a2..7b9369be 100644 --- a/configure.ac +++ b/configure.ac @@ -64,7 +64,7 @@ LT_INIT([disable-static]) dnl pthread-stubs is mandatory on BSD platforms, due to the nature of the dnl project. Even then there's a notable issue as described in the project README case "$host_os" in -linux* | cygwin* | darwin* | solaris* | gnu*) +linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu*) pthread_stubs_possible="no" ;; * ) -- cgit v1.2.3-54-g00ecf From e379c6a137bba5c40d9a126b71a667b4d7f5697a Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Tue, 4 Apr 2017 21:38:56 +0100 Subject: Headers: Sync drm{,_mode}.h with the kernel Generated using make headers_install, based on drm-misc-next commit 5db06a8a98f515f67446a69c57577c4c363ec65d. This clarifies the comments around modifiers such that they are per-framebuffer rather than per-plane, adds the beginnings of aspect ratio mode flags, link status properties, and updates the 'reserved' field from vblank events to include the CRTC ID. v2: Split into separate patch, pull in full kernel changes. v3: Undo revert of connector-type enums, since it is not actually harmful. Signed-off-by: Daniel Stone Reviewed-by: Emil Velikov --- include/drm/drm.h | 3 ++- include/drm/drm_mode.h | 45 +++++++++++++++++++++++++++++++-------------- 2 files changed, 33 insertions(+), 15 deletions(-) diff --git a/include/drm/drm.h b/include/drm/drm.h index f6fd5c2c..1e7a4bc7 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -641,6 +641,7 @@ struct drm_gem_open { #define DRM_CAP_CURSOR_HEIGHT 0x9 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 #define DRM_CAP_PAGE_FLIP_TARGET 0x11 +#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 /** DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { @@ -845,7 +846,7 @@ struct drm_event_vblank { __u32 tv_sec; __u32 tv_usec; __u32 sequence; - __u32 reserved; + __u32 crtc_id; /* 0 on older kernels that do not support this */ }; /* typedef area */ diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index df0e3504..70571af6 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -47,7 +47,15 @@ extern "C" { #define DRM_MODE_TYPE_DRIVER (1<<6) /* Video mode flags */ -/* bit compatible with the xorg definitions. */ +/* bit compatible with the xrandr RR_ definitions (bits 0-13) + * + * ABI warning: Existing userspace really expects + * the mode flags to match the xrandr definitions. Any + * changes that don't match the xrandr definitions will + * likely need a new client cap or some other mechanism + * to avoid breaking existing userspace. This includes + * allocating new flags in the previously unused bits! + */ #define DRM_MODE_FLAG_PHSYNC (1<<0) #define DRM_MODE_FLAG_NHSYNC (1<<1) #define DRM_MODE_FLAG_PVSYNC (1<<2) @@ -107,6 +115,10 @@ extern "C" { #define DRM_MODE_DIRTY_ON 1 #define DRM_MODE_DIRTY_ANNOTATE 2 +/* Link Status options */ +#define DRM_MODE_LINK_STATUS_GOOD 0 +#define DRM_MODE_LINK_STATUS_BAD 1 + struct drm_mode_modeinfo { __u32 clock; __u16 hdisplay; @@ -220,14 +232,16 @@ struct drm_mode_get_encoder { /* This is for connectors with multiple signal types. */ /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ -#define DRM_MODE_SUBCONNECTOR_Automatic 0 -#define DRM_MODE_SUBCONNECTOR_Unknown 0 -#define DRM_MODE_SUBCONNECTOR_DVID 3 -#define DRM_MODE_SUBCONNECTOR_DVIA 4 -#define DRM_MODE_SUBCONNECTOR_Composite 5 -#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 -#define DRM_MODE_SUBCONNECTOR_Component 8 -#define DRM_MODE_SUBCONNECTOR_SCART 9 +enum drm_mode_subconnector { + DRM_MODE_SUBCONNECTOR_Automatic = 0, + DRM_MODE_SUBCONNECTOR_Unknown = 0, + DRM_MODE_SUBCONNECTOR_DVID = 3, + DRM_MODE_SUBCONNECTOR_DVIA = 4, + DRM_MODE_SUBCONNECTOR_Composite = 5, + DRM_MODE_SUBCONNECTOR_SVIDEO = 6, + DRM_MODE_SUBCONNECTOR_Component = 8, + DRM_MODE_SUBCONNECTOR_SCART = 9, +}; #define DRM_MODE_CONNECTOR_Unknown 0 #define DRM_MODE_CONNECTOR_VGA 1 @@ -392,17 +406,20 @@ struct drm_mode_fb_cmd2 { * offsets[1]. Note that offsets[0] will generally * be 0 (but this is not required). * - * To accommodate tiled, compressed, etc formats, a per-plane + * To accommodate tiled, compressed, etc formats, a * modifier can be specified. The default value of zero * indicates "native" format as specified by the fourcc. - * Vendor specific modifier token. This allows, for example, - * different tiling/swizzling pattern on different planes. - * See discussion above of DRM_FORMAT_MOD_xxx. + * Vendor specific modifier token. Note that even though + * it looks like we have a modifier per-plane, we in fact + * do not. The modifier for each plane must be identical. + * Thus all combinations of different data layouts for + * multi plane formats must be enumerated as separate + * modifiers. */ __u32 handles[4]; __u32 pitches[4]; /* pitch for each plane */ __u32 offsets[4]; /* offset of each plane */ - __u64 modifier[4]; /* ie, tiling, compressed (per plane) */ + __u64 modifier[4]; /* ie, tiling, compress */ }; #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 -- cgit v1.2.3-54-g00ecf From 890d43a6a8d091211b82dd432af5e0a38472ffa6 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Mon, 17 Aug 2015 16:21:24 +0300 Subject: Add CRTC ID to vblank event When using the atomic API, one request can span multiple CRTCs, however one event is generated per CRTC. As we cannot disambiguate the CRTC with user data (since we only have one piece of user data to pass in), newer kernels can include the CRTC ID in the page flip event. Add a new vfunc to dispatch vblank events carrying a CRTC ID to clients who negotiate a higher interface version. [daniels: Rebased, include new cap, call page_flip_handler if it is set but page_flip_handler2 isn't even on newer contexts, write a commit message.] v2: Split into separate commit. Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Stone Reviewed-by: Maarten Lankhorst --- xf86drm.h | 9 ++++++++- xf86drmMode.c | 24 ++++++++++++++++-------- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/xf86drm.h b/xf86drm.h index 0d927018..d75ca8ce 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -728,7 +728,7 @@ extern void drmMsg(const char *format, ...) DRM_PRINTFLIKE(1, 2); extern int drmSetMaster(int fd); extern int drmDropMaster(int fd); -#define DRM_EVENT_CONTEXT_VERSION 2 +#define DRM_EVENT_CONTEXT_VERSION 3 typedef struct _drmEventContext { @@ -748,6 +748,13 @@ typedef struct _drmEventContext { unsigned int tv_usec, void *user_data); + void (*page_flip_handler2)(int fd, + unsigned int sequence, + unsigned int tv_sec, + unsigned int tv_usec, + unsigned int crtc_id, + void *user_data); + } drmEventContext, *drmEventContextPtr; extern int drmHandleEvent(int fd, drmEventContextPtr evctx); diff --git a/xf86drmMode.c b/xf86drmMode.c index 0266bc10..d3bc20ea 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -889,6 +889,7 @@ int drmHandleEvent(int fd, drmEventContextPtr evctx) int len, i; struct drm_event *e; struct drm_event_vblank *vblank; + void *user_data; /* The DRM read semantics guarantees that we always get only * complete events. */ @@ -915,15 +916,22 @@ int drmHandleEvent(int fd, drmEventContextPtr evctx) U642VOID (vblank->user_data)); break; case DRM_EVENT_FLIP_COMPLETE: - if (evctx->version < 2 || - evctx->page_flip_handler == NULL) - break; vblank = (struct drm_event_vblank *) e; - evctx->page_flip_handler(fd, - vblank->sequence, - vblank->tv_sec, - vblank->tv_usec, - U642VOID (vblank->user_data)); + user_data = U642VOID (vblank->user_data); + + if (evctx->version >= 3 && evctx->page_flip_handler2) + evctx->page_flip_handler2(fd, + vblank->sequence, + vblank->tv_sec, + vblank->tv_usec, + vblank->crtc_id, + user_data); + else if (evctx->version >= 2 && evctx->page_flip_handler) + evctx->page_flip_handler(fd, + vblank->sequence, + vblank->tv_sec, + vblank->tv_usec, + user_data); break; default: break; -- cgit v1.2.3-54-g00ecf From 1142f9b30fd5c3b2ca93069bee757418ba497895 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 7 Apr 2017 09:10:15 +0100 Subject: configure.ac: bump version for release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 7b9369be..37022fee 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.77], + [2.4.78], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 047aba169731b32ca80b612e6e0d71e4b4e11937 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 4 Apr 2017 16:34:56 +0200 Subject: amdgpu: allow to query GPU sensor related information This exposes amdgpu_query_sensor_info(). v2: - add amdgpu_query_sensor_info() to the symbols list Signed-off-by: Samuel Pitoiset Reviewed-by: Marek Olšák --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 18 ++++++++++++++++++ amdgpu/amdgpu_gpu_info.c | 15 +++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 8e06474d..4d1ae65c 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -46,6 +46,7 @@ amdgpu_query_heap_info amdgpu_query_hw_ip_count amdgpu_query_hw_ip_info amdgpu_query_info +amdgpu_query_sensor_info amdgpu_read_mm_registers amdgpu_va_range_alloc amdgpu_va_range_free diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 6b2ded83..55884b24 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1058,6 +1058,24 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, int amdgpu_query_gds_info(amdgpu_device_handle dev, struct amdgpu_gds_resource_info *gds_info); +/** + * Query information about sensor. + * + * The return size is query-specific and depends on the "sensor_type" + * parameter. No more than "size" bytes is returned. + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* + * \param size - \c [in] Size of the returned value. + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, + unsigned size, void *value); + /** * Read a set of consecutive memory-mapped registers. * Not all registers are allowed to be read by userspace. diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index c5f5f6f4..f4b94c9e 100644 --- a/amdgpu/amdgpu_gpu_info.c +++ b/amdgpu/amdgpu_gpu_info.c @@ -318,3 +318,18 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, return 0; } + +int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, + unsigned size, void *value) +{ + struct drm_amdgpu_info request; + + memset(&request, 0, sizeof(request)); + request.return_pointer = (uintptr_t)value; + request.return_size = size; + request.query = AMDGPU_INFO_SENSOR; + request.sensor_info.type = sensor_type; + + return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, + sizeof(struct drm_amdgpu_info)); +} -- cgit v1.2.3-54-g00ecf From c9c77c37175be1a8f30e34d30f32a9f3f3df0dce Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 8 Apr 2017 21:58:46 +0200 Subject: configure.ac: bump version for release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 37022fee..a67480c1 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.78], + [2.4.79], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 47521438eb5c3f01c0bbae79c85ddbe8a5435a98 Mon Sep 17 00:00:00 2001 From: Tobias Jakobi Date: Wed, 5 Apr 2017 16:22:24 +0200 Subject: exynos: add C++ support to exynos_drmif header Add the usual extern "C" when compiling in C++ mode. Signed-off-by: Tobias Jakobi Reviewed-by: Eric Engestrom Reviewed-by: Emil Velikov --- exynos/exynos_drmif.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/exynos/exynos_drmif.h b/exynos/exynos_drmif.h index 626e3998..154439bb 100644 --- a/exynos/exynos_drmif.h +++ b/exynos/exynos_drmif.h @@ -31,6 +31,10 @@ #include #include "exynos_drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + struct exynos_device { int fd; }; @@ -109,4 +113,8 @@ int exynos_handle_event(struct exynos_device *dev, struct exynos_event_context *ctx); +#if defined(__cplusplus) +} +#endif + #endif /* EXYNOS_DRMIF_H_ */ -- cgit v1.2.3-54-g00ecf From 3f1df25e0b6ebff8841647dff867b62d66dc40d7 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Sun, 9 Apr 2017 22:48:46 +0100 Subject: intel: remove dead code Signed-off-by: Eric Engestrom --- intel/intel_bufmgr_gem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index e260f2dc..45a26da1 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -659,7 +659,6 @@ drm_intel_gem_bo_busy(drm_intel_bo *bo) } else { return false; } - return (ret == 0 && busy.busy); } static int -- cgit v1.2.3-54-g00ecf From 26e51e413be72256d4d416f8a9b9d04a78bfbf18 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 10 Apr 2017 11:15:52 +0200 Subject: etnaviv: sync uapi header Import the etnaviv header changes from kernel commits 9ad59fea162c ("drm/etnaviv: submit support for in-fences") and 78ec187f64fa ("drm/etnaviv: submit support for out-fences") for fence fd support. The drm_etnaviv_gem_submit structure was extended to include a flags field, new flags for in-fence and out-fence fds and an input/output fence fd field. This is one-way backwards compatible because old userspace code passing a short structure not including the flags field to new kernels will cause the remaining fields to be zero-filled. New userspace code must make sure to only pass the short structure to old kernels, though. Not generated using make headers_install, since the drm/etnaviv_drm.h uapi header is not installed yet by the kernel. Copied from the airlied/drm-next commit 78ec187f64fa. v2: improved commit message Signed-off-by: Philipp Zabel Reviewed-by: Christian Gmeiner Signed-off-by: Lucas Stach --- etnaviv/etnaviv_drm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/etnaviv/etnaviv_drm.h b/etnaviv/etnaviv_drm.h index 2584c1cc..76f6f78a 100644 --- a/etnaviv/etnaviv_drm.h +++ b/etnaviv/etnaviv_drm.h @@ -154,6 +154,12 @@ struct drm_etnaviv_gem_submit_bo { * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. */ +#define ETNA_SUBMIT_NO_IMPLICIT 0x0001 +#define ETNA_SUBMIT_FENCE_FD_IN 0x0002 +#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004 +#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \ + ETNA_SUBMIT_FENCE_FD_IN | \ + ETNA_SUBMIT_FENCE_FD_OUT) #define ETNA_PIPE_3D 0x00 #define ETNA_PIPE_2D 0x01 #define ETNA_PIPE_VG 0x02 @@ -167,6 +173,8 @@ struct drm_etnaviv_gem_submit { __u64 bos; /* in, ptr to array of submit_bo's */ __u64 relocs; /* in, ptr to array of submit_reloc's */ __u64 stream; /* in, ptr to cmdstream */ + __u32 flags; /* in, mask of ETNA_SUBMIT_x */ + __s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */ }; /* The normal way to synchronize with the GPU is just to CPU_PREP on -- cgit v1.2.3-54-g00ecf From 2f902a6844124291e8f4458ecae98543bd9a2802 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 10 Apr 2017 11:15:53 +0200 Subject: etnaviv: add fence fd support Add etna_cmd_stream_flush2 with in-fence fd and out-fence fd support for explicit fencing. v3: added etna_cmd_stream_flush2 to etnaviv/etnaviv-symbol-check v2: renamed etna_cmd_stream_flush_explicit to etna_cmd_stream_flush2 Signed-off-by: Philipp Zabel Reviewed-by: Eric Engestrom Reviewed-by: Christian Gmeiner Signed-off-by: Lucas Stach --- etnaviv/etnaviv-symbol-check | 1 + etnaviv/etnaviv_cmd_stream.c | 33 +++++++++++++++++++++++++++++---- etnaviv/etnaviv_drmif.h | 2 ++ 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/etnaviv/etnaviv-symbol-check b/etnaviv/etnaviv-symbol-check index 22afd168..0e2030e4 100755 --- a/etnaviv/etnaviv-symbol-check +++ b/etnaviv/etnaviv-symbol-check @@ -39,6 +39,7 @@ etna_cmd_stream_new etna_cmd_stream_del etna_cmd_stream_timestamp etna_cmd_stream_flush +etna_cmd_stream_flush2 etna_cmd_stream_finish etna_cmd_stream_reloc EOF diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c index 9ce3f363..3c7b0ed6 100644 --- a/etnaviv/etnaviv_cmd_stream.c +++ b/etnaviv/etnaviv_cmd_stream.c @@ -177,7 +177,8 @@ static uint32_t bo2idx(struct etna_cmd_stream *stream, struct etna_bo *bo, return idx; } -static void flush(struct etna_cmd_stream *stream) +static void flush(struct etna_cmd_stream *stream, int in_fence_fd, + int *out_fence_fd) { struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream); int ret, id = priv->pipe->id; @@ -194,8 +195,22 @@ static void flush(struct etna_cmd_stream *stream) .stream_size = stream->offset * 4, /* in bytes */ }; + if (in_fence_fd != -1) { + req.flags |= ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_NO_IMPLICIT; + req.fence_fd = in_fence_fd; + } + + if (out_fence_fd) + req.flags |= ETNA_SUBMIT_FENCE_FD_OUT; + + /* + * Pass the complete submit structure only if flags are set. Otherwise, + * only pass the fields up to, but not including the flags field for + * backwards compatiblity with older kernels. + */ ret = drmCommandWriteRead(gpu->dev->fd, DRM_ETNAVIV_GEM_SUBMIT, - &req, sizeof(req)); + &req, req.flags ? sizeof(req) : + offsetof(struct drm_etnaviv_gem_submit, flags)); if (ret) ERROR_MSG("submit failed: %d (%s)", ret, strerror(errno)); @@ -208,11 +223,21 @@ static void flush(struct etna_cmd_stream *stream) bo->current_stream = NULL; etna_bo_del(bo); } + + if (out_fence_fd) + *out_fence_fd = req.fence_fd; } void etna_cmd_stream_flush(struct etna_cmd_stream *stream) { - flush(stream); + flush(stream, -1, NULL); + reset_buffer(stream); +} + +void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd, + int *out_fence_fd) +{ + flush(stream, in_fence_fd, out_fence_fd); reset_buffer(stream); } @@ -220,7 +245,7 @@ void etna_cmd_stream_finish(struct etna_cmd_stream *stream) { struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream); - flush(stream); + flush(stream, -1, NULL); etna_pipe_wait(priv->pipe, priv->last_timestamp, 5000); reset_buffer(stream); } diff --git a/etnaviv/etnaviv_drmif.h b/etnaviv/etnaviv_drmif.h index 8119baad..87704acd 100644 --- a/etnaviv/etnaviv_drmif.h +++ b/etnaviv/etnaviv_drmif.h @@ -142,6 +142,8 @@ struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t siz void etna_cmd_stream_del(struct etna_cmd_stream *stream); uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream); void etna_cmd_stream_flush(struct etna_cmd_stream *stream); +void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd, + int *out_fence_fd); void etna_cmd_stream_finish(struct etna_cmd_stream *stream); static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream) -- cgit v1.2.3-54-g00ecf From f02719c5246d301a50d7e0356bf3fe61b1e945a1 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Sat, 15 Apr 2017 00:45:57 +0200 Subject: configure.ac: bump version for release Signed-off-by: Christian Gmeiner --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index a67480c1..e5158b7d 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.79], + [2.4.80], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From f45853802e910fd472f368a2d461708491fedfa3 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sat, 15 Apr 2017 14:43:17 -0400 Subject: freedreno: fix double-free on exit Fixes: a07ae97 ("freedreno: fix device close issues") Signed-off-by: Rob Clark --- freedreno/freedreno_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c index dba7ec47..12b95fd0 100644 --- a/freedreno/freedreno_device.c +++ b/freedreno/freedreno_device.c @@ -112,13 +112,13 @@ struct fd_device * fd_device_ref(struct fd_device *dev) static void fd_device_del_impl(struct fd_device *dev) { + int close_fd = dev->closefd ? dev->fd : -1; fd_bo_cache_cleanup(&dev->bo_cache, 0); drmHashDestroy(dev->handle_table); drmHashDestroy(dev->name_table); dev->funcs->destroy(dev); - if (dev->closefd) - close(dev->fd); - free(dev); + if (close_fd >= 0) + close(close_fd); } drm_private void fd_device_del_locked(struct fd_device *dev) -- cgit v1.2.3-54-g00ecf From d8d45a4938d99337503197fe6d28cbf20b16cc32 Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Thu, 13 Apr 2017 16:43:14 +0200 Subject: amdgpu: add the interface of waiting multiple fences Signed-off-by: Junwei Zhang [v2: allow returning the first signaled fence index] Signed-off-by: monk.liu [v3: - cleanup *status setting - fix amdgpu symbols check v4: simplify return from amdgpu_cs_wait_fences (suggested by Edward O'Callaghan)] Signed-off-by: Nicolai Hähnle Reviewed-by: Christian König (v1) Reviewed-by: Jammy Zhou (v1) Reviewed-by: Alex Deucher --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 23 +++++++++++++++ amdgpu/amdgpu_cs.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 4d1ae65c..81ef9b4e 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -33,6 +33,7 @@ amdgpu_cs_query_fence_status amdgpu_cs_query_reset_state amdgpu_cs_signal_semaphore amdgpu_cs_submit +amdgpu_cs_wait_fences amdgpu_cs_wait_semaphore amdgpu_device_deinitialize amdgpu_device_initialize diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 55884b24..fdea9050 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -907,6 +907,29 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, uint64_t flags, uint32_t *expired); +/** + * Wait for multiple fences + * + * \param fences - \c [in] The fence array to wait + * \param fence_count - \c [in] The fence count + * \param wait_all - \c [in] If true, wait all fences to be signaled, + * otherwise, wait at least one fence + * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds + * \param status - \c [out] '1' for signaled, '0' for timeout + * \param first - \c [out] the index of the first signaled fence from @fences + * + * \return 0 on success + * <0 - Negative POSIX Error code + * + * \note Currently it supports only one amdgpu_device. All fences come from + * the same amdgpu_device with the same fd. +*/ +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, + uint32_t fence_count, + bool wait_all, + uint64_t timeout_ns, + uint32_t *status, uint32_t *first); + /* * Query / Info API * diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index fb5b3a8c..779c7dbc 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -443,6 +443,77 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, return r; } +static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, + uint32_t fence_count, + bool wait_all, + uint64_t timeout_ns, + uint32_t *status, + uint32_t *first) +{ + struct drm_amdgpu_fence *drm_fences; + amdgpu_device_handle dev = fences[0].context->dev; + union drm_amdgpu_wait_fences args; + int r; + uint32_t i; + + drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count); + for (i = 0; i < fence_count; i++) { + drm_fences[i].ctx_id = fences[i].context->id; + drm_fences[i].ip_type = fences[i].ip_type; + drm_fences[i].ip_instance = fences[i].ip_instance; + drm_fences[i].ring = fences[i].ring; + drm_fences[i].seq_no = fences[i].fence; + } + + memset(&args, 0, sizeof(args)); + args.in.fences = (uint64_t)(uintptr_t)drm_fences; + args.in.fence_count = fence_count; + args.in.wait_all = wait_all; + args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns); + + r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args); + if (r) + return -errno; + + *status = args.out.status; + + if (first) + *first = args.out.first_signaled; + + return 0; +} + +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, + uint32_t fence_count, + bool wait_all, + uint64_t timeout_ns, + uint32_t *status, + uint32_t *first) +{ + uint32_t i; + + /* Sanity check */ + if (NULL == fences) + return -EINVAL; + if (NULL == status) + return -EINVAL; + if (fence_count <= 0) + return -EINVAL; + for (i = 0; i < fence_count; i++) { + if (NULL == fences[i].context) + return -EINVAL; + if (fences[i].ip_type >= AMDGPU_HW_IP_NUM) + return -EINVAL; + if (fences[i].ring >= AMDGPU_CS_MAX_RINGS) + return -EINVAL; + } + + *status = 0; + + return amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, + timeout_ns, status, first); +} + int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) { struct amdgpu_semaphore *gpu_semaphore; -- cgit v1.2.3-54-g00ecf From 90c304584af8e1bac6391530f59bbe9ccac8e06a Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Thu, 13 Apr 2017 16:43:58 +0200 Subject: amdgpu: add a test for amdgpu_cs_wait_fences Signed-off-by: monk.liu [v2: actually hook up the test case] Signed-off-by: Nicolai Hähnle Reviewed-by: Alex Deucher --- tests/amdgpu/basic_tests.c | 100 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 4dce67e9..8d5844b6 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -45,6 +45,7 @@ static void amdgpu_query_info_test(void); static void amdgpu_memory_alloc(void); static void amdgpu_command_submission_gfx(void); static void amdgpu_command_submission_compute(void); +static void amdgpu_command_submission_multi_fence(void); static void amdgpu_command_submission_sdma(void); static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); @@ -59,6 +60,7 @@ CU_TestInfo basic_tests[] = { { "Userptr Test", amdgpu_userptr_test }, { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, { "Command submission Test (Compute)", amdgpu_command_submission_compute }, + { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, { "SW semaphore Test", amdgpu_semaphore_test }, CU_TEST_INFO_NULL, @@ -1149,6 +1151,104 @@ static void amdgpu_command_submission_sdma(void) amdgpu_command_submission_sdma_copy_linear(); } +static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle ib_result_handle, ib_result_ce_handle; + void *ib_result_cpu, *ib_result_ce_cpu; + uint64_t ib_result_mc_address, ib_result_ce_mc_address; + struct amdgpu_cs_request ibs_request[2] = {0}; + struct amdgpu_cs_ib_info ib_info[2]; + struct amdgpu_cs_fence fence_status[2] = {0}; + uint32_t *ptr; + uint32_t expired; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle, va_handle_ce; + int r; + int i, ib_cs_num = 2; + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_ce_handle, &ib_result_ce_cpu, + &ib_result_ce_mc_address, &va_handle_ce); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_get_bo_list(device_handle, ib_result_handle, + ib_result_ce_handle, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); + + /* IT_SET_CE_DE_COUNTERS */ + ptr = ib_result_ce_cpu; + ptr[0] = 0xc0008900; + ptr[1] = 0; + ptr[2] = 0xc0008400; + ptr[3] = 1; + ib_info[0].ib_mc_address = ib_result_ce_mc_address; + ib_info[0].size = 4; + ib_info[0].flags = AMDGPU_IB_FLAG_CE; + + /* IT_WAIT_ON_CE_COUNTER */ + ptr = ib_result_cpu; + ptr[0] = 0xc0008600; + ptr[1] = 0x00000001; + ib_info[1].ib_mc_address = ib_result_mc_address; + ib_info[1].size = 2; + + for (i = 0; i < ib_cs_num; i++) { + ibs_request[i].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[i].number_of_ibs = 2; + ibs_request[i].ibs = ib_info; + ibs_request[i].resources = bo_list; + ibs_request[i].fence_info.handle = NULL; + } + + r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num); + + CU_ASSERT_EQUAL(r, 0); + + for (i = 0; i < ib_cs_num; i++) { + fence_status[i].context = context_handle; + fence_status[i].ip_type = AMDGPU_HW_IP_GFX; + fence_status[i].fence = ibs_request[i].seq_no; + } + + r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, + AMDGPU_TIMEOUT_INFINITE, + &expired, NULL); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce, + ib_result_ce_mc_address, 4096); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_command_submission_multi_fence(void) +{ + amdgpu_command_submission_multi_fence_wait_all(true); + amdgpu_command_submission_multi_fence_wait_all(false); +} + static void amdgpu_userptr_test(void) { int i, r, j; -- cgit v1.2.3-54-g00ecf From 7cfcd5ef4b394f66c4a6fde705cf7c583a0b0c7b Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 19 Apr 2017 02:13:19 +1000 Subject: amdgpu/: concisely && consistently check null ptrs in canonical form Be consistent and use the canonical form while sanity checking null pointers, also combine a few branches for brevity. v2: rebase on top of 'add amdgpu_cs_wait_fences' series. Signed-off-by: Edward O'Callaghan Reviewed-by: Nicolai Hähnle --- amdgpu/amdgpu_bo.c | 2 +- amdgpu/amdgpu_cs.c | 43 +++++++++++++------------------------------ amdgpu/amdgpu_gpu_info.c | 5 +++-- 3 files changed, 17 insertions(+), 33 deletions(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 9adfffa2..5ac456be 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -652,7 +652,7 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, return -EINVAL; list = malloc(number_of_resources * sizeof(struct drm_amdgpu_bo_list_entry)); - if (list == NULL) + if (!list) return -ENOMEM; args.in.operation = AMDGPU_BO_LIST_OP_UPDATE; diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 779c7dbc..0993a6d8 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -59,13 +59,11 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, int i, j, k; int r; - if (NULL == dev) - return -EINVAL; - if (NULL == context) + if (!dev || !context) return -EINVAL; gpu_context = calloc(1, sizeof(struct amdgpu_context)); - if (NULL == gpu_context) + if (!gpu_context) return -ENOMEM; gpu_context->dev = dev; @@ -110,7 +108,7 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context) int i, j, k; int r; - if (NULL == context) + if (!context) return -EINVAL; pthread_mutex_destroy(&context->sequence_mutex); @@ -330,9 +328,7 @@ int amdgpu_cs_submit(amdgpu_context_handle context, uint32_t i; int r; - if (NULL == context) - return -EINVAL; - if (NULL == ibs_request) + if (!context || !ibs_request) return -EINVAL; r = 0; @@ -416,11 +412,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, bool busy = true; int r; - if (NULL == fence) - return -EINVAL; - if (NULL == expired) - return -EINVAL; - if (NULL == fence->context) + if (!fence || !expired || !fence->context) return -EINVAL; if (fence->ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; @@ -493,12 +485,9 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, uint32_t i; /* Sanity check */ - if (NULL == fences) - return -EINVAL; - if (NULL == status) - return -EINVAL; - if (fence_count <= 0) + if (!fences || !status || !fence_count) return -EINVAL; + for (i = 0; i < fence_count; i++) { if (NULL == fences[i].context) return -EINVAL; @@ -518,11 +507,11 @@ int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) { struct amdgpu_semaphore *gpu_semaphore; - if (NULL == sem) + if (!sem) return -EINVAL; gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore)); - if (NULL == gpu_semaphore) + if (!gpu_semaphore) return -ENOMEM; atomic_set(&gpu_semaphore->refcount, 1); @@ -537,14 +526,12 @@ int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, uint32_t ring, amdgpu_semaphore_handle sem) { - if (NULL == ctx) + if (!ctx || !sem) return -EINVAL; if (ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; - if (NULL == sem) - return -EINVAL; /* sem has been signaled */ if (sem->signal_fence.context) return -EINVAL; @@ -565,14 +552,12 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, uint32_t ring, amdgpu_semaphore_handle sem) { - if (NULL == ctx) + if (!ctx || !sem) return -EINVAL; if (ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; - if (NULL == sem) - return -EINVAL; /* must signal first */ if (NULL == sem->signal_fence.context) return -EINVAL; @@ -585,9 +570,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem) { - if (NULL == sem) - return -EINVAL; - if (NULL == sem->signal_fence.context) + if (!sem || !sem->signal_fence.context) return -EINVAL; sem->signal_fence.context = NULL;; @@ -601,7 +584,7 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem) static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem) { - if (NULL == sem) + if (!sem) return -EINVAL; if (update_references(&sem->refcount, NULL)) diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index f4b94c9e..1efffc6f 100644 --- a/amdgpu/amdgpu_gpu_info.c +++ b/amdgpu/amdgpu_gpu_info.c @@ -234,8 +234,9 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) int amdgpu_query_gpu_info(amdgpu_device_handle dev, struct amdgpu_gpu_info *info) { - if ((dev == NULL) || (info == NULL)) + if (!dev || !info) return -EINVAL; + /* Get ASIC info*/ *info = dev->info; @@ -300,7 +301,7 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, struct drm_amdgpu_info_gds gds_config = {}; int r; - if (gds_info == NULL) + if (!gds_info) return -EINVAL; r = amdgpu_query_info(dev, AMDGPU_INFO_GDS_CONFIG, -- cgit v1.2.3-54-g00ecf From 691a21579962d2db2d5cb1de5286fa86ef22214f Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Tue, 18 Apr 2017 08:54:11 -0400 Subject: modetest: fix printing of fourcc on BE machines fourcc is not a string, it's a packed integer. This happens to work out on LE, but gets reversed on BE. Signed-off-by: Ilia Mirkin Reviewed-by: Michel Dänzer --- tests/modetest/modetest.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index c390d875..b8891ff5 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -174,6 +174,15 @@ static const char *mode_flag_names[] = { static bit_name_fn(mode_flag) +static void dump_fourcc(uint32_t fourcc) +{ + printf(" %c%c%c%c", + fourcc, + fourcc >> 8, + fourcc >> 16, + fourcc >> 24); +} + static void dump_encoders(struct device *dev) { drmModeEncoder *encoder; @@ -443,7 +452,7 @@ static void dump_planes(struct device *dev) printf(" formats:"); for (j = 0; j < ovr->count_formats; j++) - printf(" %4.4s", (char *)&ovr->formats[j]); + dump_fourcc(ovr->formats[j]); printf("\n"); if (plane->props) { -- cgit v1.2.3-54-g00ecf From d75a7ef1d7353cd122e5f8e975e69d2446eaad74 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 25 Apr 2017 11:29:33 -0700 Subject: Add pl111 as a KMS driver for utils. Signed-off-by: Eric Anholt Reviewed-by: Daniel Stone --- tests/util/kms.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/util/kms.c b/tests/util/kms.c index 959b6881..c008f78a 100644 --- a/tests/util/kms.c +++ b/tests/util/kms.c @@ -145,6 +145,7 @@ static const char * const modules[] = { "virtio_gpu", "mediatek", "meson", + "pl111", }; int util_open(const char *device, const char *module) -- cgit v1.2.3-54-g00ecf From 2ee1fd2470e96473f27080c01c5ecd710a6ab6c8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 25 Apr 2017 11:31:27 -0700 Subject: Add the DPI encoder/connector types to KMS utils. Signed-off-by: Eric Anholt Reviewed-by: Daniel Stone --- tests/util/kms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/util/kms.c b/tests/util/kms.c index c008f78a..028cc8d9 100644 --- a/tests/util/kms.c +++ b/tests/util/kms.c @@ -79,6 +79,7 @@ static const struct type_name encoder_type_names[] = { { DRM_MODE_ENCODER_VIRTUAL, "Virtual" }, { DRM_MODE_ENCODER_DSI, "DSI" }, { DRM_MODE_ENCODER_DPMST, "DPMST" }, + { DRM_MODE_ENCODER_DPI, "DPI" }, }; const char *util_lookup_encoder_type_name(unsigned int type) @@ -117,6 +118,7 @@ static const struct type_name connector_type_names[] = { { DRM_MODE_CONNECTOR_eDP, "eDP" }, { DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" }, { DRM_MODE_CONNECTOR_DSI, "DSI" }, + { DRM_MODE_CONNECTOR_DPI, "DPI" }, }; const char *util_lookup_connector_type_name(unsigned int type) -- cgit v1.2.3-54-g00ecf From 00aa2c18810efb896afd9ff0acbadd4aa9540fe6 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Sat, 22 Apr 2017 16:47:40 +1000 Subject: amdgpu: Use the canonical form in branch predicate Suggested-by: Emil Velikov Signed-off-by: Edward O'Callaghan Reviewed-by: Emil Velikov Reviewed-by: Nicolai Hähnle --- amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 0993a6d8..868eb7b0 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -559,7 +559,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, if (ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; /* must signal first */ - if (NULL == sem->signal_fence.context) + if (!sem->signal_fence.context) return -EINVAL; pthread_mutex_lock(&ctx->sequence_mutex); -- cgit v1.2.3-54-g00ecf From 7c27cd7c5da0b87cea0dacd454307e2613d3b415 Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Thu, 4 May 2017 10:48:56 -0400 Subject: Export drmDevicesEqual drmCompareBusInfo was almost this already, but it wasn't exported, its name didn't match its functionality, and while it almost looks like it was usable for sorting due to memcmp it wouldn't work if you had multiple bus types. I don't really want to think about defining a sensible sort order for bus types, so let's at least make it less of a trap for the caller. Invert its boolean sense to be 'true if equal', rename it to describe the types it actually operates on, and export. Reviewed-by: Eric Anholt Reviewed-by: Emil Velikov Signed-off-by: Adam Jackson --- xf86drm.c | 18 +++++++++--------- xf86drm.h | 2 ++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/xf86drm.c b/xf86drm.c index 685cf69d..29fea331 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -3029,32 +3029,32 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info) #endif } -static int drmCompareBusInfo(drmDevicePtr a, drmDevicePtr b) +int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b) { if (a == NULL || b == NULL) - return -1; + return 0; if (a->bustype != b->bustype) - return -1; + return 0; switch (a->bustype) { case DRM_BUS_PCI: - return memcmp(a->businfo.pci, b->businfo.pci, sizeof(drmPciBusInfo)); + return memcmp(a->businfo.pci, b->businfo.pci, sizeof(drmPciBusInfo)) == 0; case DRM_BUS_USB: - return memcmp(a->businfo.usb, b->businfo.usb, sizeof(drmUsbBusInfo)); + return memcmp(a->businfo.usb, b->businfo.usb, sizeof(drmUsbBusInfo)) == 0; case DRM_BUS_PLATFORM: - return memcmp(a->businfo.platform, b->businfo.platform, sizeof(drmPlatformBusInfo)); + return memcmp(a->businfo.platform, b->businfo.platform, sizeof(drmPlatformBusInfo)) == 0; case DRM_BUS_HOST1X: - return memcmp(a->businfo.host1x, b->businfo.host1x, sizeof(drmHost1xBusInfo)); + return memcmp(a->businfo.host1x, b->businfo.host1x, sizeof(drmHost1xBusInfo)) == 0; default: break; } - return -1; + return 0; } static int drmGetNodeType(const char *name) @@ -3669,7 +3669,7 @@ static void drmFoldDuplicatedDevices(drmDevicePtr local_devices[], int count) for (i = 0; i < count; i++) { for (j = i + 1; j < count; j++) { - if (drmCompareBusInfo(local_devices[i], local_devices[j]) == 0) { + if (drmCompareDevices(local_devices[i], local_devices[j])) { local_devices[i]->available_nodes |= local_devices[j]->available_nodes; node_type = log2(local_devices[j]->available_nodes); memcpy(local_devices[i]->nodes[node_type], diff --git a/xf86drm.h b/xf86drm.h index d75ca8ce..74f54f17 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -851,6 +851,8 @@ extern void drmFreeDevices(drmDevicePtr devices[], int count); extern int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device); extern int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices); +extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b); + #if defined(__cplusplus) } #endif -- cgit v1.2.3-54-g00ecf From 7040fea0280bad527ed4b3d5eee7d7bfbf303efc Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Thu, 4 May 2017 12:25:01 -0400 Subject: configure: Fix the check AC_HEADER_MAJOR only defines MAJOR_IN_SYSMACROS if major() is _not_ defined by alone. It is, but it warns, and that's ugly. To fix this, push -Werror into CFLAGS when invoking AC_HEADER_MAJOR so the warning makes the compilation test fail. Reviewed-by: Emil Velikov Signed-off-by: Adam Jackson --- configure.ac | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configure.ac b/configure.ac index e5158b7d..43fcf68f 100644 --- a/configure.ac +++ b/configure.ac @@ -54,7 +54,11 @@ AC_USE_SYSTEM_EXTENSIONS AC_SYS_LARGEFILE AC_FUNC_ALLOCA +save_CFLAGS="$CFLAGS" +export CFLAGS="$CFLAGS -Werror" AC_HEADER_MAJOR +CFLAGS="$save_CFLAGS" + AC_CHECK_HEADERS([sys/sysctl.h sys/select.h]) # Initialize libtool -- cgit v1.2.3-54-g00ecf From a2fa2e08692483cf9f4d06caa6e0f0add59e3343 Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Thu, 4 May 2017 15:57:14 -0400 Subject: Fix stray caller of drmCompareDevices Signed-off-by: Adam Jackson --- xf86drm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xf86drm.c b/xf86drm.c index 29fea331..728ac78c 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -3669,7 +3669,7 @@ static void drmFoldDuplicatedDevices(drmDevicePtr local_devices[], int count) for (i = 0; i < count; i++) { for (j = i + 1; j < count; j++) { - if (drmCompareDevices(local_devices[i], local_devices[j])) { + if (drmDevicesEqual(local_devices[i], local_devices[j])) { local_devices[i]->available_nodes |= local_devices[j]->available_nodes; node_type = log2(local_devices[j]->available_nodes); memcpy(local_devices[i]->nodes[node_type], -- cgit v1.2.3-54-g00ecf From 41be41f99eb53bd4998b1cd930fa63f0e552d971 Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Sat, 13 May 2017 23:03:55 +0200 Subject: amdgpu: add missing extern "C" headers Signed-off-by: Nicolai Hähnle Reviewed-by: Michel Dänzer Reviewed-by: Alex Xie --- amdgpu/amdgpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index fdea9050..1901fa8c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -37,6 +37,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + struct drm_amdgpu_info_hw_ip; /*--------------------------------------------------------------------------*/ @@ -1324,4 +1328,8 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); */ const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); +#ifdef __cplusplus +} +#endif + #endif /* #ifdef _AMDGPU_H_ */ -- cgit v1.2.3-54-g00ecf From 3f457d2a6e2dd74820ad7258edef573ab3b114fd Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 5 Jan 2017 02:24:53 +0800 Subject: amdgpu: add raven family id Signed-off-by: Hawking Zhang Signed-off-by: Chunming Zhou Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher Reviewed-by: Christian König --- include/drm/amdgpu_drm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 516a9f28..0de4cf6e 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -816,6 +816,7 @@ struct drm_amdgpu_info_vce_clock_table { #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ #define AMDGPU_FAMILY_AI 141 /* Vega10 */ +#define AMDGPU_FAMILY_RV 142 /* Raven */ #if defined(__cplusplus) } -- cgit v1.2.3-54-g00ecf From 5faee772721d2d2623e7f5980477de773bc73128 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Tue, 7 Feb 2017 11:10:48 -0500 Subject: amdgpu/drm: add AMDGPU_HW_IP_VCN_DEC Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Reviewed-by: Christian König --- include/drm/amdgpu_drm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 0de4cf6e..add5163a 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -406,7 +406,8 @@ struct drm_amdgpu_gem_va { #define AMDGPU_HW_IP_UVD 3 #define AMDGPU_HW_IP_VCE 4 #define AMDGPU_HW_IP_UVD_ENC 5 -#define AMDGPU_HW_IP_NUM 6 +#define AMDGPU_HW_IP_VCN_DEC 6 +#define AMDGPU_HW_IP_NUM 7 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 -- cgit v1.2.3-54-g00ecf From eeb51df3ced003515ba4a71492eeb86c145cb77e Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Tue, 21 Feb 2017 11:14:09 -0500 Subject: amdgpu/drm: add AMDGPU_HW_IP_VCN_ENC Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Reviewed-by: Christian König --- include/drm/amdgpu_drm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index add5163a..8cfe68c5 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -407,7 +407,8 @@ struct drm_amdgpu_gem_va { #define AMDGPU_HW_IP_VCE 4 #define AMDGPU_HW_IP_UVD_ENC 5 #define AMDGPU_HW_IP_VCN_DEC 6 -#define AMDGPU_HW_IP_NUM 7 +#define AMDGPU_HW_IP_VCN_ENC 7 +#define AMDGPU_HW_IP_NUM 8 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 -- cgit v1.2.3-54-g00ecf From 81312f3730c14a2930a7784493701809c7f04a26 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 24 May 2017 17:01:36 +0200 Subject: Bump version to 2.4.81 --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 43fcf68f..1cfb8c27 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.80], + [2.4.81], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From bbe998791d6cd0d5c048beba6ae8a6dbbf8185be Mon Sep 17 00:00:00 2001 From: Elliott Hughes Date: Sat, 20 May 2017 11:24:29 -0700 Subject: Android's major/minor/makedev live in Bug: https://github.com/android-ndk/ndk/issues/398 Signed-off-by: Rob Herring --- Android.common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/Android.common.mk b/Android.common.mk index 35c0f02c..4b5462f6 100644 --- a/Android.common.mk +++ b/Android.common.mk @@ -1,5 +1,6 @@ # XXX: Consider moving these to config.h analogous to autoconf. LOCAL_CFLAGS += \ + -DMAJOR_IN_SYSMACROS=1 -DHAVE_VISIBILITY=1 \ -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 -- cgit v1.2.3-54-g00ecf From ce9e3ba6e2cc65e1e9e6e05a5f326c4dd25ab2c4 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Sun, 28 May 2017 09:34:13 -0500 Subject: Android: fix missing trailing \ In commit bbe998791d6c ("Android's major/minor/makedev live in "), it didn't apply cleanly and I missed the trailing \, so add it here. Signed-off-by: Rob Herring --- Android.common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Android.common.mk b/Android.common.mk index 4b5462f6..b45ca10f 100644 --- a/Android.common.mk +++ b/Android.common.mk @@ -1,6 +1,6 @@ # XXX: Consider moving these to config.h analogous to autoconf. LOCAL_CFLAGS += \ - -DMAJOR_IN_SYSMACROS=1 + -DMAJOR_IN_SYSMACROS=1 \ -DHAVE_VISIBILITY=1 \ -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 -- cgit v1.2.3-54-g00ecf From 1b8db1777983b917384c2ed78ed5a2ab653d9e55 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Wed, 31 May 2017 13:48:53 +0100 Subject: headers: sync drm_fourcc.h with airlied/drm-next This adds a bunch of modifiers stuff, as well as a few new formats. Includes the following changes: ebbb0e5cfd2ceb1150b1 drm: add extern C guard for the UAPI headers b9fb2a21ac8058965a6b drm_fourcc: Document linear modifier af913418261d6d3e7a29 drm_fourcc: Fix DRM_FORMAT_MOD_LINEAR #define fd056f05b9fcba35b77e drm: add fourcc codes for 16bit R and RG 73f1a5858bf82f3bf232 drm/fourcc: add vivante tiled layout format modifiers ba2b5277dc52cc96944d drm: add RGB formats with separate alpha plane 5e91144dd702d068b22a drm/tegra: Add tiling FB modifiers Generated using `make headers_install` from airlied/drm-next at commit 2a1720376adda5ecf8e636fbfb05339c7dad1c55 Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- include/drm/drm_fourcc.h | 126 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index 4d8da699..55e30104 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -26,6 +26,10 @@ #include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ ((__u32)(c) << 16) | ((__u32)(d) << 24)) @@ -37,10 +41,17 @@ /* 8 bpp Red */ #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ +/* 16 bpp Red */ +#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ + /* 16 bpp RG */ #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ +/* 32 bpp RG */ +#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ +#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ + /* 8 bpp RGB */ #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ @@ -102,6 +113,20 @@ #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ +/* + * 2 plane RGB + A + * index 0 = RGB plane, same format as the corresponding non _A8 format has + * index 1 = A plane, [7:0] A + */ +#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') +#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') +#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') +#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') +#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') +#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') +#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') +#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') + /* * 2 plane YCbCr * index 0 = Y plane, [7:0] Y @@ -150,11 +175,13 @@ /* Vendor Ids: */ #define DRM_FORMAT_MOD_NONE 0 +#define DRM_FORMAT_MOD_VENDOR_NONE 0 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 #define DRM_FORMAT_MOD_VENDOR_NV 0x03 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 +#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 /* add more to the end as needed */ #define fourcc_mod_code(vendor, val) \ @@ -168,6 +195,16 @@ * authoritative source for all of these. */ +/* + * Linear Layout + * + * Just plain linear layout. Note that this is different from no specifying any + * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), + * which tells the driver to also take driver-internal information into account + * and so might actually result in a tiled framebuffer. + */ +#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) + /* Intel framebuffer modifiers */ /* @@ -229,4 +266,93 @@ */ #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) +/* Vivante framebuffer modifiers */ + +/* + * Vivante 4x4 tiling layout + * + * This is a simple tiled layout using tiles of 4x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) + +/* + * Vivante 64x64 super-tiling layout + * + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile + * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- + * major layout. + * + * For more information: see + * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling + */ +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) + +/* + * Vivante 4x4 tiling layout for dual-pipe + * + * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a + * different base address. Offsets from the base addresses are therefore halved + * compared to the non-split tiled layout. + */ +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) + +/* + * Vivante 64x64 super-tiling layout for dual-pipe + * + * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile + * starts at a different base address. Offsets from the base addresses are + * therefore halved compared to the non-split super-tiled layout. + */ +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) + + +/* NVIDIA Tegra frame buffer modifiers */ + +/* + * Some modifiers take parameters, for example the number of vertical GOBs in + * a block. Reserve the lower 32 bits for parameters + */ +#define __fourcc_mod_tegra_mode_shift 32 +#define fourcc_mod_tegra_code(val, params) \ + fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) +#define fourcc_mod_tegra_mod(m) \ + (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) +#define fourcc_mod_tegra_param(m) \ + (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) + +/* + * Tegra Tiled Layout, used by Tegra 2, 3 and 4. + * + * Pixels are arranged in simple tiles of 16 x 16 bytes. + */ +#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) + +/* + * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 + * + * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked + * vertically by a power of 2 (1 to 32 GOBs) to form a block. + * + * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. + * + * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. + * Valid values are: + * + * 0 == ONE_GOB + * 1 == TWO_GOBS + * 2 == FOUR_GOBS + * 3 == EIGHT_GOBS + * 4 == SIXTEEN_GOBS + * 5 == THIRTYTWO_GOBS + * + * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format + * in full detail. + */ +#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) + +#if defined(__cplusplus) +} +#endif + #endif /* DRM_FOURCC_H */ -- cgit v1.2.3-54-g00ecf From 48aac8c6ef301be5ed4cf824779baa3c98981a90 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Wed, 31 May 2017 14:47:40 +0100 Subject: headers: sync drm_sarea.h with airlied/drm-next Adds the C++ extern guards from ebbb0e5cfd2ceb1150b1 drm: add extern C guard for the UAPI headers Generated using `make headers_install` from airlied/drm-next at commit 2a1720376adda5ecf8e636fbfb05339c7dad1c55 Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- include/drm/drm_sarea.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h index 502934ed..93025be8 100644 --- a/include/drm/drm_sarea.h +++ b/include/drm/drm_sarea.h @@ -34,6 +34,10 @@ #include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + /* SAREA area needs to be at least a page */ #if defined(__alpha__) #define SAREA_MAX 0x2000U @@ -81,4 +85,8 @@ typedef struct drm_sarea_drawable drm_sarea_drawable_t; typedef struct drm_sarea_frame drm_sarea_frame_t; typedef struct drm_sarea drm_sarea_t; +#if defined(__cplusplus) +} +#endif + #endif /* _DRM_SAREA_H_ */ -- cgit v1.2.3-54-g00ecf From ec65d19809121b460c80b45509ed12a4cdbde4b8 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Mon, 3 Apr 2017 14:44:04 -0400 Subject: tests/amdgpu: rename uvd messages to decode messages It will be shared with VCN decode Signed-off-by: Leo Liu Acked-by: Christian König --- tests/amdgpu/cs_tests.c | 2 +- tests/amdgpu/decode_messages.h | 813 +++++++++++++++++++++++++++++++++++++++++ tests/amdgpu/uvd_messages.h | 813 ----------------------------------------- 3 files changed, 814 insertions(+), 814 deletions(-) create mode 100644 tests/amdgpu/decode_messages.h delete mode 100644 tests/amdgpu/uvd_messages.h diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 342815de..65f2434b 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -32,7 +32,7 @@ #include "util_math.h" #include "amdgpu_test.h" -#include "uvd_messages.h" +#include "decode_messages.h" #include "amdgpu_drm.h" #include "amdgpu_internal.h" diff --git a/tests/amdgpu/decode_messages.h b/tests/amdgpu/decode_messages.h new file mode 100644 index 00000000..09abc37e --- /dev/null +++ b/tests/amdgpu/decode_messages.h @@ -0,0 +1,813 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _DECODE_MESSAGES_H_ +#define _DECODE_MESSAGES_H_ + +static const uint8_t uvd_create_msg[] = { + 0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00, + 0xe0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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+static const uint8_t uvd_bitstream[] ={ + 0x00,0x00,0x01,0x25,0xb8,0x20,0x20,0x21,0x44,0xc5,0x00,0x01,0x57,0x9b,0xef,0xbe, + 0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb, + 0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef, + 0xbe,0xfb,0xef,0xbe,0xff,0x87,0xff,0xc2,0x58,0x0e,0x00,0x02,0x02,0xa0,0x00,0x20, + 0x3a,0x00,0x0d,0x00,0x01,0x01,0xa4,0xcb,0x94,0x73,0xeb,0xae,0xba,0xeb,0xae,0xba, + 0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb, + 0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae, + 0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba, + 0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb, + 0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae, + 0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba, + 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; + +static const uint8_t uvd_it_scaling_table[] = { + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, +}; + +#endif /* _DECODE_MESSAGES_H_ */ diff --git a/tests/amdgpu/uvd_messages.h b/tests/amdgpu/uvd_messages.h deleted file mode 100644 index 00235cbb..00000000 --- a/tests/amdgpu/uvd_messages.h +++ /dev/null @@ -1,813 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _UVD_MESSAGES_H_ -#define _UVD_MESSAGES_H_ - -static const uint8_t uvd_create_msg[] = { - 0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00, - 0xe0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -}; - -static const uint8_t uvd_it_scaling_table[] = { - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, -}; - -#endif /* _UVD_MESSAGES_H_ */ -- cgit v1.2.3-54-g00ecf From 1851f1b57a96547d5b8f8b651768561ee6927b16 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Mon, 3 Apr 2017 14:52:15 -0400 Subject: tests/amdgpu: separate decode messages AVC decode messages will be common with VCN decode Signed-off-by: Leo Liu Acked-by: Christian König --- tests/amdgpu/cs_tests.c | 3 ++- tests/amdgpu/decode_messages.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 65f2434b..fe78326f 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -289,7 +289,8 @@ static void amdgpu_cs_uvd_decode(void) r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr); CU_ASSERT_EQUAL(r, 0); - memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg)); + memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg)); + memcpy(ptr + sizeof(uvd_decode_msg), avc_decode_msg, sizeof(avc_decode_msg)); if (family_id >= AMDGPU_FAMILY_VI) { ptr[0x10] = 7; diff --git a/tests/amdgpu/decode_messages.h b/tests/amdgpu/decode_messages.h index 09abc37e..edfba3b7 100644 --- a/tests/amdgpu/decode_messages.h +++ b/tests/amdgpu/decode_messages.h @@ -356,6 +356,9 @@ static const uint8_t uvd_decode_msg[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; + +static const uint8_t avc_decode_msg[] = { 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x88,0x00,0x00,0x00, 0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, -- cgit v1.2.3-54-g00ecf From 01096f2122234c48c959b5bcf451873de459bc47 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Mon, 3 Apr 2017 14:59:15 -0400 Subject: tests/amdgpu: move decode sum to common Signed-off-by: Leo Liu Acked-by: Christian König --- tests/amdgpu/cs_tests.c | 2 +- tests/amdgpu/decode_messages.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index fe78326f..081ec9c2 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -378,7 +378,7 @@ static void amdgpu_cs_uvd_decode(void) /* TODO: use a real CRC32 */ for (i = 0, sum = 0; i < dt_size; ++i) sum += ptr[i]; - CU_ASSERT_EQUAL(sum, 0x20345d8); + CU_ASSERT_EQUAL(sum, SUM_DECODE); r = amdgpu_bo_cpu_unmap(buf_handle); CU_ASSERT_EQUAL(r, 0); diff --git a/tests/amdgpu/decode_messages.h b/tests/amdgpu/decode_messages.h index edfba3b7..c5c96f80 100644 --- a/tests/amdgpu/decode_messages.h +++ b/tests/amdgpu/decode_messages.h @@ -24,6 +24,8 @@ #ifndef _DECODE_MESSAGES_H_ #define _DECODE_MESSAGES_H_ +#define SUM_DECODE 0x20345d8 + static const uint8_t uvd_create_msg[] = { 0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00, -- cgit v1.2.3-54-g00ecf From c1f5eea50ff5d4c1a76bb16cbda5530a7bb8e8d1 Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Mon, 3 Apr 2017 15:52:31 -0400 Subject: tests/amdgpu: add vcn tests support and sets Signed-off-by: Leo Liu Acked-by: Christian König --- tests/amdgpu/Makefile.am | 3 +- tests/amdgpu/amdgpu_test.c | 6 + tests/amdgpu/amdgpu_test.h | 15 +++ tests/amdgpu/vcn_tests.c | 277 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 300 insertions(+), 1 deletion(-) create mode 100644 tests/amdgpu/vcn_tests.c diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index c1c3a32e..d4572bec 100644 --- a/tests/amdgpu/Makefile.am +++ b/tests/amdgpu/Makefile.am @@ -26,4 +26,5 @@ amdgpu_test_SOURCES = \ uvd_messages.h \ vce_tests.c \ vce_ib.h \ - frame.h + frame.h \ + vcn_tests.c diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 3fd6820a..bc901a9e 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -85,6 +85,12 @@ static CU_SuiteInfo suites[] = { .pCleanupFunc = suite_vce_tests_clean, .pTests = vce_tests, }, + { + .pName = "VCN Tests", + .pInitFunc = suite_vcn_tests_init, + .pCleanupFunc = suite_vcn_tests_clean, + .pTests = vcn_tests, + }, CU_SUITE_INFO_NULL, }; diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index e30e2312..c75a07a4 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -104,6 +104,21 @@ int suite_vce_tests_clean(); */ extern CU_TestInfo vce_tests[]; +/** ++ * Initialize vcn test suite ++ */ +int suite_vcn_tests_init(); + +/** ++ * Deinitialize vcn test suite ++ */ +int suite_vcn_tests_clean(); + +/** ++ * Tests in vcn test suite ++ */ +extern CU_TestInfo vcn_tests[]; + /** * Helper functions */ diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c new file mode 100644 index 00000000..0d3991a8 --- /dev/null +++ b/tests/amdgpu/vcn_tests.c @@ -0,0 +1,277 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include + +#include "CUnit/Basic.h" + +#include "util_math.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" + +#define IB_SIZE 4096 +#define MAX_RESOURCES 16 + +struct amdgpu_vcn_bo { + amdgpu_bo_handle handle; + amdgpu_va_handle va_handle; + uint64_t addr; + uint64_t size; + uint8_t *ptr; +}; + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; +static uint32_t family_id; + +static amdgpu_context_handle context_handle; +static amdgpu_bo_handle ib_handle; +static amdgpu_va_handle ib_va_handle; +static uint64_t ib_mc_address; +static uint32_t *ib_cpu; + +static amdgpu_bo_handle resources[MAX_RESOURCES]; +static unsigned num_resources; + +static void amdgpu_cs_vcn_dec_create(void); +static void amdgpu_cs_vcn_dec_decode(void); +static void amdgpu_cs_vcn_dec_destroy(void); + +static void amdgpu_cs_vcn_enc_create(void); +static void amdgpu_cs_vcn_enc_encode(void); +static void amdgpu_cs_vcn_enc_destroy(void); + +CU_TestInfo vcn_tests[] = { + + { "VCN DEC create", amdgpu_cs_vcn_dec_create }, + { "VCN DEC decode", amdgpu_cs_vcn_dec_decode }, + { "VCN DEC destroy", amdgpu_cs_vcn_dec_destroy }, + + { "VCN ENC create", amdgpu_cs_vcn_enc_create }, + { "VCN ENC decode", amdgpu_cs_vcn_enc_encode }, + { "VCN ENC destroy", amdgpu_cs_vcn_enc_destroy }, + CU_TEST_INFO_NULL, +}; + +int suite_vcn_tests_init(void) +{ + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + if (r) + return CUE_SINIT_FAILED; + + family_id = device_handle->info.family_id; + + if (family_id < AMDGPU_FAMILY_RV) { + printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n"); + return CUE_SUCCESS; + } + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + if (r) + return CUE_SINIT_FAILED; + + r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_handle, (void**)&ib_cpu, + &ib_mc_address, &ib_va_handle); + if (r) + return CUE_SINIT_FAILED; + + return CUE_SUCCESS; +} + +int suite_vcn_tests_clean(void) +{ + int r; + + if (family_id < AMDGPU_FAMILY_RV) { + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + } else { + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + } + + return CUE_SUCCESS; +} + +static int submit(unsigned ndw, unsigned ip) +{ + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info = {0}; + struct amdgpu_cs_fence fence_status = {0}; + uint32_t expired; + int r; + + ib_info.ib_mc_address = ib_mc_address; + ib_info.size = ndw; + + ibs_request.ip_type = ip; + + r = amdgpu_bo_list_create(device_handle, num_resources, resources, + NULL, &ibs_request.resources); + if (r) + return r; + + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.fence_info.handle = NULL; + + r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); + if (r) + return r; + + r = amdgpu_bo_list_destroy(ibs_request.resources); + if (r) + return r; + + fence_status.context = context_handle; + fence_status.ip_type = ip; + fence_status.fence = ibs_request.seq_no; + + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); + if (r) + return r; + + return 0; +} + +static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo, + unsigned size, unsigned domain) +{ + struct amdgpu_bo_alloc_request req = {0}; + amdgpu_bo_handle buf_handle; + amdgpu_va_handle va_handle; + uint64_t va = 0; + int r; + + req.alloc_size = ALIGN(size, 4096); + req.preferred_heap = domain; + r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_va_range_alloc(device_handle, + amdgpu_gpu_va_range_general, + req.alloc_size, 1, 0, &va, + &va_handle, 0); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, + AMDGPU_VA_OP_MAP); + CU_ASSERT_EQUAL(r, 0); + vcn_bo->addr = va; + vcn_bo->handle = buf_handle; + vcn_bo->size = req.alloc_size; + vcn_bo->va_handle = va_handle; + r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr); + CU_ASSERT_EQUAL(r, 0); + memset(vcn_bo->ptr, 0, size); + r = amdgpu_bo_cpu_unmap(vcn_bo->handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void free_resource(struct amdgpu_vcn_bo *vcn_bo) +{ + int r; + + r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size, + vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_va_range_free(vcn_bo->va_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_free(vcn_bo->handle); + CU_ASSERT_EQUAL(r, 0); + memset(vcn_bo, 0, sizeof(*vcn_bo)); +} + +static void amdgpu_cs_vcn_dec_create(void) +{ + if (family_id < AMDGPU_FAMILY_RV) + return; + + /* TODO */ +} + +static void amdgpu_cs_vcn_dec_decode(void) +{ + if (family_id < AMDGPU_FAMILY_RV) + return; + + /* TODO */ +} + +static void amdgpu_cs_vcn_dec_destroy(void) +{ + if (family_id < AMDGPU_FAMILY_RV) + return; + + /* TODO */ +} + +static void amdgpu_cs_vcn_enc_create(void) +{ + if (family_id < AMDGPU_FAMILY_RV) + return; + + /* TODO */ +} + +static void amdgpu_cs_vcn_enc_encode(void) +{ + if (family_id < AMDGPU_FAMILY_RV) + return; + + /* TODO */ +} + +static void amdgpu_cs_vcn_enc_destroy(void) +{ + if (family_id < AMDGPU_FAMILY_RV) + return; + + /* TODO */ +} -- cgit v1.2.3-54-g00ecf From 16444e1061a2dcc80cdc80d64b6ae9ef2deee5fe Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Mon, 3 Apr 2017 15:58:31 -0400 Subject: tests/amdgpu: implement vcn dec unit tests Signed-off-by: Leo Liu Acked-by: Christian König --- tests/amdgpu/decode_messages.h | 30 +++++++++ tests/amdgpu/vcn_tests.c | 139 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 166 insertions(+), 3 deletions(-) diff --git a/tests/amdgpu/decode_messages.h b/tests/amdgpu/decode_messages.h index c5c96f80..bd6fe4b6 100644 --- a/tests/amdgpu/decode_messages.h +++ b/tests/amdgpu/decode_messages.h @@ -815,4 +815,34 @@ static const uint8_t uvd_it_scaling_table[] = { 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, }; +static const uint8_t vcn_dec_create_msg[] = { + 0x28,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x28,0x00,0x00,0x00, + 0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00, +}; + +static const uint8_t vcn_dec_decode_msg[] = { + 0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00, + 0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00, + 0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x94,0x6b,0x00, + 0x96,0x4e,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x50,0x00, + 0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; + +static const uint8_t vcn_dec_destroy_msg[] = { + 0x28,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00, + 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, +}; + #endif /* _DECODE_MESSAGES_H_ */ diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c index 0d3991a8..2b1696dd 100644 --- a/tests/amdgpu/vcn_tests.c +++ b/tests/amdgpu/vcn_tests.c @@ -35,6 +35,7 @@ #include "amdgpu_test.h" #include "amdgpu_drm.h" #include "amdgpu_internal.h" +#include "decode_messages.h" #define IB_SIZE 4096 #define MAX_RESOURCES 16 @@ -228,28 +229,160 @@ static void free_resource(struct amdgpu_vcn_bo *vcn_bo) memset(vcn_bo, 0, sizeof(*vcn_bo)); } +static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx) +{ + ib_cpu[(*idx)++] = 0x81C4; + ib_cpu[(*idx)++] = addr; + ib_cpu[(*idx)++] = 0x81C5; + ib_cpu[(*idx)++] = addr >> 32; + ib_cpu[(*idx)++] = 0x81C3; + ib_cpu[(*idx)++] = cmd << 1; +} + static void amdgpu_cs_vcn_dec_create(void) { + struct amdgpu_vcn_bo msg_buf; + int len, r; + if (family_id < AMDGPU_FAMILY_RV) return; - /* TODO */ + num_resources = 0; + alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT); + resources[num_resources++] = msg_buf.handle; + resources[num_resources++] = ib_handle; + + r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr); + CU_ASSERT_EQUAL(r, 0); + + memset(msg_buf.ptr, 0, 4096); + memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg)); + + len = 0; + ib_cpu[len++] = 0x81C4; + ib_cpu[len++] = msg_buf.addr; + ib_cpu[len++] = 0x81C5; + ib_cpu[len++] = msg_buf.addr >> 32; + ib_cpu[len++] = 0x81C3; + ib_cpu[len++] = 0; + for (; len % 16; ++len) + ib_cpu[len] = 0x81ff; + + r = submit(len, AMDGPU_HW_IP_VCN_DEC); + CU_ASSERT_EQUAL(r, 0); + + free_resource(&msg_buf); } static void amdgpu_cs_vcn_dec_decode(void) { + const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280; + uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum; + struct amdgpu_vcn_bo dec_buf; + int size, len, i, r; + uint8_t *dec; + if (family_id < AMDGPU_FAMILY_RV) return; - /* TODO */ + size = 4*1024; /* msg */ + size += 4*1024; /* fb */ + size += 4096; /*it_scaling_table*/ + size += ALIGN(sizeof(uvd_bitstream), 4*1024); + size += ALIGN(dpb_size, 4*1024); + size += ALIGN(dt_size, 4*1024); + + num_resources = 0; + alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT); + resources[num_resources++] = dec_buf.handle; + resources[num_resources++] = ib_handle; + + r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); + dec = dec_buf.ptr; + + CU_ASSERT_EQUAL(r, 0); + memset(dec_buf.ptr, 0, size); + memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg)); + memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg), + avc_decode_msg, sizeof(avc_decode_msg)); + + dec += 4*1024; + dec += 4*1024; + memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table)); + + dec += 4*1024; + memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream)); + + dec += ALIGN(sizeof(uvd_bitstream), 4*1024); + + dec += ALIGN(dpb_size, 4*1024); + + msg_addr = dec_buf.addr; + fb_addr = msg_addr + 4*1024; + it_addr = fb_addr + 4*1024; + bs_addr = it_addr + 4*1024; + dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); + ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); + dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); + + len = 0; + vcn_dec_cmd(msg_addr, 0x0, &len); + vcn_dec_cmd(dpb_addr, 0x1, &len); + vcn_dec_cmd(dt_addr, 0x2, &len); + vcn_dec_cmd(fb_addr, 0x3, &len); + vcn_dec_cmd(bs_addr, 0x100, &len); + vcn_dec_cmd(it_addr, 0x204, &len); + vcn_dec_cmd(ctx_addr, 0x206, &len); + + ib_cpu[len++] = 0x81C6; + ib_cpu[len++] = 0x1; + for (; len % 16; ++len) + ib_cpu[len] = 0x80000000; + + r = submit(len, AMDGPU_HW_IP_VCN_DEC); + CU_ASSERT_EQUAL(r, 0); + + for (i = 0, sum = 0; i < dt_size; ++i) + sum += dec[i]; + + CU_ASSERT_EQUAL(sum, SUM_DECODE); + + free_resource(&dec_buf); } static void amdgpu_cs_vcn_dec_destroy(void) { + struct amdgpu_vcn_bo msg_buf; + int len, r; + if (family_id < AMDGPU_FAMILY_RV) return; - /* TODO */ + num_resources = 0; + alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT); + resources[num_resources++] = msg_buf.handle; + resources[num_resources++] = ib_handle; + + r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr); + CU_ASSERT_EQUAL(r, 0); + + memset(msg_buf.ptr, 0, 1024); + memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg)); + + len = 0; + ib_cpu[len++] = 0x81C4; + ib_cpu[len++] = msg_buf.addr; + ib_cpu[len++] = 0x81C5; + ib_cpu[len++] = msg_buf.addr >> 32; + ib_cpu[len++] = 0x81C3; + ib_cpu[len++] = 0; + for (; len % 16; ++len) + ib_cpu[len] = 0x80000000; + + r = submit(len, AMDGPU_HW_IP_VCN_DEC); + CU_ASSERT_EQUAL(r, 0); + + free_resource(&msg_buf); } static void amdgpu_cs_vcn_enc_create(void) -- cgit v1.2.3-54-g00ecf From b6f450e065a538d566c71872ce890ff07956e3eb Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Mon, 5 Jun 2017 14:04:11 -0400 Subject: tests/amdgpu: Fix device_id option The device_id option [-d] was badly broken. This commit fixes the width (was 8 is now 16 bits) as well as enables searches without specifying a bus id. It was also comparing "dev" from the bus field which is not the PCI device id. Reviewed-by: Alex Deucher Signed-off-by: Tom St Denis --- tests/amdgpu/amdgpu_test.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index bc901a9e..1d44b09e 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -270,25 +270,25 @@ static void amdgpu_print_devices() /* Find a match AMD device in PCI bus * Return the index of the device or -1 if not found */ -static int amdgpu_find_device(uint8_t bus, uint8_t dev) +static int amdgpu_find_device(uint8_t bus, uint16_t dev) { int i; drmDevicePtr device; - for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++) + for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) { if (drmGetDevice2(drm_amdgpu[i], DRM_DEVICE_GET_PCI_REVISION, &device) == 0) { if (device->bustype == DRM_BUS_PCI) - if (device->businfo.pci->bus == bus && - device->businfo.pci->dev == dev) { - + if ((bus == 0xFF || device->businfo.pci->bus == bus) && + device->deviceinfo.pci->device_id == dev) { drmFreeDevice(&device); return i; } drmFreeDevice(&device); } + } return -1; } @@ -331,7 +331,7 @@ int main(int argc, char **argv) pci_bus_id = atoi(optarg); break; case 'd': - pci_device_id = atoi(optarg); + sscanf(optarg, "%x", &pci_device_id); break; case 'p': display_devices = 1; @@ -365,10 +365,10 @@ int main(int argc, char **argv) exit(EXIT_SUCCESS); } - if (pci_bus_id > 0) { + if (pci_bus_id > 0 || pci_device_id) { /* A device was specified to run the test */ - test_device_index = amdgpu_find_device((uint8_t)pci_bus_id, - (uint8_t)pci_device_id); + test_device_index = amdgpu_find_device(pci_bus_id, + pci_device_id); if (test_device_index >= 0) { /* Most tests run on device of drm_amdgpu[0]. -- cgit v1.2.3-54-g00ecf From 57d67d55d32e9196fceef41a693c89d0eb163a72 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Mon, 12 Jun 2017 17:15:21 +0900 Subject: tests/amdgpu: s/uvd_messages.h/decode_messages.h/ in Makefile.am Fixes make distcheck with amdgpu enabled. Fixes: ec65d1980912 ("tests/amdgpu: rename uvd messages to decode messages") Trivial. --- tests/amdgpu/Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index d4572bec..9e085784 100644 --- a/tests/amdgpu/Makefile.am +++ b/tests/amdgpu/Makefile.am @@ -23,7 +23,7 @@ amdgpu_test_SOURCES = \ basic_tests.c \ bo_tests.c \ cs_tests.c \ - uvd_messages.h \ + decode_messages.h \ vce_tests.c \ vce_ib.h \ frame.h \ -- cgit v1.2.3-54-g00ecf From 87dac00db38fa962c2fd6aa66c8482a9d7464903 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Mon, 12 Jun 2017 19:00:13 +0900 Subject: amdgpu: Add .editorconfig file for amdgpu coding style The .editorconfig file in the toplevel directory doesn't match. Acked-by: Christian König Reviewed-by: Alex Deucher --- amdgpu/.editorconfig | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 amdgpu/.editorconfig diff --git a/amdgpu/.editorconfig b/amdgpu/.editorconfig new file mode 100644 index 00000000..2528d675 --- /dev/null +++ b/amdgpu/.editorconfig @@ -0,0 +1,9 @@ +# To use this config with your editor, follow the instructions at: +# http://editorconfig.org + +[*] +charset = utf-8 +indent_style = tab +indent_size = 8 +tab_width = 8 +insert_final_newline = true -- cgit v1.2.3-54-g00ecf From 7e6bf88cac315a9fa41818cf72a7b5d18a2cb1fc Mon Sep 17 00:00:00 2001 From: Xiaojie Yuan Date: Wed, 31 May 2017 16:22:50 -0400 Subject: amdgpu: move asic id table to a separate file v2: fix an off by one error and leading white spaces v3: use thread safe strtok_r(); initialize len before calling getline(); change printf() to drmMsg(); add initial amdgpu.ids v4: integrate some recent internal changes, including format changes v5: fix line number for empty/commented lines; realloc to save memory; indentation changes v6: remove a line error v7: [Michel Dänzer] * Move amdgpu.ids to new data directory * Remove placeholder entries from amdgpu.ids * Set libdrmdatadir variable in configure.ac instead of Makefile.am [Emil Velikov] * Use isblank() instead of open-coding it [Emil Velikov] * Don't leak asic_id_table memory if realloc fails [Emil Velikov] * Check and bump table_max_size at the beginning of the while loop [Emil Velikov] * Initialize table_max_size to the number of entries in data/amdgpu.ids v8: [Michel Dänzer] * Make sure amdgpu_asic_id.c gets rebuilt when amdgpu.ids changes Reviewed-by: Alex Deucher Reviewed-by: Emil Velikov Signed-off-by: Samuel Li --- Makefile.am | 1 + amdgpu/Makefile.am | 7 ++ amdgpu/Makefile.sources | 2 +- amdgpu/amdgpu_asic_id.c | 219 +++++++++++++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_asic_id.h | 165 ----------------------------------- amdgpu/amdgpu_device.c | 28 ++++-- amdgpu/amdgpu_internal.h | 10 +++ configure.ac | 4 + data/Makefile.am | 23 +++++ data/amdgpu.ids | 159 ++++++++++++++++++++++++++++++++++ 10 files changed, 445 insertions(+), 173 deletions(-) create mode 100644 amdgpu/amdgpu_asic_id.c delete mode 100644 amdgpu/amdgpu_asic_id.h create mode 100644 data/Makefile.am create mode 100644 data/amdgpu.ids diff --git a/Makefile.am b/Makefile.am index dfb8fcdb..7b86214e 100644 --- a/Makefile.am +++ b/Makefile.am @@ -109,6 +109,7 @@ SUBDIRS = \ $(TEGRA_SUBDIR) \ $(VC4_SUBDIR) \ $(ETNAVIV_SUBDIR) \ + data \ tests \ $(MAN_SUBDIR) diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am index cf7bc1ba..66f6f676 100644 --- a/amdgpu/Makefile.am +++ b/amdgpu/Makefile.am @@ -30,12 +30,19 @@ AM_CFLAGS = \ $(PTHREADSTUBS_CFLAGS) \ -I$(top_srcdir)/include/drm +libdrmdatadir = @libdrmdatadir@ +ASIC_ID_TABLE_NUM_ENTRIES := $(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' \ + $(top_srcdir)/data/amdgpu.ids) +AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\" \ + -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(ASIC_ID_TABLE_NUM_ENTRIES) + libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la libdrm_amdgpu_ladir = $(libdir) libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined libdrm_amdgpu_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ libdrm_amdgpu_la_SOURCES = $(LIBDRM_AMDGPU_FILES) +amdgpu_asic_id.lo: $(top_srcdir)/data/amdgpu.ids libdrm_amdgpuincludedir = ${includedir}/libdrm libdrm_amdgpuinclude_HEADERS = $(LIBDRM_AMDGPU_H_FILES) diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources index 487b9e0a..bc3abaa6 100644 --- a/amdgpu/Makefile.sources +++ b/amdgpu/Makefile.sources @@ -1,5 +1,5 @@ LIBDRM_AMDGPU_FILES := \ - amdgpu_asic_id.h \ + amdgpu_asic_id.c \ amdgpu_bo.c \ amdgpu_cs.c \ amdgpu_device.c \ diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c new file mode 100644 index 00000000..3a88896b --- /dev/null +++ b/amdgpu/amdgpu_asic_id.c @@ -0,0 +1,219 @@ +/* + * Copyright © 2017 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include +#include +#include + +#include "xf86drm.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" + +static int parse_one_line(const char *line, struct amdgpu_asic_id *id) +{ + char *buf, *saveptr; + char *s_did; + char *s_rid; + char *s_name; + char *endptr; + int r = 0; + + buf = strdup(line); + if (!buf) + return -ENOMEM; + + /* ignore empty line and commented line */ + if (strlen(line) == 0 || line[0] == '#') { + r = -EAGAIN; + goto out; + } + + /* device id */ + s_did = strtok_r(buf, ",", &saveptr); + if (!s_did) { + r = -EINVAL; + goto out; + } + + id->did = strtol(s_did, &endptr, 16); + if (*endptr) { + r = -EINVAL; + goto out; + } + + /* revision id */ + s_rid = strtok_r(NULL, ",", &saveptr); + if (!s_rid) { + r = -EINVAL; + goto out; + } + + id->rid = strtol(s_rid, &endptr, 16); + if (*endptr) { + r = -EINVAL; + goto out; + } + + /* marketing name */ + s_name = strtok_r(NULL, ",", &saveptr); + if (!s_name) { + r = -EINVAL; + goto out; + } + /* trim leading whitespaces or tabs */ + while (isblank(*s_name)) + s_name++; + if (strlen(s_name) == 0) { + r = -EINVAL; + goto out; + } + + id->marketing_name = strdup(s_name); + if (id->marketing_name == NULL) { + r = -EINVAL; + goto out; + } + +out: + free(buf); + + return r; +} + +int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) +{ + struct amdgpu_asic_id *asic_id_table; + struct amdgpu_asic_id *id; + FILE *fp; + char *line = NULL; + size_t len = 0; + ssize_t n; + int line_num = 1; + size_t table_size = 0; + size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES; + int r = 0; + + fp = fopen(AMDGPU_ASIC_ID_TABLE, "r"); + if (!fp) { + fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE, + strerror(errno)); + return -EINVAL; + } + + asic_id_table = calloc(table_max_size + 1, + sizeof(struct amdgpu_asic_id)); + if (!asic_id_table) { + r = -ENOMEM; + goto close; + } + + /* 1st valid line is file version */ + while ((n = getline(&line, &len, fp)) != -1) { + /* trim trailing newline */ + if (line[n - 1] == '\n') + line[n - 1] = '\0'; + + /* ignore empty line and commented line */ + if (strlen(line) == 0 || line[0] == '#') { + line_num++; + continue; + } + + drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line); + break; + } + + while ((n = getline(&line, &len, fp)) != -1) { + if (table_size > table_max_size) { + /* double table size */ + table_max_size *= 2; + id = realloc(asic_id_table, (table_max_size + 1) * + sizeof(struct amdgpu_asic_id)); + if (!id) { + r = -ENOMEM; + goto free; + } + asic_id_table = id; + } + + id = asic_id_table + table_size; + + /* trim trailing newline */ + if (line[n - 1] == '\n') + line[n - 1] = '\0'; + + r = parse_one_line(line, id); + if (r) { + if (r == -EAGAIN) { + line_num++; + continue; + } + fprintf(stderr, "Invalid format: %s: line %d: %s\n", + AMDGPU_ASIC_ID_TABLE, line_num, line); + goto free; + } + + line_num++; + table_size++; + } + + /* end of table */ + id = asic_id_table + table_size; + memset(id, 0, sizeof(struct amdgpu_asic_id)); + + if (table_size != table_max_size) { + id = realloc(asic_id_table, (table_size + 1) * + sizeof(struct amdgpu_asic_id)); + if (!id) + r = -ENOMEM; + else + asic_id_table = id; + } + +free: + free(line); + + if (r && asic_id_table) { + while (table_size--) { + id = asic_id_table + table_size; + free(id->marketing_name); + } + free(asic_id_table); + asic_id_table = NULL; + } +close: + fclose(fp); + + *p_asic_id_table = asic_id_table; + + return r; +} diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h deleted file mode 100644 index 3e7d736b..00000000 --- a/amdgpu/amdgpu_asic_id.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright © 2016 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __AMDGPU_ASIC_ID_H__ -#define __AMDGPU_ASIC_ID_H__ - -static struct amdgpu_asic_id_table_t { - uint32_t did; - uint32_t rid; - const char *marketing_name; -} const amdgpu_asic_id_table [] = { - {0x6600, 0x0, "AMD Radeon HD 8600/8700M"}, - {0x6600, 0x81, "AMD Radeon R7 M370"}, - {0x6601, 0x0, "AMD Radeon HD 8500M/8700M"}, - {0x6604, 0x0, "AMD Radeon R7 M265 Series"}, - {0x6604, 0x81, "AMD Radeon R7 M350"}, - {0x6605, 0x0, "AMD Radeon R7 M260 Series"}, - {0x6605, 0x81, "AMD Radeon R7 M340"}, - {0x6606, 0x0, "AMD Radeon HD 8790M"}, - {0x6607, 0x0, "AMD Radeon HD8530M"}, - {0x6608, 0x0, "AMD FirePro W2100"}, - {0x6610, 0x0, "AMD Radeon HD 8600 Series"}, - {0x6610, 0x81, "AMD Radeon R7 350"}, - {0x6610, 0x83, "AMD Radeon R5 340"}, - {0x6611, 0x0, "AMD Radeon HD 8500 Series"}, - {0x6613, 0x0, "AMD Radeon HD 8500 series"}, - {0x6617, 0xC7, "AMD Radeon R7 240 Series"}, - {0x6640, 0x0, "AMD Radeon HD 8950"}, - {0x6640, 0x80, "AMD Radeon R9 M380"}, - {0x6646, 0x0, "AMD Radeon R9 M280X"}, - {0x6646, 0x80, "AMD Radeon R9 M470X"}, - {0x6647, 0x0, "AMD Radeon R9 M270X"}, - {0x6647, 0x80, "AMD Radeon R9 M380"}, - {0x6649, 0x0, "AMD FirePro W5100"}, - {0x6658, 0x0, "AMD Radeon R7 200 Series"}, - {0x665C, 0x0, "AMD Radeon HD 7700 Series"}, - {0x665D, 0x0, "AMD Radeon R7 200 Series"}, - {0x665F, 0x81, "AMD Radeon R7 300 Series"}, - {0x6660, 0x0, "AMD Radeon HD 8600M Series"}, - {0x6660, 0x81, "AMD Radeon R5 M335"}, - {0x6660, 0x83, "AMD Radeon R5 M330"}, - {0x6663, 0x0, "AMD Radeon HD 8500M Series"}, - {0x6663, 0x83, "AMD Radeon R5 M320"}, - {0x6664, 0x0, "AMD Radeon R5 M200 Series"}, - {0x6665, 0x0, "AMD Radeon R5 M200 Series"}, - {0x6665, 0x83, "AMD Radeon R5 M320"}, - {0x6667, 0x0, "AMD Radeon R5 M200 Series"}, - {0x666F, 0x0, "AMD Radeon HD 8500M"}, - {0x6780, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"}, - {0x678A, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"}, - {0x6798, 0x0, "AMD Radeon HD 7900 Series"}, - {0x679A, 0x0, "AMD Radeon HD 7900 Series"}, - {0x679B, 0x0, "AMD Radeon HD 7900 Series"}, - {0x679E, 0x0, "AMD Radeon HD 7800 Series"}, - {0x67A0, 0x0, "HAWAII XTGL (67A0)"}, - {0x67A1, 0x0, "HAWAII GL40 (67A1)"}, - {0x67B0, 0x0, "AMD Radeon R9 200 Series"}, - {0x67B0, 0x80, "AMD Radeon R9 390 Series"}, - {0x67B1, 0x0, "AMD Radeon R9 200 Series"}, - {0x67B1, 0x80, "AMD Radeon R9 390 Series"}, - {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, - {0x67DF, 0xC4, "AMD Radeon RX 480 Graphics"}, - {0x67DF, 0xC5, "AMD Radeon RX 470 Graphics"}, - {0x67DF, 0xC7, "AMD Radeon RX 480 Graphics"}, - {0x67DF, 0xCF, "AMD Radeon RX 470 Graphics"}, - {0x67C4, 0x00, "AMD Radeon Pro WX 7100 Graphics"}, - {0x67C7, 0x00, "AMD Radeon Pro WX 5100 Graphics"}, - {0x67C0, 0x00, "AMD Radeon Pro WX 7100 Graphics"}, - {0x67E0, 0x00, "AMD Radeon Pro WX Series Graphics"}, - {0x67E3, 0x00, "AMD Radeon Pro WX 4100 Graphics"}, - {0x67E8, 0x00, "AMD Radeon Pro WX Series Graphics"}, - {0x67E8, 0x01, "AMD Radeon Pro WX Series Graphics"}, - {0x67E8, 0x80, "AMD Radeon E9260 Graphics"}, - {0x67EB, 0x00, "AMD Radeon Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon RX Graphics"}, - {0x67EF, 0xC1, "AMD Radeon RX 460 Graphics"}, - {0x67EF, 0xC5, "AMD Radeon RX 460 Graphics"}, - {0x67EF, 0xC7, "AMD Radeon RX Graphics"}, - {0x67EF, 0xCF, "AMD Radeon RX 460 Graphics"}, - {0x67EF, 0xEF, "AMD Radeon RX Graphics"}, - {0x67FF, 0xC0, "AMD Radeon RX Graphics"}, - {0x67FF, 0xC1, "AMD Radeon RX Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, - {0x6809, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, - {0x6810, 0x0, "AMD Radeon(TM) HD 8800 Series"}, - {0x6810, 0x81, "AMD Radeon R7 370 Series"}, - {0x6811, 0x0, "AMD Radeon(TM) HD8800 Series"}, - {0x6811, 0x81, "AMD Radeon R7 300 Series"}, - {0x6818, 0x0, "AMD Radeon HD 7800 Series"}, - {0x6819, 0x0, "AMD Radeon HD 7800 Series"}, - {0x6820, 0x0, "AMD Radeon HD 8800M Series"}, - {0x6820, 0x81, "AMD Radeon R9 M375"}, - {0x6820, 0x83, "AMD Radeon R9 M375X"}, - {0x6821, 0x0, "AMD Radeon HD 8800M Series"}, - {0x6821, 0x87, "AMD Radeon R7 M380"}, - {0x6821, 0x83, "AMD Radeon R9 M370X"}, - {0x6822, 0x0, "AMD Radeon E8860"}, - {0x6823, 0x0, "AMD Radeon HD 8800M Series"}, - {0x6825, 0x0, "AMD Radeon HD 7800M Series"}, - {0x6827, 0x0, "AMD Radeon HD 7800M Series"}, - {0x6828, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, - {0x682B, 0x0, "AMD Radeon HD 8800M Series"}, - {0x682B, 0x87, "AMD Radeon R9 M360"}, - {0x682C, 0x0, "AMD FirePro W4100"}, - {0x682D, 0x0, "AMD Radeon HD 7700M Series"}, - {0x682F, 0x0, "AMD Radeon HD 7700M Series"}, - {0x6835, 0x0, "AMD Radeon R7 Series / HD 9000 Series"}, - {0x6837, 0x0, "AMD Radeon HD7700 Series"}, - {0x683D, 0x0, "AMD Radeon HD 7700 Series"}, - {0x683F, 0x0, "AMD Radeon HD 7700 Series"}, - {0x6900, 0x0, "AMD Radeon R7 M260"}, - {0x6900, 0x81, "AMD Radeon R7 M360"}, - {0x6900, 0x83, "AMD Radeon R7 M340"}, - {0x6901, 0x0, "AMD Radeon R5 M255"}, - {0x6907, 0x0, "AMD Radeon R5 M255"}, - {0x6907, 0x87, "AMD Radeon R5 M315"}, - {0x6920, 0x0, "AMD Radeon R9 M395X"}, - {0x6920, 0x1, "AMD Radeon R9 M390X"}, - {0x6921, 0x0, "AMD Radeon R9 M295X"}, - {0x6929, 0x0, "AMD FirePro S7150"}, - {0x692B, 0x0, "AMD FirePro W7100"}, - {0x6938, 0x0, "AMD Radeon R9 200 Series"}, - {0x6938, 0xF0, "AMD Radeon R9 200 Series"}, - {0x6938, 0xF1, "AMD Radeon R9 380 Series"}, - {0x6939, 0xF0, "AMD Radeon R9 200 Series"}, - {0x6939, 0x0, "AMD Radeon R9 200 Series"}, - {0x6939, 0xF1, "AMD Radeon R9 380 Series"}, - {0x7300, 0xC8, "AMD Radeon R9 Fury Series"}, - {0x7300, 0xCB, "AMD Radeon R9 Fury Series"}, - {0x7300, 0xCA, "AMD Radeon R9 Fury Series"}, - {0x9874, 0xC4, "AMD Radeon R7 Graphics"}, - {0x9874, 0xC5, "AMD Radeon R6 Graphics"}, - {0x9874, 0xC6, "AMD Radeon R6 Graphics"}, - {0x9874, 0xC7, "AMD Radeon R5 Graphics"}, - {0x9874, 0x81, "AMD Radeon R6 Graphics"}, - {0x9874, 0x87, "AMD Radeon R5 Graphics"}, - {0x9874, 0x85, "AMD Radeon R6 Graphics"}, - {0x9874, 0x84, "AMD Radeon R7 Graphics"}, - - {0x0000, 0x0, "\0"}, -}; -#endif diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index f473d2da..9a238d97 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -44,7 +44,6 @@ #include "amdgpu_internal.h" #include "util_hash_table.h" #include "util_math.h" -#include "amdgpu_asic_id.h" #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) #define UINT_TO_PTR(x) ((void *)((intptr_t)(x))) @@ -131,6 +130,7 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { + const struct amdgpu_asic_id *id; amdgpu_vamgr_deinit(&dev->vamgr_32); amdgpu_vamgr_deinit(&dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); @@ -140,6 +140,12 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev) close(dev->fd); if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd)) close(dev->flink_fd); + if (dev->asic_ids) { + for (id = dev->asic_ids; id->did; id++) + free(id->marketing_name); + + free(dev->asic_ids); + } free(dev); } @@ -267,6 +273,12 @@ int amdgpu_device_initialize(int fd, amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); + r = amdgpu_parse_asic_ids(&dev->asic_ids); + if (r) { + fprintf(stderr, "%s: Cannot parse ASIC IDs, 0x%x.", + __func__, r); + } + *major_version = dev->major_version; *minor_version = dev->minor_version; *device_handle = dev; @@ -297,13 +309,15 @@ int amdgpu_device_deinitialize(amdgpu_device_handle dev) const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) { - const struct amdgpu_asic_id_table_t *t = amdgpu_asic_id_table; + const struct amdgpu_asic_id *id; + + if (!dev->asic_ids) + return NULL; - while (t->did) { - if ((t->did == dev->info.asic_id) && - (t->rid == dev->info.pci_rev_id)) - return t->marketing_name; - t++; + for (id = dev->asic_ids; id->did; id++) { + if ((id->did == dev->info.asic_id) && + (id->rid == dev->info.pci_rev_id)) + return id->marketing_name; } return NULL; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index cf119a53..e68246bf 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -69,6 +69,12 @@ struct amdgpu_va { struct amdgpu_bo_va_mgr *vamgr; }; +struct amdgpu_asic_id { + uint32_t did; + uint32_t rid; + char *marketing_name; +}; + struct amdgpu_device { atomic_t refcount; int fd; @@ -76,6 +82,8 @@ struct amdgpu_device { unsigned major_version; unsigned minor_version; + /** Lookup table of asic device id, revision id and marketing name */ + struct amdgpu_asic_id *asic_ids; /** List of buffer handles. Protected by bo_table_mutex. */ struct util_hash_table *bo_handles; /** List of buffer GEM flink names. Protected by bo_table_mutex. */ @@ -149,6 +157,8 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); +drm_private int amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids); + drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); diff --git a/configure.ac b/configure.ac index 1cfb8c27..aa9529cd 100644 --- a/configure.ac +++ b/configure.ac @@ -84,6 +84,9 @@ fi pkgconfigdir=${libdir}/pkgconfig AC_SUBST(pkgconfigdir) +libdrmdatadir=${datadir}/libdrm +AC_SUBST(libdrmdatadir) + AC_ARG_ENABLE([udev], [AS_HELP_STRING([--enable-udev], [Enable support for using udev instead of mknod (default: disabled)])], @@ -527,6 +530,7 @@ fi AC_SUBST(WARN_CFLAGS) AC_CONFIG_FILES([ Makefile + data/Makefile libkms/Makefile libkms/libkms.pc intel/Makefile diff --git a/data/Makefile.am b/data/Makefile.am new file mode 100644 index 00000000..eba915dd --- /dev/null +++ b/data/Makefile.am @@ -0,0 +1,23 @@ +# Copyright © 2017 Advanced Micro Devices, Inc. +# All Rights Reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# on the rights to use, copy, modify, merge, publish, distribute, sub +# license, and/or sell copies of the Software, and to permit persons to whom +# the Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +libdrmdatadir = @libdrmdatadir@ +dist_libdrmdata_DATA = amdgpu.ids diff --git a/data/amdgpu.ids b/data/amdgpu.ids new file mode 100644 index 00000000..0b98c3c3 --- /dev/null +++ b/data/amdgpu.ids @@ -0,0 +1,159 @@ +# List of AMDGPU IDs +# +# Syntax: +# device_id, revision_id, product_name <-- single tab after comma + +1.0.0 +6600, 0, AMD Radeon HD 8600/8700M +6600, 81, AMD Radeon (TM) R7 M370 +6601, 0, AMD Radeon (TM) HD 8500M/8700M +6604, 0, AMD Radeon R7 M265 Series +6604, 81, AMD Radeon (TM) R7 M350 +6605, 0, AMD Radeon R7 M260 Series +6605, 81, AMD Radeon (TM) R7 M340 +6606, 0, AMD Radeon HD 8790M +6607, 0, AMD Radeon (TM) HD8530M +6608, 0, AMD FirePro W2100 +6610, 0, AMD Radeon HD 8600 Series +6610, 81, AMD Radeon (TM) R7 350 +6610, 83, AMD Radeon (TM) R5 340 +6611, 0, AMD Radeon HD 8500 Series +6613, 0, AMD Radeon HD 8500 series +6617, C7, AMD Radeon R7 240 Series +6640, 0, AMD Radeon HD 8950 +6640, 80, AMD Radeon (TM) R9 M380 +6646, 0, AMD Radeon R9 M280X +6646, 80, AMD Radeon (TM) R9 M470X +6647, 0, AMD Radeon R9 M270X +6647, 80, AMD Radeon (TM) R9 M380 +6649, 0, AMD FirePro W5100 +6658, 0, AMD Radeon R7 200 Series +665C, 0, AMD Radeon HD 7700 Series +665D, 0, AMD Radeon R7 200 Series +665F, 81, AMD Radeon (TM) R7 300 Series +6660, 0, AMD Radeon HD 8600M Series +6660, 81, AMD Radeon (TM) R5 M335 +6660, 83, AMD Radeon (TM) R5 M330 +6663, 0, AMD Radeon HD 8500M Series +6663, 83, AMD Radeon (TM) R5 M320 +6664, 0, AMD Radeon R5 M200 Series +6665, 0, AMD Radeon R5 M200 Series +6665, 83, AMD Radeon (TM) R5 M320 +6667, 0, AMD Radeon R5 M200 Series +666F, 0, AMD Radeon HD 8500M +6780, 0, ATI FirePro V (FireGL V) Graphics Adapter +678A, 0, ATI FirePro V (FireGL V) Graphics Adapter +6798, 0, AMD Radeon HD 7900 Series +679A, 0, AMD Radeon HD 7900 Series +679B, 0, AMD Radeon HD 7900 Series +679E, 0, AMD Radeon HD 7800 Series +67A0, 0, AMD Radeon FirePro W9100 +67A1, 0, AMD Radeon FirePro W8100 +67B0, 0, AMD Radeon R9 200 Series +67B0, 80, AMD Radeon (TM) R9 390 Series +67B1, 0, AMD Radeon R9 200 Series +67B1, 80, AMD Radeon (TM) R9 390 Series +67B9, 0, AMD Radeon R9 200 Series +67DF, C1, Radeon RX 580 Series +67DF, C2, Radeon RX 570 Series +67DF, C3, Radeon RX 580 Series +67DF, C4, AMD Radeon (TM) RX 480 Graphics +67DF, C5, AMD Radeon (TM) RX 470 Graphics +67DF, C6, Radeon RX 570 Series +67DF, C7, AMD Radeon (TM) RX 480 Graphics +67DF, CF, AMD Radeon (TM) RX 470 Graphics +67DF, E3, Radeon RX Series +67DF, E7, Radeon RX 580 Series +67DF, EF, Radeon RX 570 Series +67C2, 01, AMD Radeon (TM) Pro V7350x2 +67C2, 02, AMD Radeon (TM) Pro V7300X +67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics +67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics +67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics +67D0, 01, AMD Radeon (TM) Pro V7350x2 +67D0, 02, AMD Radeon (TM) Pro V7300X +67E0, 00, AMD Radeon (TM) Pro WX Series +67E3, 00, AMD Radeon (TM) Pro WX 4100 +67E8, 00, AMD Radeon (TM) Pro WX Series +67E8, 01, AMD Radeon (TM) Pro WX Series +67E8, 80, AMD Radeon (TM) E9260 Graphics +67EB, 00, AMD Radeon (TM) Pro V5300X +67EF, C0, AMD Radeon (TM) RX Graphics +67EF, C1, AMD Radeon (TM) RX 460 Graphics +67EF, C3, Radeon RX Series +67EF, C5, AMD Radeon (TM) RX 460 Graphics +67EF, C7, AMD Radeon (TM) RX Graphics +67EF, CF, AMD Radeon (TM) RX 460 Graphics +67EF, E1, Radeon RX Series +67EF, E3, Radeon RX Series +67EF, E7, Radeon RX Series +67EF, EF, AMD Radeon (TM) RX Graphics +67EF, FF, Radeon RX Series +67FF, C0, AMD Radeon (TM) RX Graphics +67FF, C1, AMD Radeon (TM) RX Graphics +67FF, FF, Radeon RX 550 Series +6800, 0, AMD Radeon HD 7970M +6801, 0, AMD Radeon(TM) HD8970M +6808, 0, ATI FirePro V(FireGL V) Graphics Adapter +6809, 0, ATI FirePro V(FireGL V) Graphics Adapter +6810, 0, AMD Radeon(TM) HD 8800 Series +6810, 81, AMD Radeon (TM) R7 370 Series +6811, 0, AMD Radeon(TM) HD8800 Series +6811, 81, AMD Radeon (TM) R7 300 Series +6818, 0, AMD Radeon HD 7800 Series +6819, 0, AMD Radeon HD 7800 Series +6820, 0, AMD Radeon HD 8800M Series +6820, 81, AMD Radeon (TM) R9 M375 +6820, 83, AMD Radeon (TM) R9 M375X +6821, 0, AMD Radeon HD 8800M Series +6821, 87, AMD Radeon (TM) R7 M380 +6821, 83, AMD Radeon R9 (TM) M370X +6822, 0, AMD Radeon E8860 +6823, 0, AMD Radeon HD 8800M Series +6825, 0, AMD Radeon HD 7800M Series +6827, 0, AMD Radeon HD 7800M Series +6828, 0, ATI FirePro V(FireGL V) Graphics Adapter +682B, 0, AMD Radeon HD 8800M Series +682B, 87, AMD Radeon (TM) R9 M360 +682C, 0, AMD FirePro W4100 +682D, 0, AMD Radeon HD 7700M Series +682F, 0, AMD Radeon HD 7700M Series +6835, 0, AMD Radeon R7 Series / HD 9000 Series +6837, 0, AMD Radeon HD7700 Series +683D, 0, AMD Radeon HD 7700 Series +683F, 0, AMD Radeon HD 7700 Series +6900, 0, AMD Radeon R7 M260 +6900, 81, AMD Radeon (TM) R7 M360 +6900, 83, AMD Radeon (TM) R7 M340 +6901, 0, AMD Radeon R5 M255 +6907, 0, AMD Radeon R5 M255 +6907, 87, AMD Radeon (TM) R5 M315 +6920, 0, AMD RADEON R9 M395X +6920, 1, AMD RADEON R9 M390X +6921, 0, AMD Radeon R9 M295X +6929, 0, AMD FirePro S7150 +692B, 0, AMD FirePro W7100 +6938, 0, AMD Radeon R9 200 Series +6938, F0, AMD Radeon R9 200 Series +6938, F1, AMD Radeon (TM) R9 380 Series +6939, F0, AMD Radeon R9 200 Series +6939, 0, AMD Radeon R9 200 Series +6939, F1, AMD Radeon (TM) R9 380 Series +6985, 00, AMD Radeon Pro WX3100 +6995, 00, AMD Radeon Pro WX2100 +699F, C0, Radeon 500 Series +699F, C3, Radeon 500 Series +699F, C7, Radeon RX 550 Series +7300, C1, AMD FirePro (TM) S9300 x2 +7300, C8, AMD Radeon (TM) R9 Fury Series +7300, C9, Radeon (TM) Pro Duo +7300, CB, AMD Radeon (TM) R9 Fury Series +7300, CA, AMD Radeon (TM) R9 Fury Series +9874, C4, AMD Radeon R7 Graphics +9874, C5, AMD Radeon R6 Graphics +9874, C6, AMD Radeon R6 Graphics +9874, C7, AMD Radeon R5 Graphics +9874, 81, AMD Radeon R6 Graphics +9874, 87, AMD Radeon R5 Graphics +9874, 85, AMD Radeon R6 Graphics +9874, 84, AMD Radeon R7 Graphics -- cgit v1.2.3-54-g00ecf From b9549c954e190010a79e6691983b6ae16eac83d5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 21 Jun 2017 10:23:23 -0700 Subject: headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI. Taken from make headers_install of drm-misc-next (34c8ea400ff6383b028f63df2453914163afc07c) Reviewed-by: Daniel Stone --- include/drm/drm_fourcc.h | 23 ++++++++++++++++++++++- include/drm/vc4_drm.h | 22 +++++++++++++++++++--- 2 files changed, 41 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index 55e30104..7586c46f 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -182,6 +182,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 +#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 /* add more to the end as needed */ #define fourcc_mod_code(vendor, val) \ @@ -306,7 +307,6 @@ extern "C" { */ #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) - /* NVIDIA Tegra frame buffer modifiers */ /* @@ -351,6 +351,27 @@ extern "C" { */ #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) +/* + * Broadcom VC4 "T" format + * + * This is the primary layout that the V3D GPU can texture from (it + * can't do linear). The T format has: + * + * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 + * pixels at 32 bit depth. + * + * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually + * 16x16 pixels). + * + * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On + * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows + * they're (TR, BR, BL, TL), where bottom left is start of memory. + * + * - an image made of 4k tiles in rows either left-to-right (even rows of 4k + * tiles) or right-to-left (odd rows of 4k tiles). + */ +#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) + #if defined(__cplusplus) } #endif diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h index 319881d8..6ac4c5c0 100644 --- a/include/drm/vc4_drm.h +++ b/include/drm/vc4_drm.h @@ -21,8 +21,8 @@ * IN THE SOFTWARE. */ -#ifndef _VC4_DRM_H_ -#define _VC4_DRM_H_ +#ifndef _UAPI_VC4_DRM_H_ +#define _UAPI_VC4_DRM_H_ #include "drm.h" @@ -38,6 +38,8 @@ extern "C" { #define DRM_VC4_CREATE_SHADER_BO 0x05 #define DRM_VC4_GET_HANG_STATE 0x06 #define DRM_VC4_GET_PARAM 0x07 +#define DRM_VC4_SET_TILING 0x08 +#define DRM_VC4_GET_TILING 0x09 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) @@ -47,6 +49,8 @@ extern "C" { #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) +#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) +#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) struct drm_vc4_submit_rcl_surface { __u32 hindex; /* Handle index, or ~0 if not present. */ @@ -295,8 +299,20 @@ struct drm_vc4_get_param { __u64 value; }; +struct drm_vc4_get_tiling { + __u32 handle; + __u32 flags; + __u64 modifier; +}; + +struct drm_vc4_set_tiling { + __u32 handle; + __u32 flags; + __u64 modifier; +}; + #if defined(__cplusplus) } #endif -#endif /* _VC4_DRM_H_ */ +#endif /* _UAPI_VC4_DRM_H_ */ -- cgit v1.2.3-54-g00ecf From 92b5b308ca2fec356dd29bb2f27d88a5aff61798 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 27 Jun 2017 12:56:25 +1000 Subject: amdgpu: sync amdgpu_drm with kernel. This syncs the amdgpu_drm header with my drm-next branch as of 6d61e70ccc21606ffb8a0a03bd3aba24f659502b. It brings over the VM and semaphore API changes. Generated using make headers_install. Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2. Reviewed-by: Michel Dänzer Signed-off-by: Dave Airlie --- include/drm/amdgpu_drm.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 8cfe68c5..d9aa4a33 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -51,6 +51,7 @@ extern "C" { #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 #define DRM_AMDGPU_WAIT_FENCES 0x12 +#define DRM_AMDGPU_VM 0x13 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -65,6 +66,7 @@ extern "C" { #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) +#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -190,6 +192,26 @@ union drm_amdgpu_ctx { union drm_amdgpu_ctx_out out; }; +/* vm ioctl */ +#define AMDGPU_VM_OP_RESERVE_VMID 1 +#define AMDGPU_VM_OP_UNRESERVE_VMID 2 + +struct drm_amdgpu_vm_in { + /** AMDGPU_VM_OP_* */ + __u32 op; + __u32 flags; +}; + +struct drm_amdgpu_vm_out { + /** For future use, no flags defined so far */ + __u64 flags; +}; + +union drm_amdgpu_vm { + struct drm_amdgpu_vm_in in; + struct drm_amdgpu_vm_out out; +}; + /* * This is not a reliable API and you should expect it to fail for any * number of reasons and have fallback path that do not use userptr to @@ -295,7 +317,10 @@ union drm_amdgpu_gem_wait_idle { }; struct drm_amdgpu_wait_cs_in { - /** Command submission handle */ + /* Command submission handle + * handle equals 0 means none to wait for + * handle equals ~0ull means wait for the latest sequence number + */ __u64 handle; /** Absolute timeout to wait */ __u64 timeout; @@ -415,6 +440,8 @@ struct drm_amdgpu_gem_va { #define AMDGPU_CHUNK_ID_IB 0x01 #define AMDGPU_CHUNK_ID_FENCE 0x02 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 +#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 +#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 struct drm_amdgpu_cs_chunk { __u32 chunk_id; @@ -482,6 +509,10 @@ struct drm_amdgpu_cs_chunk_fence { __u32 offset; }; +struct drm_amdgpu_cs_chunk_sem { + __u32 handle; +}; + struct drm_amdgpu_cs_chunk_data { union { struct drm_amdgpu_cs_chunk_ib ib_data; @@ -578,6 +609,8 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_SENSOR_VDDNB 0x6 /* Subquery id: Query graphics voltage */ #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 +/* Number of VRAM page faults on CPU access. */ +#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -766,6 +799,25 @@ struct drm_amdgpu_info_device { __u64 cntl_sb_buf_gpu_addr; /* NGG Parameter Cache */ __u64 param_buf_gpu_addr; + __u32 prim_buf_size; + __u32 pos_buf_size; + __u32 cntl_sb_buf_size; + __u32 param_buf_size; + /* wavefront size*/ + __u32 wave_front_size; + /* shader visible vgprs*/ + __u32 num_shader_visible_vgprs; + /* CU per shader array*/ + __u32 num_cu_per_sh; + /* number of tcc blocks*/ + __u32 num_tcc_blocks; + /* gs vgt table depth*/ + __u32 gs_vgt_table_depth; + /* gs primitive buffer depth*/ + __u32 gs_prim_buffer_depth; + /* max gs wavefront per vgt*/ + __u32 max_gs_waves_per_vgt; + __u32 _pad1; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3-54-g00ecf From 3832374dafb8d0b1b69d8856be28352514afab5d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jun 2017 05:27:39 +1000 Subject: drm: update drm.h to latest in drm-next. This syncs the drm.h header with my drm-next branch as of 6d61e70ccc21606ffb8a0a03bd3aba24f659502b. It brings over the semaphore API changes. Generated using make headers_install. Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2. [airlied: I split patch in two, split reviewed by across both] Reviewed-by: Eric Anholt Signed-off-by: Dave Airlie --- include/drm/drm.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/drm/drm.h b/include/drm/drm.h index 1e7a4bc7..bf3674ae 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -642,6 +642,7 @@ struct drm_gem_open { #define DRM_CAP_ADDFB2_MODIFIERS 0x10 #define DRM_CAP_PAGE_FLIP_TARGET 0x11 #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 +#define DRM_CAP_SYNCOBJ 0x13 /** DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { @@ -691,6 +692,26 @@ struct drm_prime_handle { __s32 fd; }; +struct drm_syncobj_create { + __u32 handle; + __u32 flags; +}; + +struct drm_syncobj_destroy { + __u32 handle; + __u32 pad; +}; + +#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) +#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) +struct drm_syncobj_handle { + __u32 handle; + __u32 flags; + + __s32 fd; + __u32 pad; +}; + #if defined(__cplusplus) } #endif @@ -809,6 +830,11 @@ extern "C" { #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) +#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) +#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) +#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) +#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) + /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. -- cgit v1.2.3-54-g00ecf From fc4922793f1871577bb44b1d69ec3801acb23eb6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 17 Jun 2017 11:01:01 +1000 Subject: libdrm: add drm syncobj create/destroy/import/export These ioctls are now in drm next so add the first set of libdrm APIs. Reviewed-by: Eric Anholt Signed-off-by: Dave Airlie --- xf86drm.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ xf86drm.h | 8 +++++++ 2 files changed, 89 insertions(+) diff --git a/xf86drm.c b/xf86drm.c index 728ac78c..2ac3f265 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -4146,3 +4146,84 @@ char *drmGetDeviceNameFromFd2(int fd) return strdup(node); #endif } + +int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle) +{ + struct drm_syncobj_create args; + int ret; + + memclear(args); + args.flags = flags; + args.handle = 0; + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &args); + if (ret) + return ret; + *handle = args.handle; + return 0; +} + +int drmSyncobjDestroy(int fd, uint32_t handle) +{ + struct drm_syncobj_destroy args; + + memclear(args); + args.handle = handle; + return drmIoctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &args); +} + +int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd) +{ + struct drm_syncobj_handle args; + int ret; + + memclear(args); + args.fd = -1; + args.handle = handle; + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args); + if (ret) + return ret; + *obj_fd = args.fd; + return 0; +} + +int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle) +{ + struct drm_syncobj_handle args; + int ret; + + memclear(args); + args.fd = obj_fd; + args.handle = 0; + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, &args); + if (ret) + return ret; + *handle = args.handle; + return 0; +} + +int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd) +{ + struct drm_syncobj_handle args; + + memclear(args); + args.fd = sync_file_fd; + args.handle = handle; + args.flags = DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE; + return drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, &args); +} + +int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd) +{ + struct drm_syncobj_handle args; + int ret; + + memclear(args); + args.fd = -1; + args.handle = handle; + args.flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE; + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args); + if (ret) + return ret; + *sync_file_fd = args.fd; + return 0; +} diff --git a/xf86drm.h b/xf86drm.h index 74f54f17..2855a3ee 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -853,6 +853,14 @@ extern int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_device extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b); +extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle); +extern int drmSyncobjDestroy(int fd, uint32_t handle); +extern int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd); +extern int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle); + +extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd); +extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd); + #if defined(__cplusplus) } #endif -- cgit v1.2.3-54-g00ecf From 0733f376ae93f7580be1641d8ebc644561d438f4 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Wed, 21 Jun 2017 11:17:35 -0700 Subject: intel: PCI Ids for S SKU in CFL Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa Reviewed-by: Clinton Taylor Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 41fc0da0..aeb72ba5 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -221,6 +221,12 @@ #define PCI_CHIP_GLK 0x3184 #define PCI_CHIP_GLK_2X6 0x3185 +#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 +#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 +#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 +#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 +#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 + #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \ @@ -452,10 +458,19 @@ #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ (devid) == PCI_CHIP_GLK_2X6) +#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3) + +#define IS_COFFEELAKE(devid) (IS_CFL_S(devid)) + #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ IS_BROXTON(devid) || \ IS_KABYLAKE(devid) || \ - IS_GEMINILAKE(devid)) + IS_GEMINILAKE(devid) || \ + IS_COFFEELAKE(devid)) #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ -- cgit v1.2.3-54-g00ecf From 2b48faf30e03cdafccffd7d6c6a715c2f969fc31 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Wed, 21 Jun 2017 11:17:36 -0700 Subject: intel: PCI Ids for H SKU in CFL Add the PCI IDs for H SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa Reviewed-by: Clinton Taylor Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index aeb72ba5..fed5a0d8 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -226,6 +226,8 @@ #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 +#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B +#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -464,7 +466,11 @@ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3) -#define IS_COFFEELAKE(devid) (IS_CFL_S(devid)) +#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) + +#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ + IS_CFL_H(devid)) #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ IS_BROXTON(devid) || \ -- cgit v1.2.3-54-g00ecf From 4c98652cb5cd3b0ef3681b1a7b2892c14b7f5c34 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Wed, 21 Jun 2017 11:17:37 -0700 Subject: intel: PCI Ids for U SKU in CFL Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa Reviewed-by: Clinton Taylor Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index fed5a0d8..891b50fc 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -228,6 +228,10 @@ #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -469,8 +473,14 @@ #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4) + #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ - IS_CFL_H(devid)) + IS_CFL_H(devid) || \ + IS_CFL_U(devid)) #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ IS_BROXTON(devid) || \ -- cgit v1.2.3-54-g00ecf From 6b624bf3c394e1883314925c65c7ed1e98f3639f Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Mon, 12 Dec 2016 16:06:02 -0800 Subject: intel: Add Cannonlake PCI IDs for U-skus. Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for SKU not mentioned in spec. v3: Add kernel commit id for reference. Cc: Anusha Srivatsa Cc: Clinton Taylor Signed-off-by: Rodrigo Vivi Reviewed-by: Clinton Taylor --- intel/intel_chipset.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 891b50fc..e6b49d73 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -233,6 +233,11 @@ #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 +#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 +#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A +#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 +#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A + #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \ @@ -496,5 +501,13 @@ IS_GEN8(dev) || \ IS_GEN9(dev)) +#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ + (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ + (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ + (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) + +#define IS_CANNONLAKE(devid) (IS_CNL_U(devid)) + +#define IS_GEN10(devid) (IS_CANNONLAKE(devid)) #endif /* _INTEL_CHIPSET_H */ -- cgit v1.2.3-54-g00ecf From 80201d706712bd87f1bac8b7493bd784acd4a764 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Mon, 12 Dec 2016 16:06:03 -0800 Subject: intel: Add Cannonlake PCI IDs for Y-skus. By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa Cc: Clinton Taylor Signed-off-by: Rodrigo Vivi Reviewed-by: Clinton Taylor --- intel/intel_chipset.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index e6b49d73..37579c64 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -237,6 +237,12 @@ #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A #define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 #define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A +#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 +#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 +#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 +#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 +#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 +#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -501,12 +507,20 @@ IS_GEN8(dev) || \ IS_GEN9(dev)) +#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) + #define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid)) +#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ + IS_CNL_Y(devid)) #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) -- cgit v1.2.3-54-g00ecf From 5c490bd6854a5b265aaa62ef62926c3ac97092c7 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Wed, 24 Aug 2016 14:51:43 -0700 Subject: intel/gen10: Add missed gen10 stuff This got lost on rebase, I believe Signed-off-by: Ben Widawsky Signed-off-by: Rodrigo Vivi --- intel/intel_bufmgr_gem.c | 2 ++ intel/intel_decode.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 45a26da1..71f140f5 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3662,6 +3662,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->gen = 8; else if (IS_GEN9(bufmgr_gem->pci_device)) bufmgr_gem->gen = 9; + else if (IS_GEN10(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 10; else { free(bufmgr_gem); bufmgr_gem = NULL; diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 2721ffd7..3a81500f 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3827,7 +3827,9 @@ drm_intel_decode_context_alloc(uint32_t devid) ctx->devid = devid; ctx->out = stdout; - if (IS_GEN9(devid)) + if (IS_GEN10(devid)) + ctx->gen = 10; + else if (IS_GEN9(devid)) ctx->gen = 9; else if (IS_GEN8(devid)) ctx->gen = 8; -- cgit v1.2.3-54-g00ecf From 3095cc8eaba1aa87ad38c04ae2b1eabe30f7e16c Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Thu, 27 Apr 2017 17:11:09 -0300 Subject: intel: add GEN10 to IS_9XX. As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 37579c64..770d21f0 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -505,7 +505,8 @@ IS_GEN6(dev) || \ IS_GEN7(dev) || \ IS_GEN8(dev) || \ - IS_GEN9(dev)) + IS_GEN9(dev) || \ + IS_GEN10(dev)) #define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ -- cgit v1.2.3-54-g00ecf From 68da7812fc8f859afa7f202f832c72a35c8d4a1d Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 30 Jun 2017 14:24:55 -0700 Subject: intel/intel_chipset: Move IS_9XX below IS_GEN10. No functional change. Just organizing the code so it gets clear for future platforms. Paulo deserves credits becuase he was the one that just noticed this IS_9XX was in the wrong position after CNL patches got introduced. Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 770d21f0..3ff59ada 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -499,15 +499,6 @@ IS_GEMINILAKE(devid) || \ IS_COFFEELAKE(devid)) -#define IS_9XX(dev) (IS_GEN3(dev) || \ - IS_GEN4(dev) || \ - IS_GEN5(dev) || \ - IS_GEN6(dev) || \ - IS_GEN7(dev) || \ - IS_GEN8(dev) || \ - IS_GEN9(dev) || \ - IS_GEN10(dev)) - #define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ @@ -525,4 +516,13 @@ #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) +#define IS_9XX(dev) (IS_GEN3(dev) || \ + IS_GEN4(dev) || \ + IS_GEN5(dev) || \ + IS_GEN6(dev) || \ + IS_GEN7(dev) || \ + IS_GEN8(dev) || \ + IS_GEN9(dev) || \ + IS_GEN10(dev)) + #endif /* _INTEL_CHIPSET_H */ -- cgit v1.2.3-54-g00ecf From 2393acd14487db0b7bedcf5af7b3710066809cbc Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Fri, 9 Jun 2017 12:27:34 +0200 Subject: etnaviv: submit full struct drm_etnaviv_gem_submit It is safe to submit the full struct even on older kernels as such kernels do not process the full struct. Without this change it becomes quite challenging to extned the submit struct. Freedreno has no special treatment too. See git commits - freedreno: sync uapi header - freedreno: add fence fd support Signed-off-by: Christian Gmeiner Reviewed-by: Philipp Zabel Tested-by: Philipp Zabel --- etnaviv/etnaviv_cmd_stream.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c index 3c7b0ed6..8d0e8135 100644 --- a/etnaviv/etnaviv_cmd_stream.c +++ b/etnaviv/etnaviv_cmd_stream.c @@ -203,14 +203,8 @@ static void flush(struct etna_cmd_stream *stream, int in_fence_fd, if (out_fence_fd) req.flags |= ETNA_SUBMIT_FENCE_FD_OUT; - /* - * Pass the complete submit structure only if flags are set. Otherwise, - * only pass the fields up to, but not including the flags field for - * backwards compatiblity with older kernels. - */ ret = drmCommandWriteRead(gpu->dev->fd, DRM_ETNAVIV_GEM_SUBMIT, - &req, req.flags ? sizeof(req) : - offsetof(struct drm_etnaviv_gem_submit, flags)); + &req, sizeof(req)); if (ret) ERROR_MSG("submit failed: %d (%s)", ret, strerror(errno)); -- cgit v1.2.3-54-g00ecf From ac214017904b31bc5f80f802d748d5f4f3149d22 Mon Sep 17 00:00:00 2001 From: coypu Date: Fri, 30 Jun 2017 03:56:55 +0000 Subject: Remove redundant memclear drmMalloc will zero out the memory for us Reviewed-by: Eric Engestrom --- xf86drm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/xf86drm.c b/xf86drm.c index 2ac3f265..879f85b6 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -866,8 +866,6 @@ drmVersionPtr drmGetVersion(int fd) drmVersionPtr retval; drm_version_t *version = drmMalloc(sizeof(*version)); - memclear(*version); - if (drmIoctl(fd, DRM_IOCTL_VERSION, version)) { drmFreeKernelVersion(version); return NULL; -- cgit v1.2.3-54-g00ecf From 69532d0188ffa12454bc26bb1c30c52555a984e0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 16 Jul 2017 20:18:40 +0100 Subject: drm/amdgpu: add syncobj create/destroy/import/export apis These are just wrappers using the amdgpu device handle. Acked-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Dave Airlie --- amdgpu/amdgpu.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++- amdgpu/amdgpu_cs.c | 38 +++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 1901fa8c..183f974c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1328,8 +1328,61 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); */ const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); +/** + * Create kernel sync object + * + * \param dev - \c [in] device handle + * \param syncobj - \c [out] sync object handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, + uint32_t *syncobj); +/** + * Destroy kernel sync object + * + * \param dev - \c [in] device handle + * \param syncobj - \c [in] sync object handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, + uint32_t syncobj); + +/** + * Export kernel sync object to shareable fd. + * + * \param dev - \c [in] device handle + * \param syncobj - \c [in] sync object handle + * \param shared_fd - \c [out] shared file descriptor. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, + uint32_t syncobj, + int *shared_fd); +/** + * Import kernel sync object from shareable fd. + * + * \param dev - \c [in] device handle + * \param shared_fd - \c [in] shared file descriptor. + * \param syncobj - \c [out] sync object handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, + int shared_fd, + uint32_t *syncobj); + #ifdef __cplusplus } #endif - #endif /* #ifdef _AMDGPU_H_ */ diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 868eb7b0..722fd75b 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -596,3 +596,41 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) { return amdgpu_cs_unreference_sem(sem); } + +int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, + uint32_t *handle) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjCreate(dev->fd, 0, handle); +} + +int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, + uint32_t handle) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjDestroy(dev->fd, handle); +} + +int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, + uint32_t handle, + int *shared_fd) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjHandleToFD(dev->fd, handle, shared_fd); +} + +int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, + int shared_fd, + uint32_t *handle) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjFDToHandle(dev->fd, shared_fd, handle); +} -- cgit v1.2.3-54-g00ecf From 22790a65d4a12c43ddbb266cb5985a9ab6b29662 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 18 Jul 2017 01:31:27 +0100 Subject: drm/amdgpu: add new low overhead command submission API. (v2) This just sends chunks to the kernel API for a single command stream. This should provide a more future proof and extensible API for command submission. v2: use amdgpu_bo_list_handle, add two helper functions to access bo and context internals. Reviewed-by: Christian König Signed-off-by: Dave Airlie --- amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++ amdgpu/amdgpu_cs.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 183f974c..238b1aaa 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1382,6 +1382,36 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, int shared_fd, uint32_t *syncobj); +/** + * Submit raw command submission to kernel + * + * \param dev - \c [in] device handle + * \param context - \c [in] context handle for context id + * \param bo_list_handle - \c [in] request bo list handle (0 for none) + * \param num_chunks - \c [in] number of CS chunks to submit + * \param chunks - \c [in] array of CS chunks + * \param seq_no - \c [out] output sequence number for submission. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + */ +struct drm_amdgpu_cs_chunk; +struct drm_amdgpu_cs_chunk_dep; +struct drm_amdgpu_cs_chunk_data; + +int amdgpu_cs_submit_raw(amdgpu_device_handle dev, + amdgpu_context_handle context, + amdgpu_bo_list_handle bo_list_handle, + int num_chunks, + struct drm_amdgpu_cs_chunk *chunks, + uint64_t *seq_no); + +void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, + struct drm_amdgpu_cs_chunk_dep *dep); +void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, + struct drm_amdgpu_cs_chunk_data *data); + #ifdef __cplusplus } #endif diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 722fd75b..dfba8754 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -634,3 +634,50 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, return drmSyncobjFDToHandle(dev->fd, shared_fd, handle); } + +int amdgpu_cs_submit_raw(amdgpu_device_handle dev, + amdgpu_context_handle context, + amdgpu_bo_list_handle bo_list_handle, + int num_chunks, + struct drm_amdgpu_cs_chunk *chunks, + uint64_t *seq_no) +{ + union drm_amdgpu_cs cs = {0}; + uint64_t *chunk_array; + int i, r; + if (num_chunks == 0) + return -EINVAL; + + chunk_array = alloca(sizeof(uint64_t) * num_chunks); + for (i = 0; i < num_chunks; i++) + chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; + cs.in.chunks = (uint64_t)(uintptr_t)chunk_array; + cs.in.ctx_id = context->id; + cs.in.bo_list_handle = bo_list_handle ? bo_list_handle->handle : 0; + cs.in.num_chunks = num_chunks; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS, + &cs, sizeof(cs)); + if (r) + return r; + + if (seq_no) + *seq_no = cs.out.handle; + return 0; +} + +void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, + struct drm_amdgpu_cs_chunk_data *data) +{ + data->fence_data.handle = fence_info->handle->handle; + data->fence_data.offset = fence_info->offset * sizeof(uint64_t); +} + +void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, + struct drm_amdgpu_cs_chunk_dep *dep) +{ + dep->ip_type = fence->ip_type; + dep->ip_instance = fence->ip_instance; + dep->ring = fence->ring; + dep->ctx_id = fence->context->id; + dep->handle = fence->fence; +} -- cgit v1.2.3-54-g00ecf From e12af382b5c59f531fddd6e5541f59474ba29ef1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 19 Jul 2017 00:40:38 +0100 Subject: amdgpu: add new symbols to tests. --- amdgpu/amdgpu-symbol-check | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 81ef9b4e..c5b85b52 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -25,14 +25,21 @@ amdgpu_bo_va_op amdgpu_bo_va_op_raw amdgpu_bo_wait_for_idle amdgpu_create_bo_from_user_mem +amdgpu_cs_chunk_fence_info_to_data +amdgpu_cs_chunk_fence_to_dep amdgpu_cs_create_semaphore +amdgpu_cs_create_syncobj amdgpu_cs_ctx_create amdgpu_cs_ctx_free amdgpu_cs_destroy_semaphore +amdgpu_cs_destroy_syncobj +amdgpu_cs_export_syncobj +amdgpu_cs_import_syncobj amdgpu_cs_query_fence_status amdgpu_cs_query_reset_state amdgpu_cs_signal_semaphore amdgpu_cs_submit +amdgpu_cs_submit_raw amdgpu_cs_wait_fences amdgpu_cs_wait_semaphore amdgpu_device_deinitialize -- cgit v1.2.3-54-g00ecf From 23e234a3503f51b9d9c585123d33b936f522808d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 19 Jul 2017 10:49:34 +0200 Subject: configure.ac: bump version for release Signed-off-by: Lucas Stach --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index aa9529cd..5a7b1f8a 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.81], + [2.4.82], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 5226b52773e0a9972cd1e0dade55cb9ae869941c Mon Sep 17 00:00:00 2001 From: Gurchetan Singh Date: Wed, 19 Jul 2017 08:37:06 -0700 Subject: xf86drm: continue after drmProcessPlatformDevice failure On ChromeOS devices, readdir() processes the directory in the following order: -NAME- -TYPE- . n/a .. n/a vgem n/a card1 DRM_BUS_PLATFORM renderD129 DRM_BUS_PLATFORM card0 DRM_BUS_PCI renderD128 DRM_BUS_PCI controlD64 DRM_BUS_PCI In drmGetDevices2, after drmProcessPlatformDevice fails for /dev/dri/card1, we don't process the remaining directory entries. As such, Vulkan fails to initialize since Mesa uses drmGetDevices2. To fix this, continue if drmProcessPlatformDevice fails. Fixes: 7b1f37f474d ("xf86drm: Add platform and host1x bus support") Reviewed-by: Emil Velikov [Emil: correct the host1x platforms as well] Signed-off-by: Emil Velikov --- xf86drm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xf86drm.c b/xf86drm.c index 879f85b6..f306c9b7 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -3997,7 +3997,7 @@ int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices) ret = drmProcessPlatformDevice(&device, node, node_type, maj, min, devices != NULL, flags); if (ret) - goto free_devices; + continue; break; @@ -4005,7 +4005,7 @@ int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices) ret = drmProcessHost1xDevice(&device, node, node_type, maj, min, devices != NULL, flags); if (ret) - goto free_devices; + continue; break; -- cgit v1.2.3-54-g00ecf From 3876bc246a07070a6043159cd7623d4def9bbd4c Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Thu, 20 Jul 2017 12:25:27 +0100 Subject: xf86drm: continue with next device if drmProcessUsbDevice fails Analogous to previous commit (and the rest of the codebase), simply discard the device if we cannot parse it. Fixes: f8484ccbd12 ("xf86drm: Add USB support") Signed-off-by: Emil Velikov --- xf86drm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xf86drm.c b/xf86drm.c index f306c9b7..6ea01129 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -3989,7 +3989,7 @@ int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices) ret = drmProcessUsbDevice(&device, node, node_type, maj, min, devices != NULL, flags); if (ret) - goto free_devices; + continue; break; -- cgit v1.2.3-54-g00ecf From 053ad3848786bf40a8131a2069d0fae259222c4f Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Sun, 30 Jul 2017 21:34:16 +0100 Subject: radeon: add fallthrough annotation GCC 7 started warning when a switch case has neither a `break` nor a "fallthrough" comment. Let's be explicit that we meant to fall through here. Signed-off-by: Eric Engestrom Reviewed-by: Michel Dänzer --- radeon/radeon_surface.c | 1 + 1 file changed, 1 insertion(+) diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 965be24c..04df77d6 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -2503,6 +2503,7 @@ static int radeon_surface_sanity(struct radeon_surface_manager *surf_man, if (surf->npix_y > 1) { return -EINVAL; } + /* fallthrough */ case RADEON_SURF_TYPE_2D: if (surf->npix_z > 1) { return -EINVAL; -- cgit v1.2.3-54-g00ecf From 0167e6836e91947418fec36c3b4b396760d0f345 Mon Sep 17 00:00:00 2001 From: Jan Vesely Date: Fri, 28 Jul 2017 01:46:45 -0400 Subject: amdgpu: Add FX-9800P Bristol Ridge iGPU id Signed-off-by: Jan Vesely Reviewed-by: Michel Dänzer --- data/amdgpu.ids | 1 + 1 file changed, 1 insertion(+) diff --git a/data/amdgpu.ids b/data/amdgpu.ids index 0b98c3c3..f6c65dd9 100644 --- a/data/amdgpu.ids +++ b/data/amdgpu.ids @@ -153,6 +153,7 @@ 9874, C5, AMD Radeon R6 Graphics 9874, C6, AMD Radeon R6 Graphics 9874, C7, AMD Radeon R5 Graphics +9874, C8, AMD Radeon R7 Graphics 9874, 81, AMD Radeon R6 Graphics 9874, 87, AMD Radeon R5 Graphics 9874, 85, AMD Radeon R6 Graphics -- cgit v1.2.3-54-g00ecf From 517df5f5134af207c90ac92185dc8c7ed5a86f92 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 27 May 2017 13:40:45 +0800 Subject: tests/amdgpu: bypass UVD CS tests on raven raven doesn't support UVD decode Signed-off-by: Hawking Zhang Reviewed-by: Xiaojie Yuan Signed-off-by: Alex Deucher --- tests/amdgpu/cs_tests.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 081ec9c2..df55c70d 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -90,6 +90,11 @@ int suite_cs_tests_init(void) chip_rev = device_handle->info.chip_rev; chip_id = device_handle->info.chip_external_rev; + if (family_id >= AMDGPU_FAMILY_RV) { + printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n"); + return CUE_SUCCESS; + } + r = amdgpu_cs_ctx_create(device_handle, &context_handle); if (r) return CUE_SINIT_FAILED; @@ -114,6 +119,9 @@ int suite_cs_tests_clean(void) { int r; + if (family_id >= AMDGPU_FAMILY_RV) + return CUE_SUCCESS; + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, ib_mc_address, IB_SIZE); if (r) @@ -192,6 +200,9 @@ static void amdgpu_cs_uvd_create(void) void *msg; int i, r; + if (family_id >= AMDGPU_FAMILY_RV) + return; + req.alloc_size = 4*1024; req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; @@ -263,6 +274,9 @@ static void amdgpu_cs_uvd_decode(void) uint8_t *ptr; int i, r; + if (family_id >= AMDGPU_FAMILY_RV) + return; + req.alloc_size = 4*1024; /* msg */ req.alloc_size += 4*1024; /* fb */ if (family_id >= AMDGPU_FAMILY_VI) @@ -402,6 +416,9 @@ static void amdgpu_cs_uvd_destroy(void) void *msg; int i, r; + if (family_id >= AMDGPU_FAMILY_RV) + return; + req.alloc_size = 4*1024; req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; -- cgit v1.2.3-54-g00ecf From 4d0e05eb2a611eef83609678de27f45a9a3ad806 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 27 May 2017 14:49:19 +0800 Subject: tests/amdgpu: bypass VCE tests on raven raven doesn't support VCE Signed-off-by: Hawking Zhang Reviewed-by: Xiaojie Yuan Signed-off-by: Alex Deucher --- tests/amdgpu/vce_tests.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c index b03807b2..8d61a3b1 100644 --- a/tests/amdgpu/vce_tests.c +++ b/tests/amdgpu/vce_tests.c @@ -106,6 +106,11 @@ int suite_vce_tests_init(void) family_id = device_handle->info.family_id; vce_harvest_config = device_handle->info.vce_harvest_config; + if (family_id >= AMDGPU_FAMILY_RV) { + printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); + return CUE_SUCCESS; + } + r = amdgpu_cs_ctx_create(device_handle, &context_handle); if (r) return CUE_SINIT_FAILED; @@ -126,6 +131,9 @@ int suite_vce_tests_clean(void) { int r; + if (family_id >= AMDGPU_FAMILY_RV) + return CUE_SUCCESS; + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, ib_mc_address, IB_SIZE); if (r) @@ -237,6 +245,9 @@ static void amdgpu_cs_vce_create(void) unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; int len, r; + if (family_id >= AMDGPU_FAMILY_RV) + return; + enc.width = vce_create[6]; enc.height = vce_create[7]; @@ -430,6 +441,9 @@ static void amdgpu_cs_vce_encode(void) unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; int i, r; + if (family_id >= AMDGPU_FAMILY_RV) + return; + vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; cpb_size = vbuf_size * 10; num_resources = 0; @@ -508,6 +522,9 @@ static void amdgpu_cs_vce_destroy(void) { int len, r; + if (family_id >= AMDGPU_FAMILY_RV) + return; + num_resources = 0; alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); resources[num_resources++] = enc.fb[0].handle; -- cgit v1.2.3-54-g00ecf From e2b6785c5abecceee8f3c1830ee1bb22e6d0ef51 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 19 Jul 2017 10:52:33 +0800 Subject: test/amdgpu: fix test failure for SI Signed-off-by: Flora Cui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- tests/amdgpu/basic_tests.c | 270 ++++++++++++++++++++++++++++++--------------- tests/amdgpu/cs_tests.c | 41 +++---- tests/amdgpu/vce_tests.c | 41 +++---- 3 files changed, 228 insertions(+), 124 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 8d5844b6..80d15e77 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -40,6 +40,7 @@ static amdgpu_device_handle device_handle; static uint32_t major_version; static uint32_t minor_version; +static uint32_t family_id; static void amdgpu_query_info_test(void); static void amdgpu_memory_alloc(void); @@ -199,22 +200,56 @@ CU_TestInfo basic_tests[] = { # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +#define SDMA_PACKET_SI(op, b, t, s, cnt) ((((op) & 0xF) << 28) | \ + (((b) & 0x1) << 26) | \ + (((t) & 0x1) << 23) | \ + (((s) & 0x1) << 22) | \ + (((cnt) & 0xFFFFF) << 0)) +#define SDMA_OPCODE_COPY_SI 3 +#define SDMA_OPCODE_CONSTANT_FILL_SI 13 +#define SDMA_NOP_SI 0xf +#define GFX_COMPUTE_NOP_SI 0x80000000 +#define PACKET3_DMA_DATA_SI 0x41 +# define PACKET3_DMA_DATA_SI_ENGINE(x) ((x) << 27) + /* 0 - ME + * 1 - PFP + */ +# define PACKET3_DMA_DATA_SI_DST_SEL(x) ((x) << 20) + /* 0 - DST_ADDR using DAS + * 1 - GDS + * 3 - DST_ADDR using L2 + */ +# define PACKET3_DMA_DATA_SI_SRC_SEL(x) ((x) << 29) + /* 0 - SRC_ADDR using SAS + * 1 - GDS + * 2 - DATA + * 3 - SRC_ADDR using L2 + */ +# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31) + int suite_basic_tests_init(void) { + struct amdgpu_gpu_info gpu_info = {0}; int r; r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle); - if (r == 0) - return CUE_SUCCESS; - else { + if (r) { if ((r == -EACCES) && (errno == EACCES)) printf("\n\nError:%s. " "Hint:Try to run this test program as root.", strerror(errno)); return CUE_SINIT_FAILED; } + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + if (r) + return CUE_SINIT_FAILED; + + family_id = gpu_info.family_id; + + return CUE_SUCCESS; } int suite_basic_tests_clean(void) @@ -301,7 +336,7 @@ static void amdgpu_command_submission_gfx_separate_ibs(void) uint32_t expired; amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle, va_handle_ce; - int r; + int r, i = 0; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -326,12 +361,14 @@ static void amdgpu_command_submission_gfx_separate_ibs(void) /* IT_SET_CE_DE_COUNTERS */ ptr = ib_result_ce_cpu; - ptr[0] = 0xc0008900; - ptr[1] = 0; - ptr[2] = 0xc0008400; - ptr[3] = 1; + if (family_id != AMDGPU_FAMILY_SI) { + ptr[i++] = 0xc0008900; + ptr[i++] = 0; + } + ptr[i++] = 0xc0008400; + ptr[i++] = 1; ib_info[0].ib_mc_address = ib_result_ce_mc_address; - ib_info[0].size = 4; + ib_info[0].size = i; ib_info[0].flags = AMDGPU_IB_FLAG_CE; /* IT_WAIT_ON_CE_COUNTER */ @@ -390,7 +427,7 @@ static void amdgpu_command_submission_gfx_shared_ib(void) uint32_t expired; amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle; - int r; + int r, i = 0; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -409,12 +446,14 @@ static void amdgpu_command_submission_gfx_shared_ib(void) /* IT_SET_CE_DE_COUNTERS */ ptr = ib_result_cpu; - ptr[0] = 0xc0008900; - ptr[1] = 0; - ptr[2] = 0xc0008400; - ptr[3] = 1; + if (family_id != AMDGPU_FAMILY_SI) { + ptr[i++] = 0xc0008900; + ptr[i++] = 0; + } + ptr[i++] = 0xc0008400; + ptr[i++] = 1; ib_info[0].ib_mc_address = ib_result_mc_address; - ib_info[0].size = 4; + ib_info[0].size = i; ib_info[0].flags = AMDGPU_IB_FLAG_CE; ptr = (uint32_t *)ib_result_cpu + 4; @@ -495,10 +534,19 @@ static void amdgpu_semaphore_test(void) struct amdgpu_cs_fence fence_status = {0}; uint32_t *ptr; uint32_t expired; + uint32_t sdma_nop, gfx_nop; amdgpu_bo_list_handle bo_list[2]; amdgpu_va_handle va_handle[2]; int r, i; + if (family_id == AMDGPU_FAMILY_SI) { + sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0); + gfx_nop = GFX_COMPUTE_NOP_SI; + } else { + sdma_nop = SDMA_PKT_HEADER_OP(SDMA_NOP); + gfx_nop = GFX_COMPUTE_NOP; + } + r = amdgpu_cs_create_semaphore(&sem); CU_ASSERT_EQUAL(r, 0); for (i = 0; i < 2; i++) { @@ -518,7 +566,7 @@ static void amdgpu_semaphore_test(void) /* 1. same context different engine */ ptr = ib_result_cpu[0]; - ptr[0] = SDMA_NOP; + ptr[0] = sdma_nop; ib_info[0].ib_mc_address = ib_result_mc_address[0]; ib_info[0].size = 1; @@ -535,7 +583,7 @@ static void amdgpu_semaphore_test(void) r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); ptr = ib_result_cpu[1]; - ptr[0] = GFX_COMPUTE_NOP; + ptr[0] = gfx_nop; ib_info[1].ib_mc_address = ib_result_mc_address[1]; ib_info[1].size = 1; @@ -559,7 +607,7 @@ static void amdgpu_semaphore_test(void) /* 2. same engine different context */ ptr = ib_result_cpu[0]; - ptr[0] = GFX_COMPUTE_NOP; + ptr[0] = gfx_nop; ib_info[0].ib_mc_address = ib_result_mc_address[0]; ib_info[0].size = 1; @@ -576,7 +624,7 @@ static void amdgpu_semaphore_test(void) r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); ptr = ib_result_cpu[1]; - ptr[0] = GFX_COMPUTE_NOP; + ptr[0] = gfx_nop; ib_info[1].ib_mc_address = ib_result_mc_address[1]; ib_info[1].size = 1; @@ -597,6 +645,7 @@ static void amdgpu_semaphore_test(void) 500000000, 0, &expired); CU_ASSERT_EQUAL(r, 0); CU_ASSERT_EQUAL(expired, true); + for (i = 0; i < 2; i++) { r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], ib_result_mc_address[i], 4096); @@ -627,11 +676,15 @@ static void amdgpu_command_submission_compute_nop(void) int i, r, instance; amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle; + struct drm_amdgpu_info_hw_ip info; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info); + CU_ASSERT_EQUAL(r, 0); r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); - for (instance = 0; instance < 8; instance++) { + for (instance = 0; (1 << instance) & info.available_rings; instance++) { r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, AMDGPU_GEM_DOMAIN_GTT, 0, &ib_result_handle, &ib_result_cpu, @@ -643,8 +696,8 @@ static void amdgpu_command_submission_compute_nop(void) CU_ASSERT_EQUAL(r, 0); ptr = ib_result_cpu; - for (i = 0; i < 16; ++i) - ptr[i] = 0xffff1000; + memset(ptr, 0, 16); + ptr[0]=PACKET3(PACKET3_NOP, 14); memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); ib_info.ib_mc_address = ib_result_mc_address; @@ -805,16 +858,12 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) uint32_t *pm4; struct amdgpu_cs_ib_info *ib_info; struct amdgpu_cs_request *ibs_request; - struct amdgpu_gpu_info gpu_info = {0}; uint64_t bo_mc; volatile uint32_t *bo_cpu; int i, j, r, loop; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -850,13 +899,17 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) /* fulfill PM4: test DMA write-linear */ i = j = 0; if (ip_type == AMDGPU_HW_IP_DMA) { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + if (family_id == AMDGPU_FAMILY_SI) + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, + sdma_write_length); + else + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); pm4[i++] = 0xffffffff & bo_mc; pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - if (gpu_info.family_id >= AMDGPU_FAMILY_AI) + if (family_id >= AMDGPU_FAMILY_AI) pm4[i++] = sdma_write_length - 1; - else + else if (family_id != AMDGPU_FAMILY_SI) pm4[i++] = sdma_write_length; while(j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; @@ -913,16 +966,12 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) uint32_t *pm4; struct amdgpu_cs_ib_info *ib_info; struct amdgpu_cs_request *ibs_request; - struct amdgpu_gpu_info gpu_info = {0}; uint64_t bo_mc; volatile uint32_t *bo_cpu; int i, j, r, loop; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -957,27 +1006,47 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) /* fulfill PM4: test DMA const fill */ i = j = 0; if (ip_type == AMDGPU_HW_IP_DMA) { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, - SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0xdeadbeaf; - if (gpu_info.family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else - pm4[i++] = sdma_write_length; + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, 0, 0, 0, + sdma_write_length / 4); + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; + } else { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, + SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0xdeadbeaf; + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; + } } else if ((ip_type == AMDGPU_HW_IP_GFX) || (ip_type == AMDGPU_HW_IP_COMPUTE)) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(2) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = 0; - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); + pm4[i++] = 0xdeadbeaf; + pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | + PACKET3_DMA_DATA_SI_DST_SEL(0) | + PACKET3_DMA_DATA_SI_SRC_SEL(2) | + PACKET3_DMA_DATA_SI_CP_SYNC; + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; + } else { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(2) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = 0; + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; + } } amdgpu_test_exec_cs_helper(context_handle, @@ -1023,16 +1092,12 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) uint32_t *pm4; struct amdgpu_cs_ib_info *ib_info; struct amdgpu_cs_request *ibs_request; - struct amdgpu_gpu_info gpu_info = {0}; uint64_t bo1_mc, bo2_mc; volatile unsigned char *bo1_cpu, *bo2_cpu; int i, j, r, loop1, loop2; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle bo1_va_handle, bo2_va_handle; - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -1083,28 +1148,51 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) /* fulfill PM4: test DMA copy linear */ i = j = 0; if (ip_type == AMDGPU_HW_IP_DMA) { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - if (gpu_info.family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else - pm4[i++] = sdma_write_length; - pm4[i++] = 0; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, + sdma_write_length); + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + } else { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; + pm4[i++] = 0; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + } + } else if ((ip_type == AMDGPU_HW_IP_GFX) || (ip_type == AMDGPU_HW_IP_COMPUTE)) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(0) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xfffffffc & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xfffffffc & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = sdma_write_length; + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); + pm4[i++] = 0xfffffffc & bo1_mc; + pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | + PACKET3_DMA_DATA_SI_DST_SEL(0) | + PACKET3_DMA_DATA_SI_SRC_SEL(0) | + PACKET3_DMA_DATA_SI_CP_SYNC | + (0xffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xfffffffc & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = sdma_write_length; + } else { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(0) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xfffffffc & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xfffffffc & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = sdma_write_length; + } } amdgpu_test_exec_cs_helper(context_handle, @@ -1165,7 +1253,7 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle, va_handle_ce; int r; - int i, ib_cs_num = 2; + int i = 0, ib_cs_num = 2; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -1190,12 +1278,14 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) /* IT_SET_CE_DE_COUNTERS */ ptr = ib_result_ce_cpu; - ptr[0] = 0xc0008900; - ptr[1] = 0; - ptr[2] = 0xc0008400; - ptr[3] = 1; + if (family_id != AMDGPU_FAMILY_SI) { + ptr[i++] = 0xc0008900; + ptr[i++] = 0; + } + ptr[i++] = 0xc0008400; + ptr[i++] = 1; ib_info[0].ib_mc_address = ib_result_ce_mc_address; - ib_info[0].size = 4; + ib_info[0].size = i; ib_info[0].flags = AMDGPU_IB_FLAG_CE; /* IT_WAIT_ON_CE_COUNTER */ @@ -1296,11 +1386,19 @@ static void amdgpu_userptr_test(void) handle = buf_handle; j = i = 0; - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + + if (family_id == AMDGPU_FAMILY_SI) + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, + sdma_write_length); + else + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); pm4[i++] = 0xffffffff & bo_mc; pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else if (family_id != AMDGPU_FAMILY_SI) + pm4[i++] = sdma_write_length; while (j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index df55c70d..3b2f17db 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -90,7 +90,7 @@ int suite_cs_tests_init(void) chip_rev = device_handle->info.chip_rev; chip_id = device_handle->info.chip_external_rev; - if (family_id >= AMDGPU_FAMILY_RV) { + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n"); return CUE_SUCCESS; } @@ -119,21 +119,24 @@ int suite_cs_tests_clean(void) { int r; - if (family_id >= AMDGPU_FAMILY_RV) - return CUE_SUCCESS; - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + } else { + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + } return CUE_SUCCESS; } @@ -200,7 +203,7 @@ static void amdgpu_cs_uvd_create(void) void *msg; int i, r; - if (family_id >= AMDGPU_FAMILY_RV) + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) return; req.alloc_size = 4*1024; @@ -274,7 +277,7 @@ static void amdgpu_cs_uvd_decode(void) uint8_t *ptr; int i, r; - if (family_id >= AMDGPU_FAMILY_RV) + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) return; req.alloc_size = 4*1024; /* msg */ @@ -416,7 +419,7 @@ static void amdgpu_cs_uvd_destroy(void) void *msg; int i, r; - if (family_id >= AMDGPU_FAMILY_RV) + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) return; req.alloc_size = 4*1024; diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c index 8d61a3b1..cf44c132 100644 --- a/tests/amdgpu/vce_tests.c +++ b/tests/amdgpu/vce_tests.c @@ -106,7 +106,7 @@ int suite_vce_tests_init(void) family_id = device_handle->info.family_id; vce_harvest_config = device_handle->info.vce_harvest_config; - if (family_id >= AMDGPU_FAMILY_RV) { + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); return CUE_SUCCESS; } @@ -131,21 +131,24 @@ int suite_vce_tests_clean(void) { int r; - if (family_id >= AMDGPU_FAMILY_RV) - return CUE_SUCCESS; - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + } else { + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + } return CUE_SUCCESS; } @@ -245,7 +248,7 @@ static void amdgpu_cs_vce_create(void) unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; int len, r; - if (family_id >= AMDGPU_FAMILY_RV) + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) return; enc.width = vce_create[6]; @@ -441,7 +444,7 @@ static void amdgpu_cs_vce_encode(void) unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; int i, r; - if (family_id >= AMDGPU_FAMILY_RV) + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) return; vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; @@ -522,7 +525,7 @@ static void amdgpu_cs_vce_destroy(void) { int len, r; - if (family_id >= AMDGPU_FAMILY_RV) + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) return; num_resources = 0; -- cgit v1.2.3-54-g00ecf From ac2b806c4556c8339f5eb95578884278b1925acb Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Sun, 30 Jul 2017 21:27:38 +0100 Subject: freedreno: remove dead error path `pipe` cannot be non-null, so the label reduces to a simple return. Then, there is no point initialising `pipe` just to overwrite it before anyone reads it. Signed-off-by: Eric Engestrom Reviewed-by: Rob Clark --- freedreno/freedreno_pipe.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c index 3f8c8342..e69cb28c 100644 --- a/freedreno/freedreno_pipe.c +++ b/freedreno/freedreno_pipe.c @@ -36,18 +36,18 @@ struct fd_pipe * fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id) { - struct fd_pipe *pipe = NULL; + struct fd_pipe *pipe; uint64_t val; if (id > FD_PIPE_MAX) { ERROR_MSG("invalid pipe id: %d", id); - goto fail; + return NULL; } pipe = dev->funcs->pipe_new(dev, id); if (!pipe) { ERROR_MSG("allocation failed"); - goto fail; + return NULL; } pipe->dev = dev; @@ -57,10 +57,6 @@ fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id) pipe->gpu_id = val; return pipe; -fail: - if (pipe) - fd_pipe_del(pipe); - return NULL; } void fd_pipe_del(struct fd_pipe *pipe) -- cgit v1.2.3-54-g00ecf From 6338e452c907a5e8024b2f3615795ac68dcf0a35 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Sun, 30 Jul 2017 21:27:39 +0100 Subject: freedreno/msm: remove dead error path `ring` cannot be non-null, so the label reduces to a simple return. Then, there is no point initialising `ring` just to overwrite it before anyone reads it. Signed-off-by: Eric Engestrom Reviewed-by: Rob Clark --- freedreno/msm/msm_ringbuffer.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index c3b2eded..5b28feaa 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c @@ -589,12 +589,12 @@ drm_private struct fd_ringbuffer * msm_ringbuffer_new(struct fd_pipe *pipe, uint32_t size) { struct msm_ringbuffer *msm_ring; - struct fd_ringbuffer *ring = NULL; + struct fd_ringbuffer *ring; msm_ring = calloc(1, sizeof(*msm_ring)); if (!msm_ring) { ERROR_MSG("allocation failed"); - goto fail; + return NULL; } if (size == 0) { @@ -614,8 +614,4 @@ drm_private struct fd_ringbuffer * msm_ringbuffer_new(struct fd_pipe *pipe, ring_cmd_new(ring, size); return ring; -fail: - if (ring) - fd_ringbuffer_del(ring); - return NULL; } -- cgit v1.2.3-54-g00ecf From ceb70a6b1015be5ccc7858c4d3e29c13acbf71b7 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Sun, 30 Jul 2017 21:27:40 +0100 Subject: freedreno: prevent deadlock in error path Signed-off-by: Eric Engestrom Reviewed-by: Rob Clark --- freedreno/freedreno_bo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index 10949ebf..7f8ea59c 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -138,6 +138,7 @@ fd_bo_from_dmabuf(struct fd_device *dev, int fd) pthread_mutex_lock(&table_lock); ret = drmPrimeFDToHandle(dev->fd, fd, &handle); if (ret) { + pthread_mutex_unlock(&table_lock); return NULL; } -- cgit v1.2.3-54-g00ecf From 4d244155945f5531b4d9735bbe73c887aac81070 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Mon, 7 Aug 2017 22:35:11 +0800 Subject: amdgpu: fix missing mutex unlock before return Reviewed-by: Christian König Signed-off-by: Monk Liu Signed-off-by: Alex Deucher --- amdgpu/amdgpu_bo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 5ac456be..d2725da8 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -302,6 +302,7 @@ int amdgpu_bo_import(amdgpu_device_handle dev, /* Get a KMS handle. */ r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle); if (r) { + pthread_mutex_unlock(&dev->bo_table_mutex); return r; } -- cgit v1.2.3-54-g00ecf From 2a89ae5d7a7d5845226ed85146140ff4c8788d59 Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 8 Aug 2017 15:34:20 +0800 Subject: amdgpu: fix race issue between two bo functions(v2) there is race issue between two threads on amdgpu_bo_reference and amdgpu_bo_import, this patch tends to fix it by moving the pthread_mutex_lock out of bo_free_internal and move to bo_reference to cover the update_reference part. The mutex_unlock in bo_import should also cover bo refcount increasement. Reviewed-by: Christian König Signed-off-by: Monk Liu Signed-off-by: Alex Deucher --- amdgpu/amdgpu_bo.c | 5 +---- amdgpu/amdgpu_internal.h | 13 +++++++++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index d2725da8..803fe54c 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -56,14 +56,12 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev, drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo) { /* Remove the buffer from the hash tables. */ - pthread_mutex_lock(&bo->dev->bo_table_mutex); util_hash_table_remove(bo->dev->bo_handles, (void*)(uintptr_t)bo->handle); if (bo->flink_name) { util_hash_table_remove(bo->dev->bo_flink_names, (void*)(uintptr_t)bo->flink_name); } - pthread_mutex_unlock(&bo->dev->bo_table_mutex); /* Release CPU access. */ if (bo->cpu_map_count > 0) { @@ -342,10 +340,9 @@ int amdgpu_bo_import(amdgpu_device_handle dev, } if (bo) { - pthread_mutex_unlock(&dev->bo_table_mutex); - /* The buffer already exists, just bump the refcount. */ atomic_inc(&bo->refcount); + pthread_mutex_unlock(&dev->bo_table_mutex); output->buf_handle = bo; output->alloc_size = bo->alloc_size; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index e68246bf..28d1f38f 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -206,8 +206,17 @@ static inline bool update_references(atomic_t *dst, atomic_t *src) static inline void amdgpu_bo_reference(struct amdgpu_bo **dst, struct amdgpu_bo *src) { - if (update_references(&(*dst)->refcount, &src->refcount)) - amdgpu_bo_free_internal(*dst); + pthread_mutex_t *mlock; + struct amdgpu_bo* bo = *dst; + + assert(bo != NULL); + mlock = &bo->dev->bo_table_mutex; + pthread_mutex_lock(mlock); + + if (update_references(&bo->refcount, src?&src->refcount:NULL)) + amdgpu_bo_free_internal(bo); + + pthread_mutex_unlock(mlock); *dst = src; } -- cgit v1.2.3-54-g00ecf From 687d250797ff0028fee949cdd66c9f012f69992d Mon Sep 17 00:00:00 2001 From: Monk Liu Date: Tue, 8 Aug 2017 12:09:07 -0400 Subject: amdgpu: merge and cleanup amdgpu_bo_free since bo_reference and bo_internal_free are all only used by bo_free, so we just merge them together Reviewed-by: Christian König Signed-off-by: Monk Liu Signed-off-by: Alex Deucher --- amdgpu/amdgpu_bo.c | 52 +++++++++++++++++++++++++++--------------------- amdgpu/amdgpu_internal.h | 33 ------------------------------ 2 files changed, 29 insertions(+), 56 deletions(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 803fe54c..3853fd03 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -53,27 +53,6 @@ static void amdgpu_close_kms_handle(amdgpu_device_handle dev, drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args); } -drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo) -{ - /* Remove the buffer from the hash tables. */ - util_hash_table_remove(bo->dev->bo_handles, - (void*)(uintptr_t)bo->handle); - if (bo->flink_name) { - util_hash_table_remove(bo->dev->bo_flink_names, - (void*)(uintptr_t)bo->flink_name); - } - - /* Release CPU access. */ - if (bo->cpu_map_count > 0) { - bo->cpu_map_count = 1; - amdgpu_bo_cpu_unmap(bo); - } - - amdgpu_close_kms_handle(bo->dev, bo->handle); - pthread_mutex_destroy(&bo->cpu_access_mutex); - free(bo); -} - int amdgpu_bo_alloc(amdgpu_device_handle dev, struct amdgpu_bo_alloc_request *alloc_buffer, amdgpu_bo_handle *buf_handle) @@ -417,8 +396,35 @@ int amdgpu_bo_import(amdgpu_device_handle dev, int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { - /* Just drop the reference. */ - amdgpu_bo_reference(&buf_handle, NULL); + struct amdgpu_device *dev; + struct amdgpu_bo *bo = buf_handle; + + assert(bo != NULL); + dev = bo->dev; + pthread_mutex_lock(&dev->bo_table_mutex); + + if (update_references(&bo->refcount, NULL)) { + /* Remove the buffer from the hash tables. */ + util_hash_table_remove(dev->bo_handles, + (void*)(uintptr_t)bo->handle); + + if (bo->flink_name) { + util_hash_table_remove(dev->bo_flink_names, + (void*)(uintptr_t)bo->flink_name); + } + + /* Release CPU access. */ + if (bo->cpu_map_count > 0) { + bo->cpu_map_count = 1; + amdgpu_bo_cpu_unmap(bo); + } + + amdgpu_close_kms_handle(dev, bo->handle); + pthread_mutex_destroy(&bo->cpu_access_mutex); + free(bo); + } + + pthread_mutex_unlock(&dev->bo_table_mutex); return 0; } diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 28d1f38f..56d15112 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -143,8 +143,6 @@ struct amdgpu_semaphore { * Functions. */ -drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo); - drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, uint64_t max, uint64_t alignment); @@ -189,35 +187,4 @@ static inline bool update_references(atomic_t *dst, atomic_t *src) return false; } -/** - * Assignment between two amdgpu_bo pointers with reference counting. - * - * Usage: - * struct amdgpu_bo *dst = ... , *src = ...; - * - * dst = src; - * // No reference counting. Only use this when you need to move - * // a reference from one pointer to another. - * - * amdgpu_bo_reference(&dst, src); - * // Reference counters are updated. dst is decremented and src is - * // incremented. dst is freed if its reference counter is 0. - */ -static inline void amdgpu_bo_reference(struct amdgpu_bo **dst, - struct amdgpu_bo *src) -{ - pthread_mutex_t *mlock; - struct amdgpu_bo* bo = *dst; - - assert(bo != NULL); - mlock = &bo->dev->bo_table_mutex; - pthread_mutex_lock(mlock); - - if (update_references(&bo->refcount, src?&src->refcount:NULL)) - amdgpu_bo_free_internal(bo); - - pthread_mutex_unlock(mlock); - *dst = src; -} - #endif -- cgit v1.2.3-54-g00ecf From 7ec689a5406a4c5f468e126007c5aa9d72dd7f59 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Mon, 14 Aug 2017 16:12:19 -0700 Subject: drm: Pull new modifier uapi into drm_fourcc and drm_mode Reviewed-by: Daniel Stone --- include/drm/drm_fourcc.h | 31 ++++++++++++++++++++++++++++++ include/drm/drm_mode.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index 7586c46f..3ad838d3 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -185,6 +185,8 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 /* add more to the end as needed */ +#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) + #define fourcc_mod_code(vendor, val) \ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) @@ -196,6 +198,15 @@ extern "C" { * authoritative source for all of these. */ +/* + * Invalid Modifier + * + * This modifier can be used as a sentinel to terminate the format modifiers + * list, or to initialize a variable with an invalid modifier. It might also be + * used to report an error back to userspace for certain APIs. + */ +#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) + /* * Linear Layout * @@ -252,6 +263,26 @@ extern "C" { */ #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) +/* + * Intel color control surface (CCS) for render compression + * + * The framebuffer format must be one of the 8:8:8:8 RGB formats. + * The main surface will be plane index 0 and must be Y/Yf-tiled, + * the CCS will be plane index 1. + * + * Each CCS tile matches a 1024x512 pixel area of the main surface. + * To match certain aspects of the 3D hardware the CCS is + * considered to be made up of normal 128Bx32 Y tiles, Thus + * the CCS pitch must be specified in multiples of 128 bytes. + * + * In reality the CCS tile appears to be a 64Bx64 Y tile, composed + * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. + * But that fact is not relevant unless the memory is accessed + * directly. + */ +#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) +#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index 70571af6..08077978 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -657,6 +657,56 @@ struct drm_mode_atomic { __u64 user_data; }; +struct drm_format_modifier_blob { +#define FORMAT_BLOB_CURRENT 1 + /* Version of this blob format */ + __u32 version; + + /* Flags */ + __u32 flags; + + /* Number of fourcc formats supported */ + __u32 count_formats; + + /* Where in this blob the formats exist (in bytes) */ + __u32 formats_offset; + + /* Number of drm_format_modifiers */ + __u32 count_modifiers; + + /* Where in this blob the modifiers exist (in bytes) */ + __u32 modifiers_offset; + + /* u32 formats[] */ + /* struct drm_format_modifier modifiers[] */ +}; + +struct drm_format_modifier { + /* Bitmask of formats in get_plane format list this info applies to. The + * offset allows a sliding window of which 64 formats (bits). + * + * Some examples: + * In today's world with < 65 formats, and formats 0, and 2 are + * supported + * 0x0000000000000005 + * ^-offset = 0, formats = 5 + * + * If the number formats grew to 128, and formats 98-102 are + * supported with the modifier: + * + * 0x0000003c00000000 0000000000000000 + * ^ + * |__offset = 64, formats = 0x3c00000000 + * + */ + __u64 formats; + __u32 offset; + __u32 pad; + + /* The modifier that applies to the >get_plane format list bitmask. */ + __u64 modifier; +}; + /** * Create a new 'blob' data property, copying length bytes from data pointer, * and returning new blob ID. -- cgit v1.2.3-54-g00ecf From 9d133dd08720d80dfc8ce098bf0972ebd05c454d Mon Sep 17 00:00:00 2001 From: Boyuan Zhang Date: Tue, 15 Aug 2017 11:33:43 -0400 Subject: tests/amdgpu: add uvd encode unit tests Signed-off-by: Boyuan Zhang Acked-by: Alex Deucher Acked-by: Christian König --- tests/amdgpu/Makefile.am | 1 + tests/amdgpu/amdgpu_test.c | 6 + tests/amdgpu/amdgpu_test.h | 15 ++ tests/amdgpu/frame.h | 2 +- tests/amdgpu/uvd_enc_tests.c | 500 ++++++++++++++++++++++++++++++++++++++++ tests/amdgpu/uve_ib.h | 527 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 1050 insertions(+), 1 deletion(-) create mode 100644 tests/amdgpu/uvd_enc_tests.c create mode 100644 tests/amdgpu/uve_ib.h diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index 9e085784..13b3dc8e 100644 --- a/tests/amdgpu/Makefile.am +++ b/tests/amdgpu/Makefile.am @@ -27,4 +27,5 @@ amdgpu_test_SOURCES = \ vce_tests.c \ vce_ib.h \ frame.h \ + uvd_enc_tests.c \ vcn_tests.c diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 1d44b09e..cd6b8262 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -91,6 +91,12 @@ static CU_SuiteInfo suites[] = { .pCleanupFunc = suite_vcn_tests_clean, .pTests = vcn_tests, }, + { + .pName = "UVD ENC Tests", + .pInitFunc = suite_uvd_enc_tests_init, + .pCleanupFunc = suite_uvd_enc_tests_clean, + .pTests = uvd_enc_tests, + }, CU_SUITE_INFO_NULL, }; diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index c75a07a4..d0b61baa 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -119,6 +119,21 @@ int suite_vcn_tests_clean(); + */ extern CU_TestInfo vcn_tests[]; +/** + * Initialize uvd enc test suite + */ +int suite_uvd_enc_tests_init(); + +/** + * Deinitialize uvd enc test suite + */ +int suite_uvd_enc_tests_clean(); + +/** + * Tests in uvd enc test suite + */ +extern CU_TestInfo uvd_enc_tests[]; + /** * Helper functions */ diff --git a/tests/amdgpu/frame.h b/tests/amdgpu/frame.h index 4c946c27..335401c1 100644 --- a/tests/amdgpu/frame.h +++ b/tests/amdgpu/frame.h @@ -24,7 +24,7 @@ #ifndef _frame_h_ #define _frame_h_ -const uint8_t frame[] = { +static const uint8_t frame[] = { 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c new file mode 100644 index 00000000..6c19f7b6 --- /dev/null +++ b/tests/amdgpu/uvd_enc_tests.c @@ -0,0 +1,500 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include + +#include "CUnit/Basic.h" + +#include "util_math.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" +#include "frame.h" +#include "uve_ib.h" + +#define IB_SIZE 4096 +#define MAX_RESOURCES 16 + +struct amdgpu_uvd_enc_bo { + amdgpu_bo_handle handle; + amdgpu_va_handle va_handle; + uint64_t addr; + uint64_t size; + uint8_t *ptr; +}; + +struct amdgpu_uvd_enc { + unsigned width; + unsigned height; + struct amdgpu_uvd_enc_bo session; + struct amdgpu_uvd_enc_bo vbuf; + struct amdgpu_uvd_enc_bo bs; + struct amdgpu_uvd_enc_bo fb; + struct amdgpu_uvd_enc_bo cpb; +}; + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; +static uint32_t family_id; + +static amdgpu_context_handle context_handle; +static amdgpu_bo_handle ib_handle; +static amdgpu_va_handle ib_va_handle; +static uint64_t ib_mc_address; +static uint32_t *ib_cpu; + +static struct amdgpu_uvd_enc enc; +static amdgpu_bo_handle resources[MAX_RESOURCES]; +static unsigned num_resources; + +static void amdgpu_cs_uvd_enc_create(void); +static void amdgpu_cs_uvd_enc_session_init(void); +static void amdgpu_cs_uvd_enc_encode(void); +static void amdgpu_cs_uvd_enc_destroy(void); + +CU_TestInfo uvd_enc_tests[] = { + { "UVD ENC create", amdgpu_cs_uvd_enc_create }, + { "UVD ENC session init", amdgpu_cs_uvd_enc_session_init }, + { "UVD ENC encode", amdgpu_cs_uvd_enc_encode }, + { "UVD ENC destroy", amdgpu_cs_uvd_enc_destroy }, + CU_TEST_INFO_NULL, +}; + +int suite_uvd_enc_tests_init(void) +{ + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + if (r) + return CUE_SINIT_FAILED; + + family_id = device_handle->info.family_id; + + if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { + printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); + return CUE_SUCCESS; + } + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + if (r) + return CUE_SINIT_FAILED; + + r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_handle, (void**)&ib_cpu, + &ib_mc_address, &ib_va_handle); + if (r) + return CUE_SINIT_FAILED; + + return CUE_SUCCESS; +} + +int suite_uvd_enc_tests_clean(void) +{ + int r; + + if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + + return CUE_SUCCESS; + } else { + + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + } + + return CUE_SUCCESS; +} + +static int submit(unsigned ndw, unsigned ip) +{ + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info = {0}; + struct amdgpu_cs_fence fence_status = {0}; + uint32_t expired; + int r; + + ib_info.ib_mc_address = ib_mc_address; + ib_info.size = ndw; + + ibs_request.ip_type = ip; + + r = amdgpu_bo_list_create(device_handle, num_resources, resources, + NULL, &ibs_request.resources); + if (r) + return r; + + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.fence_info.handle = NULL; + + r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); + if (r) + return r; + + r = amdgpu_bo_list_destroy(ibs_request.resources); + if (r) + return r; + + fence_status.context = context_handle; + fence_status.ip_type = ip; + fence_status.fence = ibs_request.seq_no; + + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); + if (r) + return r; + + return 0; +} + +static void alloc_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo, + unsigned size, unsigned domain) +{ + struct amdgpu_bo_alloc_request req = {0}; + amdgpu_bo_handle buf_handle; + amdgpu_va_handle va_handle; + uint64_t va = 0; + int r; + + req.alloc_size = ALIGN(size, 4096); + req.preferred_heap = domain; + r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_va_range_alloc(device_handle, + amdgpu_gpu_va_range_general, + req.alloc_size, 1, 0, &va, + &va_handle, 0); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, + AMDGPU_VA_OP_MAP); + CU_ASSERT_EQUAL(r, 0); + uvd_enc_bo->addr = va; + uvd_enc_bo->handle = buf_handle; + uvd_enc_bo->size = req.alloc_size; + uvd_enc_bo->va_handle = va_handle; + r = amdgpu_bo_cpu_map(uvd_enc_bo->handle, (void **)&uvd_enc_bo->ptr); + CU_ASSERT_EQUAL(r, 0); + memset(uvd_enc_bo->ptr, 0, size); + r = amdgpu_bo_cpu_unmap(uvd_enc_bo->handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) +{ + int r; + + r = amdgpu_bo_va_op(uvd_enc_bo->handle, 0, uvd_enc_bo->size, + uvd_enc_bo->addr, 0, AMDGPU_VA_OP_UNMAP); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_va_range_free(uvd_enc_bo->va_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_free(uvd_enc_bo->handle); + CU_ASSERT_EQUAL(r, 0); + memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); +} + +static void amdgpu_cs_uvd_enc_create(void) +{ + int len, r; + + if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + return; + + enc.width = 160; + enc.height = 128; + + num_resources = 0; + alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); + resources[num_resources++] = enc.session.handle; + resources[num_resources++] = ib_handle; +} + +static void check_result(struct amdgpu_uvd_enc *enc) +{ + uint64_t sum; + uint32_t s = 26382; + uint32_t *ptr, size; + int i, j, r; + + r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr); + CU_ASSERT_EQUAL(r, 0); + ptr = (uint32_t *)enc->fb.ptr; + size = ptr[6]; + r = amdgpu_bo_cpu_unmap(enc->fb.handle); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_cpu_map(enc->bs.handle, (void **)&enc->bs.ptr); + CU_ASSERT_EQUAL(r, 0); + for (j = 0, sum = 0; j < size; ++j) + sum += enc->bs.ptr[j]; + CU_ASSERT_EQUAL(sum, s); + r = amdgpu_bo_cpu_unmap(enc->bs.handle); + CU_ASSERT_EQUAL(r, 0); + +} + +static void amdgpu_cs_uvd_enc_session_init(void) +{ + int len, r; + + if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + return; + + len = 0; + memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); + len += sizeof(uve_session_info) / 4; + ib_cpu[len++] = enc.session.addr >> 32; + ib_cpu[len++] = enc.session.addr; + + memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); + len += sizeof(uve_task_info) / 4; + ib_cpu[len++] = 0x000000d8; + ib_cpu[len++] = 0x00000000; + ib_cpu[len++] = 0x00000000; + + memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); + len += sizeof(uve_op_init) / 4; + + memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init)); + len += sizeof(uve_session_init) / 4; + + memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl)); + len += sizeof(uve_layer_ctrl) / 4; + + memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl)); + len += sizeof(uve_slice_ctrl) / 4; + + memcpy((ib_cpu + len), uve_spec_misc, sizeof(uve_spec_misc)); + len += sizeof(uve_spec_misc) / 4; + + memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init)); + len += sizeof(uve_rc_session_init) / 4; + + memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter)); + len += sizeof(uve_deblocking_filter) / 4; + + memcpy((ib_cpu + len), uve_quality_params, sizeof(uve_quality_params)); + len += sizeof(uve_quality_params) / 4; + + memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc)); + len += sizeof(uve_op_init_rc) / 4; + + memcpy((ib_cpu + len), uve_op_init_rc_vbv_level, sizeof(uve_op_init_rc_vbv_level)); + len += sizeof(uve_op_init_rc_vbv_level) / 4; + + r = submit(len, AMDGPU_HW_IP_UVD_ENC); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_cs_uvd_enc_encode(void) +{ + int len, r, i; + uint64_t luma_offset, chroma_offset; + uint32_t vbuf_size, bs_size = 0x003f4800, cpb_size; + unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; + vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; + cpb_size = vbuf_size * 10; + + if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + return; + + num_resources = 0; + alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM); + resources[num_resources++] = enc.fb.handle; + alloc_resource(&enc.bs, bs_size, AMDGPU_GEM_DOMAIN_VRAM); + resources[num_resources++] = enc.bs.handle; + alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); + resources[num_resources++] = enc.vbuf.handle; + alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); + resources[num_resources++] = enc.cpb.handle; + resources[num_resources++] = ib_handle; + + r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); + CU_ASSERT_EQUAL(r, 0); + + memset(enc.vbuf.ptr, 0, vbuf_size); + for (i = 0; i < enc.height; ++i) { + memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); + enc.vbuf.ptr += ALIGN(enc.width, align); + } + for (i = 0; i < enc.height / 2; ++i) { + memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); + enc.vbuf.ptr += ALIGN(enc.width, align); + } + + r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); + CU_ASSERT_EQUAL(r, 0); + + len = 0; + memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); + len += sizeof(uve_session_info) / 4; + ib_cpu[len++] = enc.session.addr >> 32; + ib_cpu[len++] = enc.session.addr; + + memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); + len += sizeof(uve_task_info) / 4; + ib_cpu[len++] = 0x000005e0; + ib_cpu[len++] = 0x00000001; + ib_cpu[len++] = 0x00000001; + + memcpy((ib_cpu + len), uve_nalu_buffer_1, sizeof(uve_nalu_buffer_1)); + len += sizeof(uve_nalu_buffer_1) / 4; + + memcpy((ib_cpu + len), uve_nalu_buffer_2, sizeof(uve_nalu_buffer_2)); + len += sizeof(uve_nalu_buffer_2) / 4; + + memcpy((ib_cpu + len), uve_nalu_buffer_3, sizeof(uve_nalu_buffer_3)); + len += sizeof(uve_nalu_buffer_3) / 4; + + memcpy((ib_cpu + len), uve_nalu_buffer_4, sizeof(uve_nalu_buffer_4)); + len += sizeof(uve_nalu_buffer_4) / 4; + + memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); + len += sizeof(uve_slice_header) / 4; + + ib_cpu[len++] = 0x00000254; + ib_cpu[len++] = 0x00000010; + ib_cpu[len++] = enc.cpb.addr >> 32; + ib_cpu[len++] = enc.cpb.addr; + memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); + len += sizeof(uve_ctx_buffer) / 4; + + memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer)); + len += sizeof(uve_bitstream_buffer) / 4; + ib_cpu[len++] = 0x00000000; + ib_cpu[len++] = enc.bs.addr >> 32; + ib_cpu[len++] = enc.bs.addr; + ib_cpu[len++] = 0x003f4800; + ib_cpu[len++] = 0x00000000; + + memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); + len += sizeof(uve_feedback_buffer) / 4; + ib_cpu[len++] = enc.fb.addr >> 32; + ib_cpu[len++] = enc.fb.addr; + ib_cpu[len++] = 0x00000010; + ib_cpu[len++] = 0x00000028; + + memcpy((ib_cpu + len), uve_feedback_buffer_additional, sizeof(uve_feedback_buffer_additional)); + len += sizeof(uve_feedback_buffer_additional) / 4; + + memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); + len += sizeof(uve_intra_refresh) / 4; + + memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); + len += sizeof(uve_layer_select) / 4; + + memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); + len += sizeof(uve_rc_layer_init) / 4; + + memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); + len += sizeof(uve_layer_select) / 4; + + memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic)); + len += sizeof(uve_rc_per_pic) / 4; + + unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); + luma_offset = enc.vbuf.addr; + chroma_offset = luma_offset + luma_size; + ib_cpu[len++] = 0x00000054; + ib_cpu[len++] = 0x0000000c; + ib_cpu[len++] = 0x00000002; + ib_cpu[len++] = 0x003f4800; + ib_cpu[len++] = luma_offset >> 32; + ib_cpu[len++] = luma_offset; + ib_cpu[len++] = chroma_offset >> 32; + ib_cpu[len++] = chroma_offset; + memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); + len += sizeof(uve_encode_param) / 4; + + memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode)); + len += sizeof(uve_op_speed_enc_mode) / 4; + + memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode)); + len += sizeof(uve_op_encode) / 4; + + r = submit(len, AMDGPU_HW_IP_UVD_ENC); + CU_ASSERT_EQUAL(r, 0); + + check_result(&enc); + + free_resource(&enc.fb); + free_resource(&enc.bs); + free_resource(&enc.vbuf); + free_resource(&enc.cpb); +} + +static void amdgpu_cs_uvd_enc_destroy(void) +{ + struct amdgpu_uvd_enc_bo sw_ctx; + int len, r; + + if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + return; + + num_resources = 0; + resources[num_resources++] = ib_handle; + + len = 0; + memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); + len += sizeof(uve_session_info) / 4; + ib_cpu[len++] = enc.session.addr >> 32; + ib_cpu[len++] = enc.session.addr; + + memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); + len += sizeof(uve_task_info) / 4; + ib_cpu[len++] = 0xffffffff; + ib_cpu[len++] = 0x00000002; + ib_cpu[len++] = 0x00000000; + + memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close)); + len += sizeof(uve_op_close) / 4; + + r = submit(len, AMDGPU_HW_IP_UVD_ENC); + CU_ASSERT_EQUAL(r, 0); + + free_resource(&enc.session); +} diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h new file mode 100644 index 00000000..9abd4066 --- /dev/null +++ b/tests/amdgpu/uve_ib.h @@ -0,0 +1,527 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#ifndef _uve_ib_h_ +#define _uve_ib_h_ + +static const uint32_t uve_session_info[] = { + 0x00000018, + 0x00000001, + 0x00000000, + 0x00010000, +}; + +static const uint32_t uve_task_info[] = { + 0x00000014, + 0x00000002, +}; + +static const uint32_t uve_session_init[] = { + 0x00000020, + 0x00000003, + 0x000000c0, + 0x00000080, + 0x00000020, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const uint32_t uve_layer_ctrl[] = { + 0x00000010, + 0x00000004, + 0x00000001, + 0x00000001, +}; + +static const uint32_t uve_layer_select[] = { + 0x0000000c, + 0x00000005, + 0x00000000, +}; + +static const uint32_t uve_slice_ctrl[] = { + 0x00000014, + 0x00000006, + 0x00000000, + 0x00000006, + 0x00000006, +}; + +static const uint32_t uve_spec_misc[] = { + 0x00000024, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000001, + 0x00000001, +}; + +static const uint32_t uve_rc_session_init[] = { + 0x00000010, + 0x00000008, + 0x00000000, + 0x00000040, +}; + +static const uint32_t uve_rc_layer_init[] = { + 0x00000028, + 0x00000009, + 0x001e8480, + 0x001e8480, + 0x0000001e, + 0x00000001, + 0x0001046a, + 0x0001046a, + 0x0001046a, + 0xaaaaaaaa, +}; + +static const uint32_t uve_deblocking_filter[] = { + 0x00000020, + 0x0000000e, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const uint32_t uve_quality_params[] = { + 0x00000014, + 0x0000000d, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const uint32_t uve_feedback_buffer[] = { + 0x0000001c, + 0x00000012, + 0x00000000, +}; + +static const uint32_t uve_feedback_buffer_additional[] = { + 0x00000108, + 0x00000014, + 0x00000001, + 0x00000010, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const uint32_t uve_nalu_buffer_1[] = { + 0x00000018, + 0x00000013, + 0x00000001, + 0x00000007, + 0x00000001, + 0x46011000, +}; + +static const uint32_t uve_nalu_buffer_2[] = { + 0x0000002c, + 0x00000013, + 0x00000002, + 0x0000001b, + 0x00000001, + 0x40010c01, + 0xffff0160, + 0x00000300, + 0xb0000003, + 0x00000300, + 0x962c0900, +}; + +static const uint32_t uve_nalu_buffer_3[] = { + 0x00000034, + 0x00000013, + 0x00000003, + 0x00000023, + 0x00000001, + 0x42010101, + 0x60000003, + 0x00b00000, + 0x03000003, + 0x0096a018, + 0x2020708f, + 0xcb924295, + 0x12e08000, +}; + +static const uint32_t uve_nalu_buffer_4[] = { + 0x0000001c, + 0x00000013, + 0x00000004, + 0x0000000b, + 0x00000001, + 0x4401e0f1, + 0x80992000, +}; + +static const uint32_t uve_slice_header[] = { + 0x000000c8, + 0x0000000b, + 0x28010000, + 0x40000000, + 0x60000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000002, + 0x00000010, + 0x00000003, + 0x00000000, + 0x00000002, + 0x00000002, + 0x00000004, + 0x00000000, + 0x00000001, + 0x00000000, + 0x00000002, + 0x00000003, + 0x00000005, + 0x00000000, + 0x00000002, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const uint32_t uve_encode_param[] = { + 0x000000a0, + 0x00000080, + 0x00000000, + 0x00000000, + 0xffffffff, + 0x00000001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const uint32_t uve_intra_refresh[] = { + 0x00000014, + 0x0000000f, + 0x00000000, + 0x00000000, + 0x00000001, +}; + +static const uint32_t uve_ctx_buffer[] = { + 0x00000000, + 0x00000000, + 0x000000a0, + 0x000000a0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const uint32_t uve_bitstream_buffer[] = { + 0x0000001c, + 0x00000011, +}; + +static const uint32_t uve_rc_per_pic[] = { + 0x00000024, + 0x0000000a, + 0x0000001a, + 0x00000000, + 0x00000033, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000001, +}; + +static const uint32_t uve_op_init[] = { + 0x00000008, + 0x08000001, +}; + +static const uint32_t uve_op_close[] = { + 0x00000008, + 0x08000002, +}; + +static const uint32_t uve_op_encode[] = { + 0x00000008, + 0x08000003, +}; + +static const uint32_t uve_op_init_rc[] = { + 0x00000008, + 0x08000004, +}; + +static const uint32_t uve_op_init_rc_vbv_level[] = { + 0x00000008, + 0x08000005, +}; + +static const uint32_t uve_op_speed_enc_mode[] = { + 0x00000008, + 0x08000006, +}; + +static const uint32_t uve_op_balance_enc_mode[] = { + 0x00000008, + 0x08000007, +}; + +static const uint32_t uve_op_quality_enc_mode[] = { + 0x00000008, + 0x08000008, +}; +#endif /*_uve_ib_h*/ -- cgit v1.2.3-54-g00ecf From 20138ea997e4e2eadd43846c114a7891688d653d Mon Sep 17 00:00:00 2001 From: Jan Vesely Date: Fri, 28 Jul 2017 10:23:22 -0400 Subject: drmsltest: Check expected neighbours Fixes: 7d8c9464081634f053e16e5eac9655a12fae1dc4 Signed-off-by: Jan Vesely Reviewed-by: Emil Velikov --- tests/drmsl.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/tests/drmsl.c b/tests/drmsl.c index d0ac0efa..d1b59a86 100644 --- a/tests/drmsl.c +++ b/tests/drmsl.c @@ -106,7 +106,9 @@ static double do_time(int size, int iter) return usec; } -static void print_neighbors(void *list, unsigned long key) +static void print_neighbors(void *list, unsigned long key, + unsigned long expected_prev, + unsigned long expected_next) { unsigned long prev_key = 0; unsigned long next_key = 0; @@ -119,6 +121,16 @@ static void print_neighbors(void *list, unsigned long key) &next_key, &next_value); printf("Neighbors of %5lu: %d %5lu %5lu\n", key, retval, prev_key, next_key); + if (prev_key != expected_prev) { + fprintf(stderr, "Unexpected neighbor: %5lu. Expected: %5lu\n", + prev_key, expected_prev); + exit(1); + } + if (next_key != expected_next) { + fprintf(stderr, "Unexpected neighbor: %5lu. Expected: %5lu\n", + next_key, expected_next); + exit(1); + } } int main(void) @@ -138,13 +150,13 @@ int main(void) print(list); printf("\n==============================\n\n"); - print_neighbors(list, 0); - print_neighbors(list, 50); - print_neighbors(list, 51); - print_neighbors(list, 123); - print_neighbors(list, 200); - print_neighbors(list, 213); - print_neighbors(list, 256); + print_neighbors(list, 0, 0, 50); + print_neighbors(list, 50, 0, 50); + print_neighbors(list, 51, 50, 123); + print_neighbors(list, 123, 50, 123); + print_neighbors(list, 200, 123, 213); + print_neighbors(list, 213, 123, 213); + print_neighbors(list, 256, 213, 256); printf("\n==============================\n\n"); drmSLDelete(list, 50); -- cgit v1.2.3-54-g00ecf From e5ce5c6807a85187dd9cede54e9144f3bcc3ee47 Mon Sep 17 00:00:00 2001 From: Chih-Wei Huang Date: Thu, 27 Jul 2017 16:20:51 +0800 Subject: android: add rules to build amdgpu.ids Signed-off-by: Chih-Wei Huang --- data/Android.mk | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 data/Android.mk diff --git a/data/Android.mk b/data/Android.mk new file mode 100644 index 00000000..3c1fd7c6 --- /dev/null +++ b/data/Android.mk @@ -0,0 +1,9 @@ +LOCAL_PATH := $(call my-dir) + +include $(CLEAR_VARS) +LOCAL_MODULE := amdgpu.ids +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_CLASS := ETC +LOCAL_MODULE_PATH := $(TARGET_OUT_ETC)/hwdata +LOCAL_SRC_FILES := $(LOCAL_MODULE) +include $(BUILD_PREBUILT) -- cgit v1.2.3-54-g00ecf From a0531e76f68e5f69cdc149d7cbff4ba299352dfe Mon Sep 17 00:00:00 2001 From: Chih-Wei Huang Date: Thu, 27 Jul 2017 16:20:52 +0800 Subject: android: amdgpu: fix build break Define two macros to avoid building errors. Fixes: 7e6bf88cac (amdgpu: move asic id table to a separate file) Signed-off-by: Chih-Wei Huang --- amdgpu/Android.mk | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/amdgpu/Android.mk b/amdgpu/Android.mk index bf0611ba..88d37651 100644 --- a/amdgpu/Android.mk +++ b/amdgpu/Android.mk @@ -10,5 +10,11 @@ LOCAL_SHARED_LIBRARIES := libdrm LOCAL_SRC_FILES := $(LIBDRM_AMDGPU_FILES) +LOCAL_CFLAGS := \ + -DAMDGPU_ASIC_ID_TABLE=\"/system/etc/hwdata/amdgpu.ids\" \ + -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' $(LIBDRM_TOP)/data/amdgpu.ids) + +LOCAL_REQUIRED_MODULES := amdgpu.ids + include $(LIBDRM_COMMON_MK) include $(BUILD_SHARED_LIBRARY) -- cgit v1.2.3-54-g00ecf From 99d3f8253cff617af4662c48ba737bf6e10e146e Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 21 Aug 2017 14:41:11 +0200 Subject: etnaviv: fix etna_bo_from_name Look up BOs from the name table using the name parameter instead of req.handle (which at this point is always zero). Signed-off-by: Philipp Zabel Reviewed-by: Eric Engestrom Reviewed-by: Christian Gmeiner Reviewed-by: Wladimir J. van der Laan Reviewed-by: Daniel Stone --- etnaviv/etnaviv_bo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/etnaviv/etnaviv_bo.c b/etnaviv/etnaviv_bo.c index 4ad0434e..4fe877f1 100644 --- a/etnaviv/etnaviv_bo.c +++ b/etnaviv/etnaviv_bo.c @@ -173,7 +173,7 @@ struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name) pthread_mutex_lock(&table_lock); /* check name table first, to see if bo is already open: */ - bo = lookup_bo(dev->name_table, req.handle); + bo = lookup_bo(dev->name_table, name); if (bo) goto out_unlock; -- cgit v1.2.3-54-g00ecf From f19dbb79fe54994ecd505ac67ad15d19f591933a Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Thu, 24 Aug 2017 12:31:30 +0100 Subject: configure.ac: Bump version to 2.4.83 --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 5a7b1f8a..f847a664 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.82], + [2.4.83], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 05a830d382382905d87b55af90aa109fb76e4c16 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 30 Aug 2017 14:00:18 -0400 Subject: tests/amdgpu: add missing header to SOURCES Fixes the tarball generation. fixes: 9d133dd08720d80dfc8ce098bf0972 (tests/amdgpu: add uvd encode unit tests) bug: https://bugs.freedesktop.org/show_bug.cgi?id=102391 Reviewed-by: Christian König Signed-off-by: Alex Deucher --- tests/amdgpu/Makefile.am | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index 13b3dc8e..9c02fd60 100644 --- a/tests/amdgpu/Makefile.am +++ b/tests/amdgpu/Makefile.am @@ -28,4 +28,5 @@ amdgpu_test_SOURCES = \ vce_ib.h \ frame.h \ uvd_enc_tests.c \ - vcn_tests.c + vcn_tests.c \ + uve_ib.h -- cgit v1.2.3-54-g00ecf From d55d0804f9e37637d7510f38f97e07a50c6b7baa Mon Sep 17 00:00:00 2001 From: Jan Vesely Date: Fri, 1 Sep 2017 14:49:19 -0400 Subject: amdgpu: Do not write beyond allocated memory when parsing ids Fixes crash when/usr/share/libdrm/amdgpu.ids contains ASIC_ID_TABLE_NUM_ENTRIES + 1 entries. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102432 Fixes: 7e6bf88cac315a9fa41818cf72a7b5d18a2cb1fc (amdgpu: move asic id table to a separate file) Signed-off-by: Jan Vesely Reviewed-by: Michel Dänzer --- amdgpu/amdgpu_asic_id.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c index 3a88896b..e8218974 100644 --- a/amdgpu/amdgpu_asic_id.c +++ b/amdgpu/amdgpu_asic_id.c @@ -186,19 +186,20 @@ int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) table_size++; } - /* end of table */ - id = asic_id_table + table_size; - memset(id, 0, sizeof(struct amdgpu_asic_id)); - if (table_size != table_max_size) { id = realloc(asic_id_table, (table_size + 1) * sizeof(struct amdgpu_asic_id)); - if (!id) + if (!id) { r = -ENOMEM; - else - asic_id_table = id; + goto free; + } + asic_id_table = id; } + /* end of table */ + id = asic_id_table + table_size; + memset(id, 0, sizeof(struct amdgpu_asic_id)); + free: free(line); -- cgit v1.2.3-54-g00ecf From 6dca9387d20204898f9e831d59b725d062513fd0 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 13 Sep 2017 16:08:19 +0200 Subject: etnaviv: prevent deadlock in error path If drmPrimeFDToHandle fails in etna_bo_from_dmabuf, the function must not return with the table_lock mutex held. Unlock the mutex in the error path. Based on ceb70a6b1015 ("freedreno: prevent deadlock in error path"). Signed-off-by: Philipp Zabel Reviewed-by: Eric Engestrom --- etnaviv/etnaviv_bo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/etnaviv/etnaviv_bo.c b/etnaviv/etnaviv_bo.c index 4fe877f1..78b9cd27 100644 --- a/etnaviv/etnaviv_bo.c +++ b/etnaviv/etnaviv_bo.c @@ -206,10 +206,15 @@ struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd) int ret, size; uint32_t handle; + /* take the lock before calling drmPrimeFDToHandle to avoid + * racing against etna_bo_del, which might invalidate the + * returned handle. + */ pthread_mutex_lock(&table_lock); ret = drmPrimeFDToHandle(dev->fd, fd, &handle); if (ret) { + pthread_mutex_unlock(&table_lock); return NULL; } -- cgit v1.2.3-54-g00ecf From 76418c244d4c52a8dd20809e3e8b4e70501fc76f Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Thu, 14 Sep 2017 10:56:01 +0100 Subject: freedreno/kgsl: fix pointer-to-int cast Fixes this warning: freedreno/kgsl/kgsl_ringbuffer.c: In function ‘kgsl_ringbuffer_flush’: freedreno/kgsl/kgsl_ringbuffer.c:149:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] req.timestamp = (uint32_t)kgsl_ring->bo->hostptr; ^ Signed-off-by: Eric Engestrom Reviewed-by: Rob Clark --- freedreno/kgsl/kgsl_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/freedreno/kgsl/kgsl_ringbuffer.c b/freedreno/kgsl/kgsl_ringbuffer.c index e4696b1b..f09c433b 100644 --- a/freedreno/kgsl/kgsl_ringbuffer.c +++ b/freedreno/kgsl/kgsl_ringbuffer.c @@ -146,7 +146,7 @@ static int kgsl_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_star ibdesc.gpuaddr = kgsl_ring->bo->gpuaddr; ibdesc.hostptr = kgsl_ring->bo->hostptr; ibdesc.sizedwords = 0x145; - req.timestamp = (uint32_t)kgsl_ring->bo->hostptr; + req.timestamp = (uintptr_t)kgsl_ring->bo->hostptr; } do { -- cgit v1.2.3-54-g00ecf From 7c71188610b4ceba0339c2bc884320bcb749adee Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Wed, 20 Sep 2017 12:11:03 -0700 Subject: intel: Change a KBL pci id to GT2 from GT1.5 See Mesa commit 9c588ff Cc: Matt Turner Cc: Rodrigo Vivi Signed-off-by: Anuj Phogat Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3ff59ada..d81b1646 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -202,7 +202,7 @@ #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 +#define PCI_CHIP_KABYLAKE_M_GT2 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B @@ -434,7 +434,6 @@ #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ @@ -446,6 +445,7 @@ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) -- cgit v1.2.3-54-g00ecf From 1dd84e01a972b1759839a7326009be24ab3e6de2 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Mon, 4 Sep 2017 21:05:26 +0200 Subject: amdgpu: print error messages when amdgpu_device_initialize is failing Reviewed-by: Alex Deucher --- amdgpu/amdgpu_device.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 9a238d97..2b31c45b 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -191,6 +191,8 @@ int amdgpu_device_initialize(int fd, fd_tab = util_hash_table_create(fd_hash, fd_compare); r = amdgpu_get_auth(fd, &flag_auth); if (r) { + fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n", + __func__, r); pthread_mutex_unlock(&fd_mutex); return r; } @@ -198,6 +200,8 @@ int amdgpu_device_initialize(int fd, if (dev) { r = amdgpu_get_auth(dev->fd, &flag_authexist); if (r) { + fprintf(stderr, "%s: amdgpu_get_auth (2) failed (%i)\n", + __func__, r); pthread_mutex_unlock(&fd_mutex); return r; } @@ -213,6 +217,7 @@ int amdgpu_device_initialize(int fd, dev = calloc(1, sizeof(struct amdgpu_device)); if (!dev) { + fprintf(stderr, "%s: calloc failed\n", __func__); pthread_mutex_unlock(&fd_mutex); return -ENOMEM; } @@ -248,16 +253,22 @@ int amdgpu_device_initialize(int fd, /* Check if acceleration is working. */ r = amdgpu_query_info(dev, AMDGPU_INFO_ACCEL_WORKING, 4, &accel_working); - if (r) + if (r) { + fprintf(stderr, "%s: amdgpu_query_info(ACCEL_WORKING) failed (%i)\n", + __func__, r); goto cleanup; + } if (!accel_working) { + fprintf(stderr, "%s: AMDGPU_INFO_ACCEL_WORKING = 0\n", __func__); r = -EBADF; goto cleanup; } r = amdgpu_query_gpu_info_init(dev); - if (r) + if (r) { + fprintf(stderr, "%s: amdgpu_query_gpu_info_init failed\n", __func__); goto cleanup; + } amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset, dev->dev_info.virtual_address_max, @@ -267,8 +278,10 @@ int amdgpu_device_initialize(int fd, start = amdgpu_vamgr_find_va(&dev->vamgr, max - dev->dev_info.virtual_address_offset, dev->dev_info.virtual_address_alignment, 0); - if (start > 0xffffffff) + if (start > 0xffffffff) { + fprintf(stderr, "%s: amdgpu_vamgr_find_va failed\n", __func__); goto free_va; /* shouldn't get here */ + } amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); -- cgit v1.2.3-54-g00ecf From 736ef0b61cab55378202c5f49d91799cc2b99091 Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 7 Sep 2017 10:16:01 +0200 Subject: amdgpu: make userptr unit test more interesting Do a fork() to force some MMU callbacks. Signed-off-by: Christian König Acked-by: Alex Deucher --- tests/amdgpu/basic_tests.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 80d15e77..18bcf919 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -31,6 +31,7 @@ #ifdef HAVE_ALLOCA_H # include #endif +#include #include "CUnit/Basic.h" @@ -1403,6 +1404,11 @@ static void amdgpu_userptr_test(void) while (j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; + if (!fork()) { + pm4[0] = 0x0; + exit(0); + } + amdgpu_test_exec_cs_helper(context_handle, AMDGPU_HW_IP_DMA, 0, i, pm4, @@ -1426,4 +1432,6 @@ static void amdgpu_userptr_test(void) r = amdgpu_cs_ctx_free(context_handle); CU_ASSERT_EQUAL(r, 0); + + wait(NULL); } -- cgit v1.2.3-54-g00ecf From 670db97dc39a7879f52bad230327edf4374b7516 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 2 Oct 2017 14:07:48 -0400 Subject: amdgpu: Add deadlock detection test suit. Adding initial tests for locks detection when SW scheduler FIFO is full. The test works by submitting a batch of identical commands which make the CP stall waiting for condition to become true. The condition is later satisfied form a helper thread. Other events that happen during this time might create deadlock situations. One such example is GPU reset triggered by this stall when amdgpu_lockup_timeout != 0. v2: Increase the delay from 2 to 100 ms. Comment out the compute test until it's working. Typos fix. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/Makefile.am | 6 +- tests/amdgpu/amdgpu_test.c | 6 ++ tests/amdgpu/amdgpu_test.h | 15 +++ tests/amdgpu/deadlock_tests.c | 245 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 270 insertions(+), 2 deletions(-) create mode 100644 tests/amdgpu/deadlock_tests.c diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index 9c02fd60..8700c4d4 100644 --- a/tests/amdgpu/Makefile.am +++ b/tests/amdgpu/Makefile.am @@ -1,7 +1,8 @@ AM_CFLAGS = \ -I $(top_srcdir)/include/drm \ -I $(top_srcdir)/amdgpu \ - -I $(top_srcdir) + -I $(top_srcdir) \ + -pthread LDADD = $(top_builddir)/libdrm.la \ $(top_builddir)/amdgpu/libdrm_amdgpu.la \ @@ -29,4 +30,5 @@ amdgpu_test_SOURCES = \ frame.h \ uvd_enc_tests.c \ vcn_tests.c \ - uve_ib.h + uve_ib.h \ + deadlock_tests.c diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index cd6b8262..99255038 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -97,6 +97,12 @@ static CU_SuiteInfo suites[] = { .pCleanupFunc = suite_uvd_enc_tests_clean, .pTests = uvd_enc_tests, }, + { + .pName = "Deadlock Tests", + .pInitFunc = suite_deadlock_tests_init, + .pCleanupFunc = suite_deadlock_tests_clean, + .pTests = deadlock_tests, + }, CU_SUITE_INFO_NULL, }; diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index d0b61baa..ece93f4c 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -134,6 +134,21 @@ int suite_uvd_enc_tests_clean(); */ extern CU_TestInfo uvd_enc_tests[]; +/** + * Initialize deadlock test suite + */ +int suite_deadlock_tests_init(); + +/** + * Deinitialize deadlock test suite + */ +int suite_deadlock_tests_clean(); + +/** + * Tests in uvd enc test suite + */ +extern CU_TestInfo deadlock_tests[]; + /** * Helper functions */ diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c new file mode 100644 index 00000000..e23d903f --- /dev/null +++ b/tests/amdgpu/deadlock_tests.c @@ -0,0 +1,245 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#ifdef HAVE_ALLOCA_H +# include +#endif + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" + +#include + + +/* + * This defines the delay in MS after which memory location designated for + * compression against reference value is written to, unblocking command + * processor + */ +#define WRITE_MEM_ADDRESS_DELAY_MS 100 + +#define PACKET_TYPE3 3 + +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +#define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) + /* 0 - wait_reg_mem + * 1 - wr_wait_wr_reg + */ +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + /* 0 - me + * 1 - pfp + */ + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; + +static pthread_t stress_thread; +static uint32_t *ptr; + +static void amdgpu_deadlock_helper(unsigned ip_type); +static void amdgpu_deadlock_gfx(void); +static void amdgpu_deadlock_compute(void); + +int suite_deadlock_tests_init(void) +{ + struct amdgpu_gpu_info gpu_info = {0}; + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + + if (r) { + if ((r == -EACCES) && (errno == EACCES)) + printf("\n\nError:%s. " + "Hint:Try to run this test program as root.", + strerror(errno)); + return CUE_SINIT_FAILED; + } + + return CUE_SUCCESS; +} + +int suite_deadlock_tests_clean(void) +{ + int r = amdgpu_device_deinitialize(device_handle); + + if (r == 0) + return CUE_SUCCESS; + else + return CUE_SCLEAN_FAILED; +} + + +CU_TestInfo deadlock_tests[] = { + { "gfx ring block test", amdgpu_deadlock_gfx }, + + /* + * BUG: Compute ring stalls and never recovers when the address is + * written after the command already submitted + */ + /* { "compute ring block test", amdgpu_deadlock_compute }, */ + + CU_TEST_INFO_NULL, +}; + +static void *write_mem_address(void *data) +{ + int i; + + /* useconds_t range is [0, 1,000,000] so use loop for waits > 1s */ + for (i = 0; i < WRITE_MEM_ADDRESS_DELAY_MS; i++) + usleep(1000); + + ptr[256] = 0x1; + + return 0; +} + +static void amdgpu_deadlock_gfx(void) +{ + amdgpu_deadlock_helper(AMDGPU_HW_IP_GFX); +} + +static void amdgpu_deadlock_compute(void) +{ + amdgpu_deadlock_helper(AMDGPU_HW_IP_COMPUTE); +} + +static void amdgpu_deadlock_helper(unsigned ip_type) +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle ib_result_handle; + void *ib_result_cpu; + uint64_t ib_result_mc_address; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + struct amdgpu_cs_fence fence_status; + uint32_t expired; + int i, r, instance; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle; + + r = pthread_create(&stress_thread, NULL, write_mem_address, NULL); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, + &bo_list); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu; + + ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5); + ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ + WAIT_REG_MEM_FUNCTION(4) | /* != */ + WAIT_REG_MEM_ENGINE(0)); /* me */ + ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc; + ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff; + ptr[4] = 0x00000000; /* reference value */ + ptr[5] = 0xffffffff; /* and mask */ + ptr[6] = 0x00000004; /* poll interval */ + + for (i = 7; i < 16; ++i) + ptr[i] = 0xffff1000; + + + ptr[256] = 0x0; /* the memory we wait on to change */ + + + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address; + ib_info.size = 16; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = ip_type; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + ibs_request.fence_info.handle = NULL; + + for (i = 0; i < 200; i++) { + r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + + } + + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); + fence_status.context = context_handle; + fence_status.ip_type = ip_type; + fence_status.ip_instance = 0; + fence_status.ring = 0; + fence_status.fence = ibs_request.seq_no; + + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE,0, &expired); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); + + pthread_join(stress_thread, NULL); +} -- cgit v1.2.3-54-g00ecf From 657b09438bf4978c9597368165c56227013625e9 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 5 Oct 2017 10:56:51 -0400 Subject: tests/amdgpu: add new uvd enc support check Query hardware IP information to find out if there are uvd encode rings ready for use in kernel driver. Signed-off-by: James Zhu Reviewed-by: Leo Liu --- tests/amdgpu/uvd_enc_tests.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 6c19f7b6..75181035 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -79,6 +79,8 @@ static void amdgpu_cs_uvd_enc_session_init(void); static void amdgpu_cs_uvd_enc_encode(void); static void amdgpu_cs_uvd_enc_destroy(void); +static bool uvd_enc_support(void); + CU_TestInfo uvd_enc_tests[] = { { "UVD ENC create", amdgpu_cs_uvd_enc_create }, { "UVD ENC session init", amdgpu_cs_uvd_enc_session_init }, @@ -98,7 +100,7 @@ int suite_uvd_enc_tests_init(void) family_id = device_handle->info.family_id; - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { + if (!uvd_enc_support()) { printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); return CUE_SUCCESS; } @@ -121,7 +123,7 @@ int suite_uvd_enc_tests_clean(void) { int r; - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) { + if (!uvd_enc_support()) { r = amdgpu_device_deinitialize(device_handle); if (r) @@ -238,11 +240,24 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); } +static bool uvd_enc_support(void) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info); + + if (r) + return false; + else + return (info.available_rings?true:false); +} + static void amdgpu_cs_uvd_enc_create(void) { int len, r; - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return; enc.width = 160; @@ -281,7 +296,7 @@ static void amdgpu_cs_uvd_enc_session_init(void) { int len, r; - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return; len = 0; @@ -339,7 +354,7 @@ static void amdgpu_cs_uvd_enc_encode(void) vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; cpb_size = vbuf_size * 10; - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return; num_resources = 0; @@ -472,7 +487,7 @@ static void amdgpu_cs_uvd_enc_destroy(void) struct amdgpu_uvd_enc_bo sw_ctx; int len, r; - if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) + if (!uvd_enc_support()) return; num_resources = 0; -- cgit v1.2.3-54-g00ecf From 2ecafcae8a215d9994fb26a122d97bcb5437c5e8 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 5 Oct 2017 10:57:42 -0400 Subject: tests/amdgpu: fix uvd enc data corruption issue In uvd encode parameter package, parameters input_pic_luma_pitch and input_pic_chroma_pitch should be picture width align with hardware alignment. The hardware alignment is 16 for amdgpu family earlier than AMDGPU_FAMILY_AI, and 256 for later than and including AMDGPU_FAMILY_AI. Signed-off-by: James Zhu Reviewed-by: Leo Liu --- tests/amdgpu/uvd_enc_tests.c | 4 +++- tests/amdgpu/uve_ib.h | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 75181035..bbda1312 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -272,7 +272,7 @@ static void amdgpu_cs_uvd_enc_create(void) static void check_result(struct amdgpu_uvd_enc *enc) { uint64_t sum; - uint32_t s = 26382; + uint32_t s = 175602; uint32_t *ptr, size; int i, j, r; @@ -463,6 +463,8 @@ static void amdgpu_cs_uvd_enc_encode(void) ib_cpu[len++] = chroma_offset >> 32; ib_cpu[len++] = chroma_offset; memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); + ib_cpu[len] = ALIGN(enc.width, align); + ib_cpu[len + 1] = ALIGN(enc.width, align); len += sizeof(uve_encode_param) / 4; memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode)); diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h index 9abd4066..cb72be22 100644 --- a/tests/amdgpu/uve_ib.h +++ b/tests/amdgpu/uve_ib.h @@ -297,8 +297,8 @@ static const uint32_t uve_slice_header[] = { }; static const uint32_t uve_encode_param[] = { - 0x000000a0, - 0x00000080, + 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xffffffff, -- cgit v1.2.3-54-g00ecf From 011fd913b445b5e17148c37d169396c39eced3df Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 15 Sep 2017 08:45:59 -0500 Subject: Android: move libraries to /vendor As part of Treble project in Android O, all the device specific files have to be located in a separate vendor partition. This is done by setting LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not break existing platforms without a vendor partition as it will just move files to /system/vendor. Signed-off-by: Rob Herring --- Android.common.mk | 2 ++ amdgpu/Android.mk | 2 +- data/Android.mk | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Android.common.mk b/Android.common.mk index b45ca10f..d487acb9 100644 --- a/Android.common.mk +++ b/Android.common.mk @@ -13,3 +13,5 @@ LOCAL_CFLAGS += \ # Quiet down the build system and remove any .h files from the sources LOCAL_SRC_FILES := $(patsubst %.h, , $(LOCAL_SRC_FILES)) LOCAL_EXPORT_C_INCLUDE_DIRS += $(LOCAL_PATH) + +LOCAL_PROPRIETARY_MODULE := true diff --git a/amdgpu/Android.mk b/amdgpu/Android.mk index 88d37651..ce273019 100644 --- a/amdgpu/Android.mk +++ b/amdgpu/Android.mk @@ -11,7 +11,7 @@ LOCAL_SHARED_LIBRARIES := libdrm LOCAL_SRC_FILES := $(LIBDRM_AMDGPU_FILES) LOCAL_CFLAGS := \ - -DAMDGPU_ASIC_ID_TABLE=\"/system/etc/hwdata/amdgpu.ids\" \ + -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\" \ -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' $(LIBDRM_TOP)/data/amdgpu.ids) LOCAL_REQUIRED_MODULES := amdgpu.ids diff --git a/data/Android.mk b/data/Android.mk index 3c1fd7c6..62013f0c 100644 --- a/data/Android.mk +++ b/data/Android.mk @@ -4,6 +4,7 @@ include $(CLEAR_VARS) LOCAL_MODULE := amdgpu.ids LOCAL_MODULE_TAGS := optional LOCAL_MODULE_CLASS := ETC -LOCAL_MODULE_PATH := $(TARGET_OUT_ETC)/hwdata +LOCAL_PROPRIETARY_MODULE := true +LOCAL_MODULE_RELATIVE_PATH := hwdata LOCAL_SRC_FILES := $(LOCAL_MODULE) include $(BUILD_PREBUILT) -- cgit v1.2.3-54-g00ecf From 965133914b14f571b91109814c393b62f7bc588a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 6 Oct 2017 16:18:57 -0500 Subject: headers: sync DRM_MODE_ROTATE/REFLECT defines from kernel v4.14-rc1 Add the new DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* defines from v4.14-rc1 kernel. Reviewed-by: Thierry Reding Reviewed-by: Robert Foss Signed-off-by: Rob Herring --- include/drm/drm_mode.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index 08077978..e01f129c 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -119,6 +119,53 @@ extern "C" { #define DRM_MODE_LINK_STATUS_GOOD 0 #define DRM_MODE_LINK_STATUS_BAD 1 +/* + * DRM_MODE_ROTATE_ + * + * Signals that a drm plane is been rotated degrees in counter + * clockwise direction. + * + * This define is provided as a convenience, looking up the property id + * using the name->prop id lookup is the preferred method. + */ +#define DRM_MODE_ROTATE_0 (1<<0) +#define DRM_MODE_ROTATE_90 (1<<1) +#define DRM_MODE_ROTATE_180 (1<<2) +#define DRM_MODE_ROTATE_270 (1<<3) + +/* + * DRM_MODE_ROTATE_MASK + * + * Bitmask used to look for drm plane rotations. + */ +#define DRM_MODE_ROTATE_MASK (\ + DRM_MODE_ROTATE_0 | \ + DRM_MODE_ROTATE_90 | \ + DRM_MODE_ROTATE_180 | \ + DRM_MODE_ROTATE_270) + +/* + * DRM_MODE_REFLECT_ + * + * Signals that the contents of a drm plane is reflected in the axis, + * in the same way as mirroring. + * + * This define is provided as a convenience, looking up the property id + * using the name->prop id lookup is the preferred method. + */ +#define DRM_MODE_REFLECT_X (1<<4) +#define DRM_MODE_REFLECT_Y (1<<5) + +/* + * DRM_MODE_REFLECT_MASK + * + * Bitmask used to look for drm plane reflections. + */ +#define DRM_MODE_REFLECT_MASK (\ + DRM_MODE_REFLECT_X | \ + DRM_MODE_REFLECT_Y) + + struct drm_mode_modeinfo { __u32 clock; __u16 hdisplay; -- cgit v1.2.3-54-g00ecf From d27fd2d02300fdc107c9cc54d57989b8a29efd9f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 11 Oct 2017 10:41:25 +1000 Subject: headers: sync syncobj ioctl defines. This syncs the drm.h header with my drm-next branch as of bb7a9c8d712f37385a706a594d6edf6e6d2669d0 Signed-off-by: Dave Airlie --- include/drm/drm.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/drm/drm.h b/include/drm/drm.h index bf3674ae..4737261a 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -694,6 +694,7 @@ struct drm_prime_handle { struct drm_syncobj_create { __u32 handle; +#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) __u32 flags; }; @@ -712,6 +713,24 @@ struct drm_syncobj_handle { __u32 pad; }; +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) +struct drm_syncobj_wait { + __u64 handles; + /* absolute timeout */ + __s64 timeout_nsec; + __u32 count_handles; + __u32 flags; + __u32 first_signaled; /* only valid when not waiting all */ + __u32 pad; +}; + +struct drm_syncobj_array { + __u64 handles; + __u32 count_handles; + __u32 pad; +}; + #if defined(__cplusplus) } #endif @@ -834,6 +853,9 @@ extern "C" { #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) +#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) +#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) +#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) /** * Device specific ioctls should only be in their respective headers -- cgit v1.2.3-54-g00ecf From ad4df736a9f8098cd47008c72948ceff9e9f9dac Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 12 Oct 2017 20:31:44 +0200 Subject: include: sync drm.h and amdgpu_drm.h with airlied/drm-next --- include/drm/amdgpu_drm.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index d9aa4a33..4c6e8c48 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -52,6 +52,7 @@ extern "C" { #define DRM_AMDGPU_GEM_USERPTR 0x11 #define DRM_AMDGPU_WAIT_FENCES 0x12 #define DRM_AMDGPU_VM 0x13 +#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -67,6 +68,7 @@ extern "C" { #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -87,6 +89,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) /* Flag that allocating the BO should use linear VRAM */ #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) +/* Flag that BO is always valid in this VM */ +#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) struct drm_amdgpu_gem_create_in { /** the requested memory size */ @@ -513,6 +517,20 @@ struct drm_amdgpu_cs_chunk_sem { __u32 handle; }; +#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 +#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 +#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 + +union drm_amdgpu_fence_to_handle { + struct { + struct drm_amdgpu_fence fence; + __u32 what; + } in; + struct { + __u32 handle; + } out; +}; + struct drm_amdgpu_cs_chunk_data { union { struct drm_amdgpu_cs_chunk_ib ib_data; @@ -764,6 +782,7 @@ struct drm_amdgpu_info_device { __u64 max_memory_clock; /* cu information */ __u32 cu_active_number; + /* NOTE: cu_ao_mask is INVALID, DON'T use it */ __u32 cu_ao_mask; __u32 cu_bitmap[4][4]; /** Render backend pipe mask. One render backend is CB+DB. */ @@ -818,6 +837,8 @@ struct drm_amdgpu_info_device { /* max gs wavefront per vgt*/ __u32 max_gs_waves_per_vgt; __u32 _pad1; + /* always on cu bitmap */ + __u32 cu_ao_bitmap[4][4]; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3-54-g00ecf From b6e24501a1f8c58501fdfa39b435e440ee667feb Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Mon, 11 Sep 2017 21:12:12 +0200 Subject: amdgpu: add sync_file import and export functions v2: update amdgpu-symbol-check Reviewed-by: Chunming Zhou --- amdgpu/amdgpu-symbol-check | 2 ++ amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++ amdgpu/amdgpu_cs.c | 20 ++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index c5b85b52..bc9ed3f9 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -40,6 +40,8 @@ amdgpu_cs_query_reset_state amdgpu_cs_signal_semaphore amdgpu_cs_submit amdgpu_cs_submit_raw +amdgpu_cs_syncobj_export_sync_file +amdgpu_cs_syncobj_import_sync_file amdgpu_cs_wait_fences amdgpu_cs_wait_semaphore amdgpu_device_deinitialize diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 238b1aaa..b44b9b64 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1382,6 +1382,36 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, int shared_fd, uint32_t *syncobj); +/** + * Export kernel sync object to a sync_file. + * + * \param dev - \c [in] device handle + * \param syncobj - \c [in] sync object handle + * \param sync_file_fd - \c [out] sync_file file descriptor. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + */ +int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, + uint32_t syncobj, + int *sync_file_fd); + +/** + * Import kernel sync object from a sync_file. + * + * \param dev - \c [in] device handle + * \param syncobj - \c [in] sync object handle + * \param sync_file_fd - \c [in] sync_file file descriptor. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + */ +int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, + uint32_t syncobj, + int sync_file_fd); + /** * Submit raw command submission to kernel * diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index dfba8754..4a055366 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -635,6 +635,26 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, return drmSyncobjFDToHandle(dev->fd, shared_fd, handle); } +int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, + uint32_t syncobj, + int *sync_file_fd) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd); +} + +int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, + uint32_t syncobj, + int sync_file_fd) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd); +} + int amdgpu_cs_submit_raw(amdgpu_device_handle dev, amdgpu_context_handle context, amdgpu_bo_list_handle bo_list_handle, -- cgit v1.2.3-54-g00ecf From 2048a9e7278d64954080077fb29d603fbb611873 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Mon, 11 Sep 2017 21:57:32 +0200 Subject: drm: add drmSyncobjWait wrapper Reviewed-by: Chunming Zhou --- xf86drm.c | 22 ++++++++++++++++++++++ xf86drm.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/xf86drm.c b/xf86drm.c index 6ea01129..8a327170 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -4225,3 +4225,25 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd) *sync_file_fd = args.fd; return 0; } + +int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, + int64_t timeout_nsec, unsigned flags, + uint32_t *first_signaled) +{ + struct drm_syncobj_wait args; + int ret; + + memclear(args); + args.handles = (intptr_t)handles; + args.timeout_nsec = timeout_nsec; + args.count_handles = num_handles; + args.flags = flags; + + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args); + if (ret < 0) + return ret; + + if (first_signaled) + *first_signaled = args.first_signaled; + return ret; +} diff --git a/xf86drm.h b/xf86drm.h index 2855a3ee..ea650eff 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -860,6 +860,9 @@ extern int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle); extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd); extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd); +extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, + int64_t timeout_nsec, unsigned flags, + uint32_t *first_signaled); #if defined(__cplusplus) } -- cgit v1.2.3-54-g00ecf From 59aa57b363ba8de550aced1d397c54fd9e5e213c Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Mon, 11 Sep 2017 21:58:03 +0200 Subject: amdgpu: add amdgpu_cs_syncobj_wait v2: update amdgpu-symbol-check Reviewed-by: Chunming Zhou --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 20 ++++++++++++++++++++ amdgpu/amdgpu_cs.c | 12 ++++++++++++ 3 files changed, 33 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index bc9ed3f9..7ecfc982 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -42,6 +42,7 @@ amdgpu_cs_submit amdgpu_cs_submit_raw amdgpu_cs_syncobj_export_sync_file amdgpu_cs_syncobj_import_sync_file +amdgpu_cs_syncobj_wait amdgpu_cs_wait_fences amdgpu_cs_wait_semaphore amdgpu_device_deinitialize diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index b44b9b64..979acfc8 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1353,6 +1353,26 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, uint32_t syncobj); +/** + * Wait for one or all sync objects to signal. + * + * \param dev - \c [in] self-explanatory + * \param handles - \c [in] array of sync object handles + * \param num_handles - \c [in] self-explanatory + * \param timeout_nsec - \c [in] self-explanatory + * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* + * \param first_signaled - \c [in] self-explanatory + * + * \return 0 on success\n + * -ETIME - Timeout + * <0 - Negative POSIX Error code + * + */ +int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, + uint32_t *handles, unsigned num_handles, + int64_t timeout_nsec, unsigned flags, + uint32_t *first_signaled); + /** * Export kernel sync object to shareable fd. * diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 4a055366..2cde7bff 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -615,6 +615,18 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, return drmSyncobjDestroy(dev->fd, handle); } +int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, + uint32_t *handles, unsigned num_handles, + int64_t timeout_nsec, unsigned flags, + uint32_t *first_signaled) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjWait(dev->fd, handles, num_handles, timeout_nsec, + flags, first_signaled); +} + int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, uint32_t handle, int *shared_fd) -- cgit v1.2.3-54-g00ecf From c74d4614048f65b412caa572c900d15adba38ce3 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Fri, 8 Sep 2017 16:05:54 +0200 Subject: amdgpu: add amdgpu_cs_fence_to_handle v2: update amdgpu-symbol-check Reviewed-by: Chunming Zhou --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 14 ++++++++++++++ amdgpu/amdgpu_cs.c | 22 ++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 7ecfc982..d9f89ef3 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -34,6 +34,7 @@ amdgpu_cs_ctx_free amdgpu_cs_destroy_semaphore amdgpu_cs_destroy_syncobj amdgpu_cs_export_syncobj +amdgpu_cs_fence_to_handle amdgpu_cs_import_syncobj amdgpu_cs_query_fence_status amdgpu_cs_query_reset_state diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 979acfc8..23cde108 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1432,6 +1432,20 @@ int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, uint32_t syncobj, int sync_file_fd); +/** + * Export an amdgpu fence as a handle (syncobj or fd). + * + * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD} + * \param out_handle returned handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + */ +int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, + struct amdgpu_cs_fence *fence, + uint32_t what, + uint32_t *out_handle); + /** * Submit raw command submission to kernel * diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 2cde7bff..9577d5c9 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -713,3 +713,25 @@ void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, dep->ctx_id = fence->context->id; dep->handle = fence->fence; } + +int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, + struct amdgpu_cs_fence *fence, + uint32_t what, + uint32_t *out_handle) +{ + union drm_amdgpu_fence_to_handle fth = {0}; + int r; + + fth.in.fence.ctx_id = fence->context->id; + fth.in.fence.ip_type = fence->ip_type; + fth.in.fence.ip_instance = fence->ip_instance; + fth.in.fence.ring = fence->ring; + fth.in.fence.seq_no = fence->fence; + fth.in.what = what; + + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE, + &fth, sizeof(fth)); + if (r == 0) + *out_handle = fth.out.handle; + return r; +} -- cgit v1.2.3-54-g00ecf From 290d29d9794813a2fe0578dbb905ad09bc810516 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 12 Oct 2017 20:48:54 +0200 Subject: configure.ac: bump version to 2.4.84 --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index f847a664..ccb910a2 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.83], + [2.4.84], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 511c71c868a7b0fac23e1387290554fee1a85434 Mon Sep 17 00:00:00 2001 From: Kristian H. Kristensen Date: Thu, 28 Sep 2017 16:02:09 -0700 Subject: modetest: Decode IN_FORMATS plane blob property This teaches modetest about the new IN_FORMATS blob and decodes the blob to show supported formats and modifiers. Signed-off-by: Kristian H. Kristensen --- tests/modetest/modetest.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index b8891ff5..8ad4766f 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -251,6 +251,89 @@ static void dump_blob(struct device *dev, uint32_t blob_id) drmModeFreePropertyBlob(blob); } +static const char *modifier_to_string(uint64_t modifier) +{ + switch (modifier) { + case DRM_FORMAT_MOD_INVALID: + return "INVALID"; + case DRM_FORMAT_MOD_LINEAR: + return "LINEAR"; + case I915_FORMAT_MOD_X_TILED: + return "X_TILED"; + case I915_FORMAT_MOD_Y_TILED: + return "Y_TILED"; + case I915_FORMAT_MOD_Yf_TILED: + return "Yf_TILED"; + case I915_FORMAT_MOD_Y_TILED_CCS: + return "Y_TILED_CCS"; + case I915_FORMAT_MOD_Yf_TILED_CCS: + return "Yf_TILED_CCS"; + case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: + return "SAMSUNG_64_32_TILE"; + case DRM_FORMAT_MOD_VIVANTE_TILED: + return "VIVANTE_TILED"; + case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED: + return "VIVANTE_SUPER_TILED"; + case DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED: + return "VIVANTE_SPLIT_TILED"; + case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED: + return "VIVANTE_SPLIT_SUPER_TILED"; + case NV_FORMAT_MOD_TEGRA_TILED: + return "MOD_TEGRA_TILED"; + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): + return "MOD_TEGRA_16BX2_BLOCK(0)"; + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(1): + return "MOD_TEGRA_16BX2_BLOCK(1)"; + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(2): + return "MOD_TEGRA_16BX2_BLOCK(2)"; + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(3): + return "MOD_TEGRA_16BX2_BLOCK(3)"; + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(4): + return "MOD_TEGRA_16BX2_BLOCK(4)"; + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(5): + return "MOD_TEGRA_16BX2_BLOCK(5)"; + case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: + return "MOD_BROADCOM_VC4_T_TILED"; + default: + return "(UNKNOWN MODIFIER)"; + } +} + +static void dump_in_formats(struct device *dev, uint32_t blob_id) +{ + uint32_t i, j; + drmModePropertyBlobPtr blob; + struct drm_format_modifier_blob *header; + uint32_t *formats; + struct drm_format_modifier *modifiers; + + printf("\t\tin_formats blob decoded:\n"); + blob = drmModeGetPropertyBlob(dev->fd, blob_id); + if (!blob) { + printf("\n"); + return; + } + + header = blob->data; + formats = (uint32_t *) ((char *) header + header->formats_offset); + modifiers = (struct drm_format_modifier *) + ((char *) header + header->modifiers_offset); + + for (i = 0; i < header->count_formats; i++) { + printf("\t\t\t"); + dump_fourcc(formats[i]); + printf(": "); + for (j = 0; j < header->count_modifiers; j++) { + uint64_t mask = 1ULL << i; + if (modifiers[j].formats & mask) + printf(" %s", modifier_to_string(modifiers[j].modifier)); + } + printf("\n"); + } + + drmModeFreePropertyBlob(blob); +} + static void dump_prop(struct device *dev, drmModePropertyPtr prop, uint32_t prop_id, uint64_t value) { @@ -328,6 +411,9 @@ static void dump_prop(struct device *dev, drmModePropertyPtr prop, printf(" %"PRId64"\n", value); else printf(" %"PRIu64"\n", value); + + if (strcmp(prop->name, "IN_FORMATS") == 0) + dump_in_formats(dev, value); } static void dump_connectors(struct device *dev) -- cgit v1.2.3-54-g00ecf From ba68d7bf600125f2755a5b3d6b1a17e8a130ba36 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 11 Oct 2017 17:58:11 +0300 Subject: modetest: Allow full testing of primary planes Allow the user to override the default configuration set by setcrtc for the primary plane. On some hardware primary planes can be freely positioned/sized, and it'd be nice if we can actually test that feature. Signed-off-by: Ville Syrjälä --- tests/modetest/modetest.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index 8ad4766f..62d93327 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -1091,7 +1091,8 @@ static int set_plane(struct device *dev, struct plane_arg *p) if (!format_support(ovr, p->fourcc)) continue; - if ((ovr->possible_crtcs & (1 << pipe)) && !ovr->crtc_id) { + if ((ovr->possible_crtcs & (1 << pipe)) && + (ovr->crtc_id == 0 || ovr->crtc_id == p->crtc_id)) { plane_id = ovr->plane_id; break; } -- cgit v1.2.3-54-g00ecf From bcae7226a1c36bee22ad747dc12960e52a706cfa Mon Sep 17 00:00:00 2001 From: Andres Rodriguez Date: Fri, 20 Oct 2017 10:57:58 -0400 Subject: headers: Sync amdgpu_drm.h with drm-next Generated using make headers_install from: airlied/drm-next 282dc83 Merge tag 'drm-intel-next-2017-10-12' ... Signed-off-by: Andres Rodriguez Acked-by: Dave Airlie Acked-by: Bas Nieuwenhuizen --- include/drm/amdgpu_drm.h | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 4c6e8c48..ff018182 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -53,6 +53,7 @@ extern "C" { #define DRM_AMDGPU_WAIT_FENCES 0x12 #define DRM_AMDGPU_VM 0x13 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 +#define DRM_AMDGPU_SCHED 0x15 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -69,6 +70,7 @@ extern "C" { #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) +#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -91,6 +93,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) /* Flag that BO is always valid in this VM */ #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) +/* Flag that BO sharing will be explicitly synchronized */ +#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) struct drm_amdgpu_gem_create_in { /** the requested memory size */ @@ -166,13 +170,22 @@ union drm_amdgpu_bo_list { /* unknown cause */ #define AMDGPU_CTX_UNKNOWN_RESET 3 +/* Context priority level */ +#define AMDGPU_CTX_PRIORITY_UNSET -2048 +#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 +#define AMDGPU_CTX_PRIORITY_LOW -512 +#define AMDGPU_CTX_PRIORITY_NORMAL 0 +/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ +#define AMDGPU_CTX_PRIORITY_HIGH 512 +#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 + struct drm_amdgpu_ctx_in { /** AMDGPU_CTX_OP_* */ __u32 op; /** For future use, no flags defined so far */ __u32 flags; __u32 ctx_id; - __u32 _pad; + __s32 priority; }; union drm_amdgpu_ctx_out { @@ -216,6 +229,21 @@ union drm_amdgpu_vm { struct drm_amdgpu_vm_out out; }; +/* sched ioctl */ +#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 + +struct drm_amdgpu_sched_in { + /* AMDGPU_SCHED_OP_* */ + __u32 op; + __u32 fd; + __s32 priority; + __u32 flags; +}; + +union drm_amdgpu_sched { + struct drm_amdgpu_sched_in in; +}; + /* * This is not a reliable API and you should expect it to fail for any * number of reasons and have fallback path that do not use userptr to @@ -629,6 +657,7 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 /* Number of VRAM page faults on CPU access. */ #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E +#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -- cgit v1.2.3-54-g00ecf From 35bc82cee9aab62d556e2ea6dfe29f71ce13dcb3 Mon Sep 17 00:00:00 2001 From: Andres Rodriguez Date: Fri, 20 Oct 2017 10:57:59 -0400 Subject: amdgpu: implement context priority for amdgpu_cs_ctx_create2 v3 Add a new context creation function that allows specifying the context priority. A high priority context has the potential of starving lower priority contexts. The current kernel driver implementation allows only apps that hold CAP_SYS_NICE or DRM_MASTER to acquire a priority above AMDGPU_CTX_PRIORITY_NORMAL. v2: corresponding changes for kernel patch v2 v3: Fixed 'make check' symbol error Signed-off-by: Andres Rodriguez Acked-by: Dave Airlie Reviewed-by: Bas Nieuwenhuizen --- amdgpu/amdgpu-symbol-check | 1 + amdgpu/amdgpu.h | 17 +++++++++++++++-- amdgpu/amdgpu_cs.c | 17 +++++++++++++---- 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index d9f89ef3..095c3a08 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -30,6 +30,7 @@ amdgpu_cs_chunk_fence_to_dep amdgpu_cs_create_semaphore amdgpu_cs_create_syncobj amdgpu_cs_ctx_create +amdgpu_cs_ctx_create2 amdgpu_cs_ctx_free amdgpu_cs_destroy_semaphore amdgpu_cs_destroy_syncobj diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 23cde108..ecc975f1 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -798,8 +798,9 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, * context will always be executed in order (first come, first serve). * * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() - * \param context - \c [out] GPU Context handle + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* + * \param context - \c [out] GPU Context handle * * \return 0 on success\n * <0 - Negative POSIX Error code @@ -807,6 +808,18 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, * \sa amdgpu_cs_ctx_free() * */ +int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, + uint32_t priority, + amdgpu_context_handle *context); +/** + * Create GPU execution Context + * + * Refer to amdgpu_cs_ctx_create2 for full documentation. This call + * is missing the priority parameter. + * + * \sa amdgpu_cs_ctx_create2() + * +*/ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, amdgpu_context_handle *context); diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 9577d5c9..b9fc01e7 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -46,13 +46,14 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem); /** * Create command submission context * - * \param dev - \c [in] amdgpu device handle - * \param context - \c [out] amdgpu context handle + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* + * \param context - \c [out] GPU Context handle * * \return 0 on success otherwise POSIX Error code */ -int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - amdgpu_context_handle *context) +int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, uint32_t priority, + amdgpu_context_handle *context) { struct amdgpu_context *gpu_context; union drm_amdgpu_ctx args; @@ -75,6 +76,8 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_CTX_OP_ALLOC_CTX; + args.in.priority = priority; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args)); if (r) goto error; @@ -94,6 +97,12 @@ error: return r; } +int amdgpu_cs_ctx_create(amdgpu_device_handle dev, + amdgpu_context_handle *context) +{ + return amdgpu_cs_ctx_create2(dev, AMDGPU_CTX_PRIORITY_NORMAL, context); +} + /** * Release command submission context * -- cgit v1.2.3-54-g00ecf From 09be54122fbd145d23751eddf7be5b220774a117 Mon Sep 17 00:00:00 2001 From: Tobias Jakobi Date: Tue, 10 Oct 2017 12:12:52 +0200 Subject: Add const qualifier to arguments of drmModeAddFB2() Both drmModeAddFB2() and drmModeAddFB2WithModifiers() have some arguments that are just pointers to uint32_t in disguise. These are not modified (just copied) in the function, so we can add a const qualifier here. Signed-off-by: Tobias Jakobi Reviewed-by: Eric Engestrom --- xf86drmMode.c | 10 +++++----- xf86drmMode.h | 11 ++++++----- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/xf86drmMode.c b/xf86drmMode.c index d3bc20ea..2b3887b3 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -271,9 +271,9 @@ int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth, } int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height, - uint32_t pixel_format, uint32_t bo_handles[4], - uint32_t pitches[4], uint32_t offsets[4], - uint64_t modifier[4], uint32_t *buf_id, uint32_t flags) + uint32_t pixel_format, const uint32_t bo_handles[4], + const uint32_t pitches[4], const uint32_t offsets[4], + const uint64_t modifier[4], uint32_t *buf_id, uint32_t flags) { struct drm_mode_fb_cmd2 f; int ret; @@ -297,8 +297,8 @@ int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height, } int drmModeAddFB2(int fd, uint32_t width, uint32_t height, - uint32_t pixel_format, uint32_t bo_handles[4], - uint32_t pitches[4], uint32_t offsets[4], + uint32_t pixel_format, const uint32_t bo_handles[4], + const uint32_t pitches[4], const uint32_t offsets[4], uint32_t *buf_id, uint32_t flags) { return drmModeAddFB2WithModifiers(fd, width, height, diff --git a/xf86drmMode.h b/xf86drmMode.h index 5b390d9f..6dbe3353 100644 --- a/xf86drmMode.h +++ b/xf86drmMode.h @@ -369,15 +369,16 @@ extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth, uint32_t *buf_id); /* ...with a specific pixel format */ extern int drmModeAddFB2(int fd, uint32_t width, uint32_t height, - uint32_t pixel_format, uint32_t bo_handles[4], - uint32_t pitches[4], uint32_t offsets[4], + uint32_t pixel_format, const uint32_t bo_handles[4], + const uint32_t pitches[4], const uint32_t offsets[4], uint32_t *buf_id, uint32_t flags); /* ...with format modifiers */ int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height, - uint32_t pixel_format, uint32_t bo_handles[4], - uint32_t pitches[4], uint32_t offsets[4], - uint64_t modifier[4], uint32_t *buf_id, uint32_t flags); + uint32_t pixel_format, const uint32_t bo_handles[4], + const uint32_t pitches[4], const uint32_t offsets[4], + const uint64_t modifier[4], uint32_t *buf_id, + uint32_t flags); /** * Destroies the given framebuffer. -- cgit v1.2.3-54-g00ecf From f579747485115cb1605a671082a70181b9a5b425 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 21 Oct 2017 00:19:52 +0200 Subject: amdgpu: add padding to the fence to handle ioctl copied from Dave's kernel patch. --- include/drm/amdgpu_drm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index ff018182..919248fb 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -553,6 +553,7 @@ union drm_amdgpu_fence_to_handle { struct { struct drm_amdgpu_fence fence; __u32 what; + __u32 pad; } in; struct { __u32 handle; -- cgit v1.2.3-54-g00ecf From e580be90e88eeed95faa5452e343f3ec509517e5 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 21 Oct 2017 00:26:24 +0200 Subject: configure.ac: bump version to 2.4.85 --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index ccb910a2..16df3a6c 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.84], + [2.4.85], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 0d889201d106f7f440a0e45b3fef554c31e2a551 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Oct 2017 16:37:44 +1000 Subject: drm: sync drm headers from drm-next. This updates the headers with the contents in drm-next at 62884cd386b876638720ef88374b31a84ca7ee5f This adds leasing and aspect ratio. --- include/drm/drm.h | 41 ++++++++++++++++++++++ include/drm/drm_mode.h | 92 +++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 124 insertions(+), 9 deletions(-) diff --git a/include/drm/drm.h b/include/drm/drm.h index 4737261a..f0bd91de 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -731,6 +731,28 @@ struct drm_syncobj_array { __u32 pad; }; +/* Query current scanout sequence number */ +struct drm_crtc_get_sequence { + __u32 crtc_id; /* requested crtc_id */ + __u32 active; /* return: crtc output is active */ + __u64 sequence; /* return: most recent vblank sequence */ + __s64 sequence_ns; /* return: most recent time of first pixel out */ +}; + +/* Queue event to be delivered at specified sequence. Time stamp marks + * when the first pixel of the refresh cycle leaves the display engine + * for the display + */ +#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ +#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ + +struct drm_crtc_queue_sequence { + __u32 crtc_id; + __u32 flags; + __u64 sequence; /* on input, target sequence. on output, actual sequence */ + __u64 user_data; /* user data passed to event */ +}; + #if defined(__cplusplus) } #endif @@ -813,6 +835,9 @@ extern "C" { #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) +#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) +#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) + #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) @@ -857,6 +882,11 @@ extern "C" { #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) +#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) +#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) +#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) +#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) + /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. @@ -887,6 +917,7 @@ struct drm_event { #define DRM_EVENT_VBLANK 0x01 #define DRM_EVENT_FLIP_COMPLETE 0x02 +#define DRM_EVENT_CRTC_SEQUENCE 0x03 struct drm_event_vblank { struct drm_event base; @@ -897,6 +928,16 @@ struct drm_event_vblank { __u32 crtc_id; /* 0 on older kernels that do not support this */ }; +/* Event delivered at sequence. Time stamp marks when the first pixel + * of the refresh cycle leaves the display engine for the display + */ +struct drm_event_crtc_sequence { + struct drm_event base; + __u64 user_data; + __s64 time_ns; + __u64 sequence; +}; + /* typedef area */ typedef struct drm_clip_rect drm_clip_rect_t; typedef struct drm_drawable_info drm_drawable_info_t; diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index e01f129c..5597a871 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -75,7 +75,7 @@ extern "C" { * (define not exposed to user space). */ #define DRM_MODE_FLAG_3D_MASK (0x1f<<14) -#define DRM_MODE_FLAG_3D_NONE (0<<14) +#define DRM_MODE_FLAG_3D_NONE (0<<14) #define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) #define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) #define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) @@ -85,6 +85,19 @@ extern "C" { #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) +/* Picture aspect ratio options */ +#define DRM_MODE_PICTURE_ASPECT_NONE 0 +#define DRM_MODE_PICTURE_ASPECT_4_3 1 +#define DRM_MODE_PICTURE_ASPECT_16_9 2 + +/* Aspect ratio flag bitmask (4 bits 22:19) */ +#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19) +#define DRM_MODE_FLAG_PIC_AR_NONE \ + (DRM_MODE_PICTURE_ASPECT_NONE<<19) +#define DRM_MODE_FLAG_PIC_AR_4_3 \ + (DRM_MODE_PICTURE_ASPECT_4_3<<19) +#define DRM_MODE_FLAG_PIC_AR_16_9 \ + (DRM_MODE_PICTURE_ASPECT_16_9<<19) /* DPMS flags */ /* bit compatible with the xorg definitions. */ @@ -100,11 +113,6 @@ extern "C" { #define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ #define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ -/* Picture aspect ratio options */ -#define DRM_MODE_PICTURE_ASPECT_NONE 0 -#define DRM_MODE_PICTURE_ASPECT_4_3 1 -#define DRM_MODE_PICTURE_ASPECT_16_9 2 - /* Dithering mode options */ #define DRM_MODE_DITHERING_OFF 0 #define DRM_MODE_DITHERING_ON 1 @@ -724,7 +732,7 @@ struct drm_format_modifier_blob { /* Where in this blob the modifiers exist (in bytes) */ __u32 modifiers_offset; - /* u32 formats[] */ + /* __u32 formats[] */ /* struct drm_format_modifier modifiers[] */ }; @@ -741,9 +749,9 @@ struct drm_format_modifier { * If the number formats grew to 128, and formats 98-102 are * supported with the modifier: * - * 0x0000003c00000000 0000000000000000 + * 0x0000007c00000000 0000000000000000 * ^ - * |__offset = 64, formats = 0x3c00000000 + * |__offset = 64, formats = 0x7c00000000 * */ __u64 formats; @@ -774,6 +782,72 @@ struct drm_mode_destroy_blob { __u32 blob_id; }; +/** + * Lease mode resources, creating another drm_master. + */ +struct drm_mode_create_lease { + /** Pointer to array of object ids (__u32) */ + __u64 object_ids; + /** Number of object ids */ + __u32 object_count; + /** flags for new FD (O_CLOEXEC, etc) */ + __u32 flags; + + /** Return: unique identifier for lessee. */ + __u32 lessee_id; + /** Return: file descriptor to new drm_master file */ + __u32 fd; +}; + +/** + * List lesses from a drm_master + */ +struct drm_mode_list_lessees { + /** Number of lessees. + * On input, provides length of the array. + * On output, provides total number. No + * more than the input number will be written + * back, so two calls can be used to get + * the size and then the data. + */ + __u32 count_lessees; + __u32 pad; + + /** Pointer to lessees. + * pointer to __u64 array of lessee ids + */ + __u64 lessees_ptr; +}; + +/** + * Get leased objects + */ +struct drm_mode_get_lease { + /** Number of leased objects. + * On input, provides length of the array. + * On output, provides total number. No + * more than the input number will be written + * back, so two calls can be used to get + * the size and then the data. + */ + __u32 count_objects; + __u32 pad; + + /** Pointer to objects. + * pointer to __u32 array of object ids + */ + __u64 objects_ptr; +}; + +/** + * Revoke lease + */ +struct drm_mode_revoke_lease { + /** Unique ID of lessee + */ + __u32 lessee_id; +}; + #if defined(__cplusplus) } #endif -- cgit v1.2.3-54-g00ecf From 61ff9779e37179ed5106c0e2452e16500127fb9e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Oct 2017 07:43:56 +0100 Subject: drm/syncobj: fix some whitespace issues These had tabs, just remove them. Signed-off-by: Dave Airlie --- xf86drm.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/xf86drm.c b/xf86drm.c index 8a327170..c44621c1 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -4155,7 +4155,7 @@ int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle) args.handle = 0; ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &args); if (ret) - return ret; + return ret; *handle = args.handle; return 0; } @@ -4179,7 +4179,7 @@ int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd) args.handle = handle; ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args); if (ret) - return ret; + return ret; *obj_fd = args.fd; return 0; } @@ -4194,7 +4194,7 @@ int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle) args.handle = 0; ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, &args); if (ret) - return ret; + return ret; *handle = args.handle; return 0; } @@ -4221,29 +4221,29 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd) args.flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE; ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args); if (ret) - return ret; + return ret; *sync_file_fd = args.fd; return 0; } int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, - int64_t timeout_nsec, unsigned flags, - uint32_t *first_signaled) + int64_t timeout_nsec, unsigned flags, + uint32_t *first_signaled) { - struct drm_syncobj_wait args; - int ret; + struct drm_syncobj_wait args; + int ret; - memclear(args); - args.handles = (intptr_t)handles; - args.timeout_nsec = timeout_nsec; - args.count_handles = num_handles; - args.flags = flags; + memclear(args); + args.handles = (intptr_t)handles; + args.timeout_nsec = timeout_nsec; + args.count_handles = num_handles; + args.flags = flags; - ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args); - if (ret < 0) - return ret; + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args); + if (ret < 0) + return ret; - if (first_signaled) - *first_signaled = args.first_signaled; - return ret; + if (first_signaled) + *first_signaled = args.first_signaled; + return ret; } -- cgit v1.2.3-54-g00ecf From 9b38ea82fc30ccbf38ebc0c55412b27e5a5afd7b Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 27 Oct 2017 11:09:10 -0400 Subject: amdgpu: Add wrappers for AMDGPU_VM IOCTL. v2: Rename wrappers to match the IOCTL naming, fix identation and fix make check error. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- amdgpu/Makefile.sources | 1 + amdgpu/amdgpu-symbol-check | 2 ++ amdgpu/amdgpu.h | 18 +++++++++++++++++ amdgpu/amdgpu_vm.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 71 insertions(+) create mode 100644 amdgpu/amdgpu_vm.c diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources index bc3abaa6..498b64cc 100644 --- a/amdgpu/Makefile.sources +++ b/amdgpu/Makefile.sources @@ -6,6 +6,7 @@ LIBDRM_AMDGPU_FILES := \ amdgpu_gpu_info.c \ amdgpu_internal.h \ amdgpu_vamgr.c \ + amdgpu_vm.c \ util_hash.c \ util_hash.h \ util_hash_table.c \ diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 095c3a08..d476038b 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -64,6 +64,8 @@ amdgpu_read_mm_registers amdgpu_va_range_alloc amdgpu_va_range_free amdgpu_va_range_query +amdgpu_vm_reserve_vmid +amdgpu_vm_unreserve_vmid EOF done) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index ecc975f1..597fc2ba 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1489,6 +1489,24 @@ void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, struct drm_amdgpu_cs_chunk_data *data); +/** + * Reserve VMID + * \param context - \c [in] GPU Context + * \param flags - \c [in] TBD + * + * \return 0 on success otherwise POSIX Error code +*/ +int amdgpu_vm_reserve_vmid(amdgpu_context_handle context, uint32_t flags); + +/** + * Free reserved VMID + * \param context - \c [in] GPU Context + * \param flags - \c [in] TBD + * + * \return 0 on success otherwise POSIX Error code +*/ +int amdgpu_vm_unreserve_vmid(amdgpu_context_handle context, uint32_t flags); + #ifdef __cplusplus } #endif diff --git a/amdgpu/amdgpu_vm.c b/amdgpu/amdgpu_vm.c new file mode 100644 index 00000000..8a9a0a15 --- /dev/null +++ b/amdgpu/amdgpu_vm.c @@ -0,0 +1,50 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#include "amdgpu.h" +#include "amdgpu_drm.h" +#include "xf86drm.h" +#include "amdgpu_internal.h" + +int amdgpu_vm_reserve_vmid(amdgpu_context_handle context, uint32_t flags) +{ + union drm_amdgpu_vm vm; + + vm.in.op = AMDGPU_VM_OP_RESERVE_VMID; + vm.in.flags = flags; + + return drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_VM, + &vm, sizeof(vm)); +} + +int amdgpu_vm_unreserve_vmid(amdgpu_context_handle context, uint32_t flags) +{ + union drm_amdgpu_vm vm; + + vm.in.op = AMDGPU_VM_OP_UNRESERVE_VMID; + vm.in.flags = flags; + + return drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_VM, + &vm, sizeof(vm)); +} -- cgit v1.2.3-54-g00ecf From 33dcc29f7ccc554de1fc42f4b95adf056822eabb Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 27 Oct 2017 11:09:11 -0400 Subject: amdgpu: Add VMID reservation per GPU context test. The test will Reserve a VMID, submit a command and unreserve the VMID. v2: Wrappers names were changed. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/Makefile.am | 3 +- tests/amdgpu/amdgpu_test.c | 7 +++ tests/amdgpu/amdgpu_test.h | 15 +++++ tests/amdgpu/vm_tests.c | 151 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 tests/amdgpu/vm_tests.c diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index 8700c4d4..e79c1bd3 100644 --- a/tests/amdgpu/Makefile.am +++ b/tests/amdgpu/Makefile.am @@ -31,4 +31,5 @@ amdgpu_test_SOURCES = \ uvd_enc_tests.c \ vcn_tests.c \ uve_ib.h \ - deadlock_tests.c + deadlock_tests.c \ + vm_tests.c diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 99255038..a82d9ab1 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -103,6 +103,13 @@ static CU_SuiteInfo suites[] = { .pCleanupFunc = suite_deadlock_tests_clean, .pTests = deadlock_tests, }, + { + .pName = "VM Tests", + .pInitFunc = suite_vm_tests_init, + .pCleanupFunc = suite_vm_tests_clean, + .pTests = vm_tests, + }, + CU_SUITE_INFO_NULL, }; diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index ece93f4c..4fffbc62 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -149,6 +149,21 @@ int suite_deadlock_tests_clean(); */ extern CU_TestInfo deadlock_tests[]; +/** + * Initialize vm test suite + */ +int suite_vm_tests_init(); + +/** + * Deinitialize deadlock test suite + */ +int suite_vm_tests_clean(); + +/** + * Tests in vm test suite + */ +extern CU_TestInfo vm_tests[]; + /** * Helper functions */ diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c new file mode 100644 index 00000000..cbfafe97 --- /dev/null +++ b/tests/amdgpu/vm_tests.c @@ -0,0 +1,151 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; + + +static void amdgpu_vmid_reserve_test(void); + +int suite_vm_tests_init(void) +{ + struct amdgpu_gpu_info gpu_info = {0}; + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + + if (r) { + if ((r == -EACCES) && (errno == EACCES)) + printf("\n\nError:%s. " + "Hint:Try to run this test program as root.", + strerror(errno)); + return CUE_SINIT_FAILED; + } + + return CUE_SUCCESS; +} + +int suite_vm_tests_clean(void) +{ + int r = amdgpu_device_deinitialize(device_handle); + + if (r == 0) + return CUE_SUCCESS; + else + return CUE_SCLEAN_FAILED; +} + + +CU_TestInfo vm_tests[] = { + { "resere vmid test", amdgpu_vmid_reserve_test }, + CU_TEST_INFO_NULL, +}; + +static void amdgpu_vmid_reserve_test(void) +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle ib_result_handle; + void *ib_result_cpu; + uint64_t ib_result_mc_address; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + struct amdgpu_cs_fence fence_status; + uint32_t expired, flags; + int i, r, instance; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle; + union drm_amdgpu_vm vm; + static uint32_t *ptr; + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + flags = 0; + r = amdgpu_vm_reserve_vmid(context_handle, flags); + CU_ASSERT_EQUAL(r, 0); + + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, + &bo_list); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu; + + for (i = 0; i < 16; ++i) + ptr[i] = 0xffff1000; + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address; + ib_info.size = 16; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + ibs_request.fence_info.handle = NULL; + + r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + + + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); + fence_status.context = context_handle; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.ring = 0; + fence_status.fence = ibs_request.seq_no; + + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE,0, &expired); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096); + CU_ASSERT_EQUAL(r, 0); + + flags = 0; + r = amdgpu_vm_unreserve_vmid(context_handle, flags); + CU_ASSERT_EQUAL(r, 0); + + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} -- cgit v1.2.3-54-g00ecf From a4b487cd80f7394f3c285d5883a24a07e156f867 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 31 Oct 2017 02:11:20 +0100 Subject: configure.ac: bump version for release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 16df3a6c..d02a29b3 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.85], + [2.4.86], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 76c325ee7d8975248d18f2e0b6b16a03abcef4df Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 31 Oct 2017 15:48:23 +0100 Subject: amdgpu: fix 32-bit build --- amdgpu/amdgpu_vm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/amdgpu/amdgpu_vm.c b/amdgpu/amdgpu_vm.c index 8a9a0a15..304b423c 100644 --- a/amdgpu/amdgpu_vm.c +++ b/amdgpu/amdgpu_vm.c @@ -21,6 +21,9 @@ * */ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif #include "amdgpu.h" #include "amdgpu_drm.h" -- cgit v1.2.3-54-g00ecf From b617f059ad45517bded1f2d8c8e3a52b60e80bd7 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 31 Oct 2017 15:49:12 +0100 Subject: configure.ac: bump version for release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index d02a29b3..a300ff3c 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.86], + [2.4.87], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From f3091bac21a963f1a3d8ce5db85c0f2b4acbeb49 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 2 Nov 2017 10:29:55 -0400 Subject: amdgpu: Fix wrappers for AMDGPU_VM IOCTL. Rmove amdgpu_context_handle from the interface and use amdgpu_device_handle instead. Uupdate VMID reservation test accordingly. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- amdgpu/amdgpu.h | 4 ++-- amdgpu/amdgpu_vm.c | 8 ++++---- tests/amdgpu/vm_tests.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 597fc2ba..df85a24c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1496,7 +1496,7 @@ void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, * * \return 0 on success otherwise POSIX Error code */ -int amdgpu_vm_reserve_vmid(amdgpu_context_handle context, uint32_t flags); +int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); /** * Free reserved VMID @@ -1505,7 +1505,7 @@ int amdgpu_vm_reserve_vmid(amdgpu_context_handle context, uint32_t flags); * * \return 0 on success otherwise POSIX Error code */ -int amdgpu_vm_unreserve_vmid(amdgpu_context_handle context, uint32_t flags); +int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); #ifdef __cplusplus } diff --git a/amdgpu/amdgpu_vm.c b/amdgpu/amdgpu_vm.c index 304b423c..5ba7c082 100644 --- a/amdgpu/amdgpu_vm.c +++ b/amdgpu/amdgpu_vm.c @@ -30,24 +30,24 @@ #include "xf86drm.h" #include "amdgpu_internal.h" -int amdgpu_vm_reserve_vmid(amdgpu_context_handle context, uint32_t flags) +int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags) { union drm_amdgpu_vm vm; vm.in.op = AMDGPU_VM_OP_RESERVE_VMID; vm.in.flags = flags; - return drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_VM, + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, &vm, sizeof(vm)); } -int amdgpu_vm_unreserve_vmid(amdgpu_context_handle context, uint32_t flags) +int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags) { union drm_amdgpu_vm vm; vm.in.op = AMDGPU_VM_OP_UNRESERVE_VMID; vm.in.flags = flags; - return drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_VM, + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM, &vm, sizeof(vm)); } diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c index cbfafe97..5f183107 100644 --- a/tests/amdgpu/vm_tests.c +++ b/tests/amdgpu/vm_tests.c @@ -88,7 +88,7 @@ static void amdgpu_vmid_reserve_test(void) CU_ASSERT_EQUAL(r, 0); flags = 0; - r = amdgpu_vm_reserve_vmid(context_handle, flags); + r = amdgpu_vm_reserve_vmid(device_handle, flags); CU_ASSERT_EQUAL(r, 0); @@ -142,7 +142,7 @@ static void amdgpu_vmid_reserve_test(void) CU_ASSERT_EQUAL(r, 0); flags = 0; - r = amdgpu_vm_unreserve_vmid(context_handle, flags); + r = amdgpu_vm_unreserve_vmid(device_handle, flags); CU_ASSERT_EQUAL(r, 0); -- cgit v1.2.3-54-g00ecf From 2fe4c07b38ded7f4b9341512da6e670d3321012b Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Fri, 3 Nov 2017 17:28:58 +0100 Subject: configure.ac: bump version for release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index a300ff3c..b2d961b1 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.87], + [2.4.88], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From 62e0767b816cb52b35226d439090ef580bd60b01 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 23 Aug 2017 15:00:12 -0400 Subject: freedreno: sync uapi header (driver version 1.3.0) Signed-off-by: Rob Clark --- freedreno/msm/msm_drm.h | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/freedreno/msm/msm_drm.h b/freedreno/msm/msm_drm.h index ed4c8d47..dac49e59 100644 --- a/freedreno/msm/msm_drm.h +++ b/freedreno/msm/msm_drm.h @@ -73,6 +73,8 @@ struct drm_msm_timespec { #define MSM_PARAM_CHIP_ID 0x03 #define MSM_PARAM_MAX_FREQ 0x04 #define MSM_PARAM_TIMESTAMP 0x05 +#define MSM_PARAM_GMEM_BASE 0x06 +#define MSM_PARAM_NR_RINGS 0x07 struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ @@ -104,10 +106,14 @@ struct drm_msm_gem_new { __u32 handle; /* out */ }; +#define MSM_INFO_IOVA 0x01 + +#define MSM_INFO_FLAGS (MSM_INFO_IOVA) + struct drm_msm_gem_info { __u32 handle; /* in */ - __u32 pad; - __u64 offset; /* out, offset to pass to mmap() */ + __u32 flags; /* in - combination of MSM_INFO_* flags */ + __u64 offset; /* out, mmap() offset or iova */ }; #define MSM_PREP_READ 0x01 @@ -167,7 +173,7 @@ struct drm_msm_gem_submit_cmd { __u32 size; /* in, cmdstream size */ __u32 pad; __u32 nr_relocs; /* in, number of submit_reloc's */ - __u64 __user relocs; /* in, ptr to array of submit_reloc's */ + __u64 relocs; /* in, ptr to array of submit_reloc's */ }; /* Each buffer referenced elsewhere in the cmdstream submit (ie. the @@ -211,9 +217,10 @@ struct drm_msm_gem_submit { __u32 fence; /* out */ __u32 nr_bos; /* in, number of submit_bo's */ __u32 nr_cmds; /* in, number of submit_cmd's */ - __u64 __user bos; /* in, ptr to array of submit_bo's */ - __u64 __user cmds; /* in, ptr to array of submit_cmd's */ + __u64 bos; /* in, ptr to array of submit_bo's */ + __u64 cmds; /* in, ptr to array of submit_cmd's */ __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ + __u32 queueid; /* in, submitqueue id */ }; /* The normal way to synchronize with the GPU is just to CPU_PREP on @@ -227,6 +234,7 @@ struct drm_msm_wait_fence { __u32 fence; /* in */ __u32 pad; struct drm_msm_timespec timeout; /* in */ + __u32 queueid; /* in, submitqueue id */ }; /* madvise provides a way to tell the kernel in case a buffers contents @@ -250,6 +258,20 @@ struct drm_msm_gem_madvise { __u32 retained; /* out, whether backing store still exists */ }; +/* + * Draw queues allow the user to set specific submission parameter. Command + * submissions specify a specific submitqueue to use. ID 0 is reserved for + * backwards compatibility as a "default" submitqueue + */ + +#define MSM_SUBMITQUEUE_FLAGS (0) + +struct drm_msm_submitqueue { + __u32 flags; /* in, MSM_SUBMITQUEUE_x */ + __u32 prio; /* in, Priority level */ + __u32 id; /* out, identifier */ +}; + #define DRM_MSM_GET_PARAM 0x00 /* placeholder: #define DRM_MSM_SET_PARAM 0x01 @@ -261,7 +283,11 @@ struct drm_msm_gem_madvise { #define DRM_MSM_GEM_SUBMIT 0x06 #define DRM_MSM_WAIT_FENCE 0x07 #define DRM_MSM_GEM_MADVISE 0x08 -#define DRM_MSM_NUM_IOCTLS 0x09 +/* placeholder: +#define DRM_MSM_GEM_SVM_NEW 0x09 + */ +#define DRM_MSM_SUBMITQUEUE_NEW 0x0A +#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) @@ -271,6 +297,8 @@ struct drm_msm_gem_madvise { #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) +#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) +#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) #if defined(__cplusplus) } -- cgit v1.2.3-54-g00ecf From 7064b2eae9c136162e5c7f25571d63f71d066887 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 23 Aug 2017 17:08:39 -0400 Subject: freedreno: submit-queue context priority With a new-enough kernel to support prioritized submit-queues, we can expose priority level support to mesa. Open a submit queue associated with the fd_pipe and pass it's id back to SUBMIT ioctl. Signed-off-by: Rob Clark --- freedreno/freedreno_drmif.h | 3 +++ freedreno/freedreno_pipe.c | 19 +++++++++++++++++-- freedreno/freedreno_priv.h | 3 ++- freedreno/kgsl/kgsl_pipe.c | 3 ++- freedreno/kgsl/kgsl_priv.h | 2 +- freedreno/msm/msm_pipe.c | 41 ++++++++++++++++++++++++++++++++++++++++- freedreno/msm/msm_priv.h | 3 ++- freedreno/msm/msm_ringbuffer.c | 1 + 8 files changed, 68 insertions(+), 7 deletions(-) diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h index 7a8073ff..c3b0d02a 100644 --- a/freedreno/freedreno_drmif.h +++ b/freedreno/freedreno_drmif.h @@ -61,6 +61,7 @@ enum fd_param_id { FD_CHIP_ID, FD_MAX_FREQ, FD_TIMESTAMP, + FD_NR_RINGS, /* # of rings == # of distinct priority levels */ }; /* bo flags: */ @@ -93,6 +94,7 @@ enum fd_version { FD_VERSION_MADVISE = 1, /* kernel supports madvise */ FD_VERSION_UNLIMITED_CMDS = 1, /* submits w/ >4 cmd buffers (growable ringbuffer) */ FD_VERSION_FENCE_FD = 2, /* submit command supports in/out fences */ + FD_VERSION_SUBMIT_QUEUES = 3, /* submit queues and multiple priority levels */ }; enum fd_version fd_device_version(struct fd_device *dev); @@ -100,6 +102,7 @@ enum fd_version fd_device_version(struct fd_device *dev); */ struct fd_pipe * fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id); +struct fd_pipe * fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio); void fd_pipe_del(struct fd_pipe *pipe); int fd_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param, uint64_t *value); diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c index e69cb28c..1540474b 100644 --- a/freedreno/freedreno_pipe.c +++ b/freedreno/freedreno_pipe.c @@ -33,8 +33,12 @@ #include "freedreno_drmif.h" #include "freedreno_priv.h" +/** + * priority of zero is highest priority, and higher numeric values are + * lower priorities + */ struct fd_pipe * -fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id) +fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio) { struct fd_pipe *pipe; uint64_t val; @@ -44,7 +48,12 @@ fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id) return NULL; } - pipe = dev->funcs->pipe_new(dev, id); + if ((prio != 1) && (fd_device_version(dev) < FD_VERSION_SUBMIT_QUEUES)) { + ERROR_MSG("invalid priority!"); + return NULL; + } + + pipe = dev->funcs->pipe_new(dev, id, prio); if (!pipe) { ERROR_MSG("allocation failed"); return NULL; @@ -59,6 +68,12 @@ fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id) return pipe; } +struct fd_pipe * +fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id) +{ + return fd_pipe_new2(dev, id, 1); +} + void fd_pipe_del(struct fd_pipe *pipe) { pipe->funcs->destroy(pipe); diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index 8dd3ee69..27307472 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -66,7 +66,8 @@ struct fd_device_funcs { uint32_t flags, uint32_t *handle); struct fd_bo * (*bo_from_handle)(struct fd_device *dev, uint32_t size, uint32_t handle); - struct fd_pipe * (*pipe_new)(struct fd_device *dev, enum fd_pipe_id id); + struct fd_pipe * (*pipe_new)(struct fd_device *dev, enum fd_pipe_id id, + unsigned prio); void (*destroy)(struct fd_device *dev); }; diff --git a/freedreno/kgsl/kgsl_pipe.c b/freedreno/kgsl/kgsl_pipe.c index 8a39eb49..80bd1313 100644 --- a/freedreno/kgsl/kgsl_pipe.c +++ b/freedreno/kgsl/kgsl_pipe.c @@ -52,6 +52,7 @@ static int kgsl_pipe_get_param(struct fd_pipe *pipe, return 0; case FD_MAX_FREQ: case FD_TIMESTAMP: + case FD_NR_RINGS: /* unsupported on kgsl */ return -1; default: @@ -210,7 +211,7 @@ static int getprop(int fd, enum kgsl_property_type type, drm_private struct fd_pipe * kgsl_pipe_new(struct fd_device *dev, - enum fd_pipe_id id) + enum fd_pipe_id id, uint32_t prio) { static const char *paths[] = { [FD_PIPE_3D] = "/dev/kgsl-3d0", diff --git a/freedreno/kgsl/kgsl_priv.h b/freedreno/kgsl/kgsl_priv.h index 6ab64965..41b13920 100644 --- a/freedreno/kgsl/kgsl_priv.h +++ b/freedreno/kgsl/kgsl_priv.h @@ -103,7 +103,7 @@ drm_private void kgsl_pipe_post_submit(struct kgsl_pipe *pipe, drm_private void kgsl_pipe_process_pending(struct kgsl_pipe *pipe, uint32_t timestamp); drm_private struct fd_pipe * kgsl_pipe_new(struct fd_device *dev, - enum fd_pipe_id id); + enum fd_pipe_id id, uint32_t prio); drm_private struct fd_ringbuffer * kgsl_ringbuffer_new(struct fd_pipe *pipe, uint32_t size); diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c index f872e245..7395e573 100644 --- a/freedreno/msm/msm_pipe.c +++ b/freedreno/msm/msm_pipe.c @@ -71,6 +71,8 @@ static int msm_pipe_get_param(struct fd_pipe *pipe, return query_param(pipe, MSM_PARAM_MAX_FREQ, value); case FD_TIMESTAMP: return query_param(pipe, MSM_PARAM_TIMESTAMP, value); + case FD_NR_RINGS: + return query_param(pipe, MSM_PARAM_NR_RINGS, value); default: ERROR_MSG("invalid param id: %d", param); return -1; @@ -83,6 +85,7 @@ static int msm_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp, struct fd_device *dev = pipe->dev; struct drm_msm_wait_fence req = { .fence = timestamp, + .queueid = to_msm_pipe(pipe)->queue_id, }; int ret; @@ -97,9 +100,42 @@ static int msm_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp, return 0; } +static int open_submitqueue(struct fd_device *dev, uint32_t prio, + uint32_t *queue_id) +{ + struct drm_msm_submitqueue req = { + .flags = 0, + .prio = prio, + }; + int ret; + + if (fd_device_version(dev) < FD_VERSION_SUBMIT_QUEUES) { + *queue_id = 0; + return 0; + } + + ret = drmCommandWriteRead(dev->fd, DRM_MSM_SUBMITQUEUE_NEW, &req, sizeof(req)); + if (ret) { + ERROR_MSG("could not create submitqueue! %d (%s)", ret, strerror(errno)); + return ret; + } + + *queue_id = req.id; + return 0; +} + +static void close_submitqueue(struct fd_device *dev, uint32_t queue_id) +{ + if (fd_device_version(dev) < FD_VERSION_SUBMIT_QUEUES) + return; + + drmCommandWrite(dev->fd, DRM_MSM_SUBMITQUEUE_CLOSE, &queue_id, sizeof(queue_id)); +} + static void msm_pipe_destroy(struct fd_pipe *pipe) { struct msm_pipe *msm_pipe = to_msm_pipe(pipe); + close_submitqueue(pipe->dev, msm_pipe->queue_id); free(msm_pipe); } @@ -122,7 +158,7 @@ static uint64_t get_param(struct fd_pipe *pipe, uint32_t param) } drm_private struct fd_pipe * msm_pipe_new(struct fd_device *dev, - enum fd_pipe_id id) + enum fd_pipe_id id, uint32_t prio) { static const uint32_t pipe_id[] = { [FD_PIPE_3D] = MSM_PIPE_3D0, @@ -157,6 +193,9 @@ drm_private struct fd_pipe * msm_pipe_new(struct fd_device *dev, INFO_MSG(" Chip-id: 0x%08x", msm_pipe->chip_id); INFO_MSG(" GMEM size: 0x%08x", msm_pipe->gmem); + if (open_submitqueue(dev, prio, &msm_pipe->queue_id)) + goto fail; + return pipe; fail: if (pipe) diff --git a/freedreno/msm/msm_priv.h b/freedreno/msm/msm_priv.h index 6d670aab..88ac3aa4 100644 --- a/freedreno/msm/msm_priv.h +++ b/freedreno/msm/msm_priv.h @@ -56,6 +56,7 @@ struct msm_pipe { uint32_t gpu_id; uint32_t gmem; uint32_t chip_id; + uint32_t queue_id; }; static inline struct msm_pipe * to_msm_pipe(struct fd_pipe *x) @@ -64,7 +65,7 @@ static inline struct msm_pipe * to_msm_pipe(struct fd_pipe *x) } drm_private struct fd_pipe * msm_pipe_new(struct fd_device *dev, - enum fd_pipe_id id); + enum fd_pipe_id id, uint32_t prio); drm_private struct fd_ringbuffer * msm_ringbuffer_new(struct fd_pipe *pipe, uint32_t size); diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index 5b28feaa..c75bb169 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c @@ -401,6 +401,7 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring); struct drm_msm_gem_submit req = { .flags = to_msm_pipe(ring->pipe)->pipe, + .queueid = to_msm_pipe(ring->pipe)->queue_id, }; uint32_t i; int ret; -- cgit v1.2.3-54-g00ecf From be40710f063a5218f62da61f5a854c69836f91e7 Mon Sep 17 00:00:00 2001 From: Inki Dae Date: Thu, 10 Aug 2017 13:52:38 +0900 Subject: exynos: change the license to X11/MIT Change GPL license of Exynos related code to X11/MIT. I'd like to keep a consistent license across all Exynos code because License checker notices two more licenses exist in libdrm. For the license change I need to get your agree - all committers. So please give me Acked-by if you agree with me. Signed-off-by: Inki Dae Acked-by: Hyungwon Hwang Acked-by: SooChan Lim Acked-by: Sangjin LEE Acked-by: Boram Park Acked-by: Seung-Woo Kim Acked-by: Joonyoung Shim Acked-by: Emil Velikov Acked-by: Tobias Jakobi Acked-by: Jan Vesely --- exynos/exynos_fimg2d.c | 21 +++++++++++++++++---- exynos/exynos_fimg2d.h | 21 +++++++++++++++++---- exynos/fimg2d_reg.h | 21 +++++++++++++++++---- libkms/exynos.c | 22 ++++++++++++++++++---- tests/exynos/exynos_fimg2d_event.c | 27 +++++++++++++++++---------- tests/exynos/exynos_fimg2d_perf.c | 27 +++++++++++++++++---------- tests/exynos/exynos_fimg2d_test.c | 21 +++++++++++++++++---- 7 files changed, 120 insertions(+), 40 deletions(-) diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c index 61340c36..5658a48e 100644 --- a/exynos/exynos_fimg2d.c +++ b/exynos/exynos_fimg2d.c @@ -3,11 +3,24 @@ * Authors: * Inki Dae * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #ifdef HAVE_CONFIG_H diff --git a/exynos/exynos_fimg2d.h b/exynos/exynos_fimg2d.h index a825c683..a4dfbe73 100644 --- a/exynos/exynos_fimg2d.h +++ b/exynos/exynos_fimg2d.h @@ -3,11 +3,24 @@ * Authors: * Inki Dae * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _FIMG2D_H_ diff --git a/exynos/fimg2d_reg.h b/exynos/fimg2d_reg.h index 07dd6349..d42296d4 100644 --- a/exynos/fimg2d_reg.h +++ b/exynos/fimg2d_reg.h @@ -3,11 +3,24 @@ * Authors: * Inki Dae * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _FIMG2D_REG_H_ diff --git a/libkms/exynos.c b/libkms/exynos.c index 0e97fb51..c20b6b05 100644 --- a/libkms/exynos.c +++ b/libkms/exynos.c @@ -5,10 +5,24 @@ * SooChan Lim * Sangjin LEE * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #ifdef HAVE_CONFIG_H diff --git a/tests/exynos/exynos_fimg2d_event.c b/tests/exynos/exynos_fimg2d_event.c index 9ed5a307..353e087b 100644 --- a/tests/exynos/exynos_fimg2d_event.c +++ b/tests/exynos/exynos_fimg2d_event.c @@ -1,17 +1,24 @@ /* * Copyright (C) 2015 - Tobias Jakobi * - * This is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundation, either version 2 of the License, - * or (at your option) any later version. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * It is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * You should have received a copy of the GNU General Public License - * along with it. If not, see . + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/tests/exynos/exynos_fimg2d_perf.c b/tests/exynos/exynos_fimg2d_perf.c index 1699bba7..a2d5c192 100644 --- a/tests/exynos/exynos_fimg2d_perf.c +++ b/tests/exynos/exynos_fimg2d_perf.c @@ -1,17 +1,24 @@ /* * Copyright (C) 2015 - Tobias Jakobi * - * This is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundation, either version 2 of the License, - * or (at your option) any later version. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * It is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * You should have received a copy of the GNU General Public License - * along with it. If not, see . + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index ab1028e8..b71cf593 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -3,11 +3,24 @@ * Authors: * Inki Dae * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #ifdef HAVE_CONFIG_H -- cgit v1.2.3-54-g00ecf From cfe0ae53556261250a08b625e020a7e0712bc59e Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Tue, 7 Nov 2017 11:21:32 +0000 Subject: freedreno: add the API fd_pipe_new2 to the symbol test As kindly spotted by `make check' Signed-off-by: Emil Velikov --- freedreno/freedreno-symbol-check | 1 + 1 file changed, 1 insertion(+) diff --git a/freedreno/freedreno-symbol-check b/freedreno/freedreno-symbol-check index 42f2c439..6b81040c 100755 --- a/freedreno/freedreno-symbol-check +++ b/freedreno/freedreno-symbol-check @@ -33,6 +33,7 @@ fd_device_version fd_pipe_del fd_pipe_get_param fd_pipe_new +fd_pipe_new2 fd_pipe_wait fd_pipe_wait_timeout fd_ringbuffer_cmd_count -- cgit v1.2.3-54-g00ecf From 4b4ccaac2e01af2d5846d168dedc2ee9cb8e7672 Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 2 Nov 2017 18:47:34 +0100 Subject: amdpgu: fix coding style in amdgpu_vamgr.c No functional change. Signed-off-by: Christian König --- amdgpu/amdgpu_vamgr.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 2b1388ed..8516b594 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -34,18 +34,19 @@ #include "util_math.h" int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) + enum amdgpu_gpu_va_range type, + uint64_t *start, uint64_t *end) { - if (type == amdgpu_gpu_va_range_general) { - *start = dev->dev_info.virtual_address_offset; - *end = dev->dev_info.virtual_address_max; - return 0; - } - return -EINVAL; + if (type != amdgpu_gpu_va_range_general) + return -EINVAL; + + *start = dev->dev_info.virtual_address_offset; + *end = dev->dev_info.virtual_address_max; + return 0; } drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, - uint64_t max, uint64_t alignment) + uint64_t max, uint64_t alignment) { mgr->va_offset = start; mgr->va_max = max; @@ -83,8 +84,8 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, /* first look for a hole */ LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { if (base_required) { - if(hole->offset > base_required || - (hole->offset + hole->size) < (base_required + size)) + if (hole->offset > base_required || + (hole->offset + hole->size) < (base_required + size)) continue; waste = base_required - hole->offset; offset = base_required; @@ -192,9 +193,9 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) hole->offset = va; hole->size += size; /* Merge lower hole if it's adjacent */ - if (next != hole - && &next->list != &mgr->va_holes - && (next->offset + next->size) == va) { + if (next != hole && + &next->list != &mgr->va_holes && + (next->offset + next->size) == va) { next->size += hole->size; list_del(&hole->list); free(hole); -- cgit v1.2.3-54-g00ecf From a844925c8af45161145ab512efb8d5584c9d97f2 Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 2 Nov 2017 18:54:59 +0100 Subject: amdgpu: sanitize 64bit VA manager Adding the extra reservation of the 32bit space to the 64bit manager is complete nonsense and just a waste of memory and CPU cycles. Signed-off-by: Christian König --- amdgpu/amdgpu_device.c | 24 ++++++------------------ amdgpu/amdgpu_internal.h | 7 ------- amdgpu/amdgpu_vamgr.c | 4 ++-- 3 files changed, 8 insertions(+), 27 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 2b31c45b..344e87ed 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -270,22 +270,16 @@ int amdgpu_device_initialize(int fd, goto cleanup; } - amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset, - dev->dev_info.virtual_address_max, - dev->dev_info.virtual_address_alignment); - + start = dev->dev_info.virtual_address_offset; max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); - start = amdgpu_vamgr_find_va(&dev->vamgr, - max - dev->dev_info.virtual_address_offset, - dev->dev_info.virtual_address_alignment, 0); - if (start > 0xffffffff) { - fprintf(stderr, "%s: amdgpu_vamgr_find_va failed\n", __func__); - goto free_va; /* shouldn't get here */ - } - amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); + start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL); + max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); + amdgpu_vamgr_init(&dev->vamgr, start, max, + dev->dev_info.virtual_address_alignment); + r = amdgpu_parse_asic_ids(&dev->asic_ids); if (r) { fprintf(stderr, "%s: Cannot parse ASIC IDs, 0x%x.", @@ -300,12 +294,6 @@ int amdgpu_device_initialize(int fd, return 0; -free_va: - r = -ENOMEM; - amdgpu_vamgr_free_va(&dev->vamgr, start, - max - dev->dev_info.virtual_address_offset); - amdgpu_vamgr_deinit(&dev->vamgr); - cleanup: if (dev->fd >= 0) close(dev->fd); diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 56d15112..e26e5190 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -148,13 +148,6 @@ drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr); -drm_private uint64_t -amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - uint64_t alignment, uint64_t base_required); - -drm_private void -amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); - drm_private int amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids); drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 8516b594..ab425ef7 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -66,7 +66,7 @@ drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) pthread_mutex_destroy(&mgr->bo_va_mutex); } -drm_private uint64_t +static drm_private uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, uint64_t alignment, uint64_t base_required) { @@ -155,7 +155,7 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, return offset; } -drm_private void +static drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) { struct amdgpu_bo_va_hole *hole; -- cgit v1.2.3-54-g00ecf From 944f6665de36b6a6c36263f23b7b9d1730e544fa Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 2 Nov 2017 18:54:59 +0100 Subject: amdgpu: fix 32bit VA manager max address The range is exclusive not inclusive. Signed-off-by: Christian König --- amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 344e87ed..fa4ab0e7 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -271,7 +271,7 @@ int amdgpu_device_initialize(int fd, } start = dev->dev_info.virtual_address_offset; - max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); + max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); -- cgit v1.2.3-54-g00ecf From 6c0ea4b0c5452bfc1e67b74ce723696ef3c80b25 Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 7 Nov 2017 15:31:45 +0100 Subject: amdgpu: use the high VA range if possible This frees up the low range for HMM. Signed-off-by: Christian König --- amdgpu/amdgpu_device.c | 9 +++++++-- include/drm/amdgpu_drm.h | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index fa4ab0e7..e04424d3 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -275,8 +275,13 @@ int amdgpu_device_initialize(int fd, amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); - start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL); - max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); + if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) { + start = dev->dev_info.high_va_offset; + max = dev->dev_info.high_va_max; + } else { + start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL); + max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); + } amdgpu_vamgr_init(&dev->vamgr, start, max, dev->dev_info.virtual_address_alignment); diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 919248fb..a023b476 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -869,6 +869,10 @@ struct drm_amdgpu_info_device { __u32 _pad1; /* always on cu bitmap */ __u32 cu_ao_bitmap[4][4]; + /** Starting high virtual address for UMDs. */ + __u64 high_va_offset; + /** The maximum high virtual address */ + __u64 high_va_max; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3-54-g00ecf From 0c2481edf7a2ce674beaf9ea61a6b19dea2f210b Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 9 Nov 2017 10:35:24 +0100 Subject: Revert "amdgpu: use the high VA range if possible" This reverts commit 6c0ea4b0c5452bfc1e67b74ce723696ef3c80b25. Accidentially pushed an incomplete patch. Signed-off-by: Christian König --- amdgpu/amdgpu_device.c | 9 ++------- include/drm/amdgpu_drm.h | 4 ---- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index e04424d3..fa4ab0e7 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -275,13 +275,8 @@ int amdgpu_device_initialize(int fd, amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); - if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) { - start = dev->dev_info.high_va_offset; - max = dev->dev_info.high_va_max; - } else { - start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL); - max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); - } + start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL); + max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr, start, max, dev->dev_info.virtual_address_alignment); diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index a023b476..919248fb 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -869,10 +869,6 @@ struct drm_amdgpu_info_device { __u32 _pad1; /* always on cu bitmap */ __u32 cu_ao_bitmap[4][4]; - /** Starting high virtual address for UMDs. */ - __u64 high_va_offset; - /** The maximum high virtual address */ - __u64 high_va_max; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3-54-g00ecf From 931f01964a2f2a75e8563feccc70ac2eb0296d99 Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 9 Nov 2017 10:36:05 +0100 Subject: Revert "amdgpu: fix 32bit VA manager max address" This reverts commit 944f6665de36b6a6c36263f23b7b9d1730e544fa. Accidentially pushed an imcomplete patch. Signed-off-by: Christian König --- amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index fa4ab0e7..344e87ed 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -271,7 +271,7 @@ int amdgpu_device_initialize(int fd, } start = dev->dev_info.virtual_address_offset; - max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL); + max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); -- cgit v1.2.3-54-g00ecf From e38de517991a20d7a2abdffc1bc4fd702e8f673c Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 8 Nov 2017 11:04:31 -0800 Subject: headers: Sync vc4 header from drm-next. This updates the header with the contents from drm-next d65d31388a23 ("Merge tag 'drm-misc-next-fixes-2017-11-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next") Signed-off-by: Eric Anholt Reviewed-by: Emil Velikov --- include/drm/vc4_drm.h | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h index 6ac4c5c0..3415a4b7 100644 --- a/include/drm/vc4_drm.h +++ b/include/drm/vc4_drm.h @@ -21,8 +21,8 @@ * IN THE SOFTWARE. */ -#ifndef _UAPI_VC4_DRM_H_ -#define _UAPI_VC4_DRM_H_ +#ifndef _VC4_DRM_H_ +#define _VC4_DRM_H_ #include "drm.h" @@ -40,6 +40,8 @@ extern "C" { #define DRM_VC4_GET_PARAM 0x07 #define DRM_VC4_SET_TILING 0x08 #define DRM_VC4_GET_TILING 0x09 +#define DRM_VC4_LABEL_BO 0x0a +#define DRM_VC4_GEM_MADVISE 0x0b #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) @@ -51,6 +53,8 @@ extern "C" { #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) +#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) +#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) struct drm_vc4_submit_rcl_surface { __u32 hindex; /* Handle index, or ~0 if not present. */ @@ -153,6 +157,16 @@ struct drm_vc4_submit_cl { __u32 pad:24; #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) +/* By default, the kernel gets to choose the order that the tiles are + * rendered in. If this is set, then the tiles will be rendered in a + * raster order, with the right-to-left vs left-to-right and + * top-to-bottom vs bottom-to-top dictated by + * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping + * blits to be implemented using the 3D engine. + */ +#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) +#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) +#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) __u32 flags; /* Returned value of the seqno of this render job (for the @@ -292,6 +306,8 @@ struct drm_vc4_get_hang_state { #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 +#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 +#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 struct drm_vc4_get_param { __u32 param; @@ -311,8 +327,33 @@ struct drm_vc4_set_tiling { __u64 modifier; }; +/** + * struct drm_vc4_label_bo - Attach a name to a BO for debug purposes. + */ +struct drm_vc4_label_bo { + __u32 handle; + __u32 len; + __u64 name; +}; + +/* + * States prefixed with '__' are internal states and cannot be passed to the + * DRM_IOCTL_VC4_GEM_MADVISE ioctl. + */ +#define VC4_MADV_WILLNEED 0 +#define VC4_MADV_DONTNEED 1 +#define __VC4_MADV_PURGED 2 +#define __VC4_MADV_NOTSUPP 3 + +struct drm_vc4_gem_madvise { + __u32 handle; + __u32 madv; + __u32 retained; + __u32 pad; +}; + #if defined(__cplusplus) } #endif -#endif /* _UAPI_VC4_DRM_H_ */ +#endif /* _VC4_DRM_H_ */ -- cgit v1.2.3-54-g00ecf From 8d34bba212342ec0e187cd3602d01edba2d7ec26 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 8 Nov 2017 11:06:55 -0800 Subject: headers: Sync up some header guard changes from drm-next. This pulls in pieces of drm-next d65d31388a23 ("Merge tag 'drm-misc-next-fixes-2017-11-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next") Signed-off-by: Eric Anholt Reviewed-by: Emil Velikov --- include/drm/README | 4 ---- include/drm/mga_drm.h | 8 ++++++++ include/drm/nouveau_drm.h | 10 ++++++++++ include/drm/qxl_drm.h | 8 ++++++++ include/drm/r128_drm.h | 10 ++++++++++ include/drm/savage_drm.h | 10 ++++++++++ include/drm/sis_drm.h | 10 ++++++++++ include/drm/tegra_drm.h | 14 +++++++++++--- include/drm/via_drm.h | 8 ++++++++ include/drm/vmwgfx_drm.h | 9 +++++++++ 10 files changed, 84 insertions(+), 7 deletions(-) diff --git a/include/drm/README b/include/drm/README index 870b0b5b..47d80929 100644 --- a/include/drm/README +++ b/include/drm/README @@ -86,10 +86,6 @@ Outdated or Broken Headers This section contains a list of headers and the respective "issues" they might have relative to their kernel equivalent. -Nearly all headers: - - Missing extern C notation. -Status: Trivial. - Most UMS headers: - Not using fixed size integers - compat ioctls are broken. Status: ? diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h index b630e8fa..f54e7a2e 100644 --- a/include/drm/mga_drm.h +++ b/include/drm/mga_drm.h @@ -37,6 +37,10 @@ #include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (mga_sarea.h) */ @@ -416,4 +420,8 @@ typedef struct drm_mga_getparam { void *value; } drm_mga_getparam_t; +#if defined(__cplusplus) +} +#endif + #endif diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h index e418f9f3..542a732b 100644 --- a/include/drm/nouveau_drm.h +++ b/include/drm/nouveau_drm.h @@ -27,6 +27,12 @@ #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + struct drm_nouveau_channel_alloc { uint32_t fb_ctxdma_handle; uint32_t tt_ctxdma_handle; @@ -207,4 +213,8 @@ struct drm_nouveau_sarea { #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 #define DRM_NOUVEAU_GEM_INFO 0x44 +#if defined(__cplusplus) +} +#endif + #endif /* __NOUVEAU_DRM_H__ */ diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h index 1e331a86..ccd841b1 100644 --- a/include/drm/qxl_drm.h +++ b/include/drm/qxl_drm.h @@ -27,6 +27,10 @@ #include #include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. * @@ -149,4 +153,8 @@ struct drm_qxl_alloc_surf { DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\ struct drm_qxl_alloc_surf) +#if defined(__cplusplus) +} +#endif + #endif diff --git a/include/drm/r128_drm.h b/include/drm/r128_drm.h index ede78ff9..bf431a02 100644 --- a/include/drm/r128_drm.h +++ b/include/drm/r128_drm.h @@ -33,6 +33,12 @@ #ifndef __R128_DRM_H__ #define __R128_DRM_H__ +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + /* WARNING: If you change any of these defines, make sure to change the * defines in the X server file (r128_sarea.h) */ @@ -323,4 +329,8 @@ typedef struct drm_r128_getparam { void *value; } drm_r128_getparam_t; +#if defined(__cplusplus) +} +#endif + #endif diff --git a/include/drm/savage_drm.h b/include/drm/savage_drm.h index f7a75eff..26f387b7 100644 --- a/include/drm/savage_drm.h +++ b/include/drm/savage_drm.h @@ -26,6 +26,12 @@ #ifndef __SAVAGE_DRM_H__ #define __SAVAGE_DRM_H__ +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + #ifndef __SAVAGE_SAREA_DEFINES__ #define __SAVAGE_SAREA_DEFINES__ @@ -207,4 +213,8 @@ union drm_savage_cmd_header { } clear1; /* SAVAGE_CMD_CLEAR data */ }; +#if defined(__cplusplus) +} +#endif + #endif diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h index 30f7b382..8e51bb9a 100644 --- a/include/drm/sis_drm.h +++ b/include/drm/sis_drm.h @@ -27,6 +27,12 @@ #ifndef __SIS_DRM_H__ #define __SIS_DRM_H__ +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + /* SiS specific ioctls */ #define NOT_USED_0_3 #define DRM_SIS_FB_ALLOC 0x04 @@ -64,4 +70,8 @@ typedef struct { unsigned int offset, size; } drm_sis_fb_t; +#if defined(__cplusplus) +} +#endif + #endif /* __SIS_DRM_H__ */ diff --git a/include/drm/tegra_drm.h b/include/drm/tegra_drm.h index 7c0fe0ed..12f9bf84 100644 --- a/include/drm/tegra_drm.h +++ b/include/drm/tegra_drm.h @@ -20,10 +20,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef _UAPI_TEGRA_DRM_H_ -#define _UAPI_TEGRA_DRM_H_ +#ifndef _TEGRA_DRM_H_ +#define _TEGRA_DRM_H_ -#include +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) @@ -198,4 +202,8 @@ struct drm_tegra_gem_get_flags { #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) +#if defined(__cplusplus) +} +#endif + #endif diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h index 182f8792..8b69e819 100644 --- a/include/drm/via_drm.h +++ b/include/drm/via_drm.h @@ -26,6 +26,10 @@ #include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + /* WARNING: These defines must be the same as what the Xserver uses. * if you change them, you must change the defines in the Xserver. */ @@ -272,4 +276,8 @@ typedef struct drm_via_dmablit { drm_via_blitsync_t sync; } drm_via_dmablit_t; +#if defined(__cplusplus) +} +#endif + #endif /* _VIA_DRM_H_ */ diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h index 5b68b4d1..d325a410 100644 --- a/include/drm/vmwgfx_drm.h +++ b/include/drm/vmwgfx_drm.h @@ -30,6 +30,10 @@ #include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + #define DRM_VMW_MAX_SURFACE_FACES 6 #define DRM_VMW_MAX_MIP_LEVELS 24 @@ -1087,4 +1091,9 @@ union drm_vmw_extended_context_arg { enum drm_vmw_extended_context req; struct drm_vmw_context_arg rep; }; + +#if defined(__cplusplus) +} +#endif + #endif -- cgit v1.2.3-54-g00ecf From 8affa2699587b8239135b75ade24ee837df1606c Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 8 Nov 2017 11:09:54 -0800 Subject: headers: Sync up some comment spelling and whitespace fixes from drm-next. This pulls in pieces of drm-next d65d31388a23 ("Merge tag 'drm-misc-next-fixes-2017-11-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next") Signed-off-by: Eric Anholt Reviewed-by: Emil Velikov --- include/drm/mga_drm.h | 2 +- include/drm/qxl_drm.h | 2 +- include/drm/savage_drm.h | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h index f54e7a2e..7035a664 100644 --- a/include/drm/mga_drm.h +++ b/include/drm/mga_drm.h @@ -111,7 +111,7 @@ extern "C" { */ #define MGA_NR_SAREA_CLIPRECTS 8 -/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 +/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 * regions, subject to a minimum region size of (1<<16) == 64k. * * Clients may subdivide regions internally, but when sharing between diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h index ccd841b1..a520123b 100644 --- a/include/drm/qxl_drm.h +++ b/include/drm/qxl_drm.h @@ -34,7 +34,7 @@ extern "C" { /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. * - * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel + * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel * compatibility Keep fields aligned to their size */ diff --git a/include/drm/savage_drm.h b/include/drm/savage_drm.h index 26f387b7..1a91234e 100644 --- a/include/drm/savage_drm.h +++ b/include/drm/savage_drm.h @@ -35,7 +35,7 @@ extern "C" { #ifndef __SAVAGE_SAREA_DEFINES__ #define __SAVAGE_SAREA_DEFINES__ -/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 +/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 * regions, subject to a minimum region size of (1<<16) == 64k. * * Clients may subdivide regions internally, but when sharing between @@ -69,10 +69,10 @@ typedef struct _drm_savage_sarea { #define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 #define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 -#define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) -#define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) -#define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) -#define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) +#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) +#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) +#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) +#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) #define SAVAGE_DMA_PCI 1 #define SAVAGE_DMA_AGP 3 -- cgit v1.2.3-54-g00ecf From 59808bcacd48f4168c3c1093b4616c2ee039b5a1 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 8 Nov 2017 11:18:47 -0800 Subject: headers: Sync up mga_drm.h from drm-next. The kernel started using the struct from drm.h instead of the typedef. Signed-off-by: Eric Anholt Reviewed-by: Emil Velikov --- include/drm/README | 4 ---- include/drm/mga_drm.h | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/include/drm/README b/include/drm/README index 47d80929..6e12ca4d 100644 --- a/include/drm/README +++ b/include/drm/README @@ -100,10 +100,6 @@ i915_drm.h - Missing PARAMS - HAS_POOLED_EU, MIN_EU_IN_POOL CONTEXT_PARAM_NO_ERROR_CAPTURE Status: Trivial. -mga_drm.h - - Typo fix, use struct over typedef. -Status: Trivial. - nouveau_drm.h - Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs, enums, using stdint.h over the __u* types. diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h index 7035a664..79300111 100644 --- a/include/drm/mga_drm.h +++ b/include/drm/mga_drm.h @@ -252,7 +252,7 @@ typedef struct _drm_mga_sarea { #define DRM_MGA_DMA_BOOTSTRAP 0x0c #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) +#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock) #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) #define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) #define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) -- cgit v1.2.3-54-g00ecf From f696698e0249a8b65ef7d1a0c484633fc3f286ef Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 8 Nov 2017 11:22:55 -0800 Subject: headers: Sync up kernel changes to use kernel types instead of stdint.h. This pulls in pieces of drm-next d65d31388a23 ("Merge tag 'drm-misc-next-fixes-2017-11-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next") Signed-off-by: Eric Anholt Reviewed-by: Emil Velikov --- include/drm/README | 9 +--- include/drm/nouveau_drm.h | 84 +++++++++++++++--------------- include/drm/qxl_drm.h | 72 +++++++++++++------------- include/drm/radeon_drm.h | 128 +++++++++++++++++++++++----------------------- 4 files changed, 144 insertions(+), 149 deletions(-) diff --git a/include/drm/README b/include/drm/README index 6e12ca4d..042cfb17 100644 --- a/include/drm/README +++ b/include/drm/README @@ -102,19 +102,14 @@ Status: Trivial. nouveau_drm.h - Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs, -enums, using stdint.h over the __u* types. +enums Status: ? -qxl_drm.h - - Using the stdint.h uint*_t over the respective __u* ones -Status: Trivial. - r128_drm.h - Broken compat ioctls. radeon_drm.h - - Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls, -using stdint types. + - Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls - Both kernel and libdrm: missing padding - drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ? Status: ? diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h index 542a732b..cb077821 100644 --- a/include/drm/nouveau_drm.h +++ b/include/drm/nouveau_drm.h @@ -111,34 +111,34 @@ struct drm_nouveau_setparam { #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 struct drm_nouveau_gem_info { - uint32_t handle; - uint32_t domain; - uint64_t size; - uint64_t offset; - uint64_t map_handle; - uint32_t tile_mode; - uint32_t tile_flags; + __u32 handle; + __u32 domain; + __u64 size; + __u64 offset; + __u64 map_handle; + __u32 tile_mode; + __u32 tile_flags; }; struct drm_nouveau_gem_new { struct drm_nouveau_gem_info info; - uint32_t channel_hint; - uint32_t align; + __u32 channel_hint; + __u32 align; }; #define NOUVEAU_GEM_MAX_BUFFERS 1024 struct drm_nouveau_gem_pushbuf_bo_presumed { - uint32_t valid; - uint32_t domain; - uint64_t offset; + __u32 valid; + __u32 domain; + __u64 offset; }; struct drm_nouveau_gem_pushbuf_bo { - uint64_t user_priv; - uint32_t handle; - uint32_t read_domains; - uint32_t write_domains; - uint32_t valid_domains; + __u64 user_priv; + __u32 handle; + __u32 read_domains; + __u32 write_domains; + __u32 valid_domains; struct drm_nouveau_gem_pushbuf_bo_presumed presumed; }; @@ -147,47 +147,47 @@ struct drm_nouveau_gem_pushbuf_bo { #define NOUVEAU_GEM_RELOC_OR (1 << 2) #define NOUVEAU_GEM_MAX_RELOCS 1024 struct drm_nouveau_gem_pushbuf_reloc { - uint32_t reloc_bo_index; - uint32_t reloc_bo_offset; - uint32_t bo_index; - uint32_t flags; - uint32_t data; - uint32_t vor; - uint32_t tor; + __u32 reloc_bo_index; + __u32 reloc_bo_offset; + __u32 bo_index; + __u32 flags; + __u32 data; + __u32 vor; + __u32 tor; }; #define NOUVEAU_GEM_MAX_PUSH 512 struct drm_nouveau_gem_pushbuf_push { - uint32_t bo_index; - uint32_t pad; - uint64_t offset; - uint64_t length; + __u32 bo_index; + __u32 pad; + __u64 offset; + __u64 length; }; struct drm_nouveau_gem_pushbuf { - uint32_t channel; - uint32_t nr_buffers; - uint64_t buffers; - uint32_t nr_relocs; - uint32_t nr_push; - uint64_t relocs; - uint64_t push; - uint32_t suffix0; - uint32_t suffix1; - uint64_t vram_available; - uint64_t gart_available; + __u32 channel; + __u32 nr_buffers; + __u64 buffers; + __u32 nr_relocs; + __u32 nr_push; + __u64 relocs; + __u64 push; + __u32 suffix0; + __u32 suffix1; + __u64 vram_available; + __u64 gart_available; }; #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 struct drm_nouveau_gem_cpu_prep { - uint32_t handle; - uint32_t flags; + __u32 handle; + __u32 flags; }; struct drm_nouveau_gem_cpu_fini { - uint32_t handle; + __u32 handle; }; enum nouveau_bus_type { diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h index a520123b..38a0dbdf 100644 --- a/include/drm/qxl_drm.h +++ b/include/drm/qxl_drm.h @@ -52,14 +52,14 @@ extern "C" { #define DRM_QXL_ALLOC_SURF 0x06 struct drm_qxl_alloc { - uint32_t size; - uint32_t handle; /* 0 is an invalid handle */ + __u32 size; + __u32 handle; /* 0 is an invalid handle */ }; struct drm_qxl_map { - uint64_t offset; /* use for mmap system call */ - uint32_t handle; - uint32_t pad; + __u64 offset; /* use for mmap system call */ + __u32 handle; + __u32 pad; }; /* @@ -72,59 +72,59 @@ struct drm_qxl_map { #define QXL_RELOC_TYPE_SURF 2 struct drm_qxl_reloc { - uint64_t src_offset; /* offset into src_handle or src buffer */ - uint64_t dst_offset; /* offset in dest handle */ - uint32_t src_handle; /* dest handle to compute address from */ - uint32_t dst_handle; /* 0 if to command buffer */ - uint32_t reloc_type; - uint32_t pad; + __u64 src_offset; /* offset into src_handle or src buffer */ + __u64 dst_offset; /* offset in dest handle */ + __u32 src_handle; /* dest handle to compute address from */ + __u32 dst_handle; /* 0 if to command buffer */ + __u32 reloc_type; + __u32 pad; }; struct drm_qxl_command { - uint64_t command; /* void* */ - uint64_t relocs; /* struct drm_qxl_reloc* */ - uint32_t type; - uint32_t command_size; - uint32_t relocs_num; - uint32_t pad; + __u64 command; /* void* */ + __u64 relocs; /* struct drm_qxl_reloc* */ + __u32 type; + __u32 command_size; + __u32 relocs_num; + __u32 pad; }; /* XXX: call it drm_qxl_commands? */ struct drm_qxl_execbuffer { - uint32_t flags; /* for future use */ - uint32_t commands_num; - uint64_t commands; /* struct drm_qxl_command* */ + __u32 flags; /* for future use */ + __u32 commands_num; + __u64 commands; /* struct drm_qxl_command* */ }; struct drm_qxl_update_area { - uint32_t handle; - uint32_t top; - uint32_t left; - uint32_t bottom; - uint32_t right; - uint32_t pad; + __u32 handle; + __u32 top; + __u32 left; + __u32 bottom; + __u32 right; + __u32 pad; }; #define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */ #define QXL_PARAM_MAX_RELOCS 2 struct drm_qxl_getparam { - uint64_t param; - uint64_t value; + __u64 param; + __u64 value; }; /* these are one bit values */ struct drm_qxl_clientcap { - uint32_t index; - uint32_t pad; + __u32 index; + __u32 pad; }; struct drm_qxl_alloc_surf { - uint32_t format; - uint32_t width; - uint32_t height; - int32_t stride; - uint32_t handle; - uint32_t pad; + __u32 format; + __u32 width; + __u32 height; + __s32 stride; + __u32 handle; + __u32 pad; }; #define DRM_IOCTL_QXL_ALLOC \ diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index f09cc04c..a1e385d6 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h @@ -797,9 +797,9 @@ typedef struct drm_radeon_surface_free { #define RADEON_GEM_DOMAIN_VRAM 0x4 struct drm_radeon_gem_info { - uint64_t gart_size; - uint64_t vram_size; - uint64_t vram_visible; + __u64 gart_size; + __u64 vram_size; + __u64 vram_visible; }; #define RADEON_GEM_NO_BACKING_STORE (1 << 0) @@ -811,11 +811,11 @@ struct drm_radeon_gem_info { #define RADEON_GEM_NO_CPU_ACCESS (1 << 4) struct drm_radeon_gem_create { - uint64_t size; - uint64_t alignment; - uint32_t handle; - uint32_t initial_domain; - uint32_t flags; + __u64 size; + __u64 alignment; + __u32 handle; + __u32 initial_domain; + __u32 flags; }; /* @@ -829,10 +829,10 @@ struct drm_radeon_gem_create { #define RADEON_GEM_USERPTR_REGISTER (1 << 3) struct drm_radeon_gem_userptr { - uint64_t addr; - uint64_t size; - uint32_t flags; - uint32_t handle; + __u64 addr; + __u64 size; + __u32 flags; + __u32 handle; }; #define RADEON_TILING_MACRO 0x1 @@ -855,72 +855,72 @@ struct drm_radeon_gem_userptr { #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf struct drm_radeon_gem_set_tiling { - uint32_t handle; - uint32_t tiling_flags; - uint32_t pitch; + __u32 handle; + __u32 tiling_flags; + __u32 pitch; }; struct drm_radeon_gem_get_tiling { - uint32_t handle; - uint32_t tiling_flags; - uint32_t pitch; + __u32 handle; + __u32 tiling_flags; + __u32 pitch; }; struct drm_radeon_gem_mmap { - uint32_t handle; - uint32_t pad; - uint64_t offset; - uint64_t size; - uint64_t addr_ptr; + __u32 handle; + __u32 pad; + __u64 offset; + __u64 size; + __u64 addr_ptr; }; struct drm_radeon_gem_set_domain { - uint32_t handle; - uint32_t read_domains; - uint32_t write_domain; + __u32 handle; + __u32 read_domains; + __u32 write_domain; }; struct drm_radeon_gem_wait_idle { - uint32_t handle; - uint32_t pad; + __u32 handle; + __u32 pad; }; struct drm_radeon_gem_busy { - uint32_t handle; - uint32_t domain; + __u32 handle; + __u32 domain; }; struct drm_radeon_gem_pread { /** Handle for the object being read. */ - uint32_t handle; - uint32_t pad; + __u32 handle; + __u32 pad; /** Offset into the object to read from */ - uint64_t offset; + __u64 offset; /** Length of data to read */ - uint64_t size; + __u64 size; /** Pointer to write the data into. */ /* void *, but pointers are not 32/64 compatible */ - uint64_t data_ptr; + __u64 data_ptr; }; struct drm_radeon_gem_pwrite { /** Handle for the object being written to. */ - uint32_t handle; - uint32_t pad; + __u32 handle; + __u32 pad; /** Offset into the object to write to */ - uint64_t offset; + __u64 offset; /** Length of data to write */ - uint64_t size; + __u64 size; /** Pointer to read the data from. */ /* void *, but pointers are not 32/64 compatible */ - uint64_t data_ptr; + __u64 data_ptr; }; /* Sets or returns a value associated with a buffer. */ struct drm_radeon_gem_op { - uint32_t handle; /* buffer */ - uint32_t op; /* RADEON_GEM_OP_* */ - uint64_t value; /* input or return value */ + __u32 handle; /* buffer */ + __u32 op; /* RADEON_GEM_OP_* */ + __u64 value; /* input or return value */ }; #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 @@ -940,11 +940,11 @@ struct drm_radeon_gem_op { #define RADEON_VM_PAGE_SNOOPED (1 << 4) struct drm_radeon_gem_va { - uint32_t handle; - uint32_t operation; - uint32_t vm_id; - uint32_t flags; - uint64_t offset; + __u32 handle; + __u32 operation; + __u32 vm_id; + __u32 flags; + __u64 offset; }; #define RADEON_CHUNK_ID_RELOCS 0x01 @@ -966,29 +966,29 @@ struct drm_radeon_gem_va { /* 0 = normal, + = higher priority, - = lower priority */ struct drm_radeon_cs_chunk { - uint32_t chunk_id; - uint32_t length_dw; - uint64_t chunk_data; + __u32 chunk_id; + __u32 length_dw; + __u64 chunk_data; }; /* drm_radeon_cs_reloc.flags */ #define RADEON_RELOC_PRIO_MASK (0xf << 0) struct drm_radeon_cs_reloc { - uint32_t handle; - uint32_t read_domains; - uint32_t write_domain; - uint32_t flags; + __u32 handle; + __u32 read_domains; + __u32 write_domain; + __u32 flags; }; struct drm_radeon_cs { - uint32_t num_chunks; - uint32_t cs_id; - /* this points to uint64_t * which point to cs chunks */ - uint64_t chunks; + __u32 num_chunks; + __u32 cs_id; + /* this points to __u64 * which point to cs chunks */ + __u64 chunks; /* updates to the limits after this CS ioctl */ - uint64_t gart_limit; - uint64_t vram_limit; + __u64 gart_limit; + __u64 vram_limit; }; #define RADEON_INFO_DEVICE_ID 0x00 @@ -1047,9 +1047,9 @@ struct drm_radeon_cs { #define RADEON_INFO_GPU_RESET_COUNTER 0x26 struct drm_radeon_info { - uint32_t request; - uint32_t pad; - uint64_t value; + __u32 request; + __u32 pad; + __u64 value; }; /* Those correspond to the tile index to use, this is to explicitly state -- cgit v1.2.3-54-g00ecf From 21885876af4c2c8a51547bb81d6d10413eed71d5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 8 Nov 2017 11:31:20 -0800 Subject: headers: Drop outdated node about a delta in drm_mode.h. Fixed in 9433b702fc16 ("headers: Sync drm{,_mode}.h with the kernel") Signed-off-by: Eric Anholt Reviewed-by: Emil Velikov --- include/drm/README | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/drm/README b/include/drm/README index 042cfb17..5b518ddf 100644 --- a/include/drm/README +++ b/include/drm/README @@ -91,11 +91,6 @@ Most UMS headers: Status: ? Promote to fixed size ints, which match the current (32bit) ones. - -drm_mode.h - - Missing DPI encode/connector pair. -Status: Trivial. - i915_drm.h - Missing PARAMS - HAS_POOLED_EU, MIN_EU_IN_POOL CONTEXT_PARAM_NO_ERROR_CAPTURE Status: Trivial. -- cgit v1.2.3-54-g00ecf From 864219425d9cf2fb4df677aa93bd54051ebcafc2 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 9 Nov 2017 23:30:00 -0500 Subject: amdgpu: Add functions to disable suites and tests. Suits are diasbled based on hooks they provide (e.g incompatible ASIC or missing blocks). Single tests are diasbled explicitly. Suit or test can be forced to execute even if disabled by adding -f flag after specifying suit [test] ids. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/amdgpu_test.c | 157 +++++++++++++++++++++++++++++++++++++++------ tests/amdgpu/amdgpu_test.h | 31 +++++++++ 2 files changed, 170 insertions(+), 18 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index a82d9ab1..68ec5d39 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -50,6 +50,16 @@ #include "amdgpu_test.h" +/* Test suit names */ +#define BASIC_TESTS_STR "Basic Tests" +#define BO_TESTS_STR "BO Tests" +#define CS_TESTS_STR "CS Tests" +#define VCE_TESTS_STR "VCE Tests" +#define VCN_TESTS_STR "VCN Tests" +#define UVD_ENC_TESTS_STR "UVD ENC Tests" +#define DEADLOCK_TESTS_STR "Deadlock Tests" +#define VM_TESTS_STR "VM Tests" + /** * Open handles for amdgpu devices * @@ -62,49 +72,49 @@ int open_render_node = 0; /* By default run most tests on primary node */ /** The table of all known test suites to run */ static CU_SuiteInfo suites[] = { { - .pName = "Basic Tests", + .pName = BASIC_TESTS_STR, .pInitFunc = suite_basic_tests_init, .pCleanupFunc = suite_basic_tests_clean, .pTests = basic_tests, }, { - .pName = "BO Tests", + .pName = BO_TESTS_STR, .pInitFunc = suite_bo_tests_init, .pCleanupFunc = suite_bo_tests_clean, .pTests = bo_tests, }, { - .pName = "CS Tests", + .pName = CS_TESTS_STR, .pInitFunc = suite_cs_tests_init, .pCleanupFunc = suite_cs_tests_clean, .pTests = cs_tests, }, { - .pName = "VCE Tests", + .pName = VCE_TESTS_STR, .pInitFunc = suite_vce_tests_init, .pCleanupFunc = suite_vce_tests_clean, .pTests = vce_tests, }, { - .pName = "VCN Tests", + .pName = VCN_TESTS_STR, .pInitFunc = suite_vcn_tests_init, .pCleanupFunc = suite_vcn_tests_clean, .pTests = vcn_tests, }, { - .pName = "UVD ENC Tests", + .pName = UVD_ENC_TESTS_STR, .pInitFunc = suite_uvd_enc_tests_init, .pCleanupFunc = suite_uvd_enc_tests_clean, .pTests = uvd_enc_tests, }, { - .pName = "Deadlock Tests", + .pName = DEADLOCK_TESTS_STR, .pInitFunc = suite_deadlock_tests_init, .pCleanupFunc = suite_deadlock_tests_clean, .pTests = deadlock_tests, }, { - .pName = "VM Tests", + .pName = VM_TESTS_STR, .pInitFunc = suite_vm_tests_init, .pCleanupFunc = suite_vm_tests_clean, .pTests = vm_tests, @@ -113,23 +123,99 @@ static CU_SuiteInfo suites[] = { CU_SUITE_INFO_NULL, }; +typedef CU_BOOL (*active__stat_func)(void); + +typedef struct Suites_Active_Status { + char* pName; + active__stat_func pActive; +}Suites_Active_Status; + +static CU_BOOL always_active() +{ + return CU_TRUE; +} + +static Suites_Active_Status suites_active_stat[] = { + { + .pName = BASIC_TESTS_STR, + .pActive = always_active, + }, + { + .pName = BO_TESTS_STR, + .pActive = always_active, + }, + { + .pName = CS_TESTS_STR, + .pActive = always_active, + }, + { + .pName = VCE_TESTS_STR, + .pActive = always_active, + }, + { + .pName = VCN_TESTS_STR, + .pActive = always_active, + }, + { + .pName = UVD_ENC_TESTS_STR, + .pActive = always_active, + }, + { + .pName = DEADLOCK_TESTS_STR, + .pActive = always_active, + }, + { + .pName = VM_TESTS_STR, + .pActive = always_active, + }, +}; + -/** Display information about all suites and their tests */ +/* + * Display information about all suites and their tests + * + * NOTE: Must be run after registry is initialized and suites registered. + */ static void display_test_suites(void) { int iSuite; int iTest; + CU_pSuite pSuite = NULL; + CU_pTest pTest = NULL; printf("Suites\n"); for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) { - printf("Suite id = %d: Name '%s'\n", - iSuite + 1, suites[iSuite].pName); + + pSuite = CU_get_suite_by_index((unsigned int) iSuite + 1, + CU_get_registry()); + + if (!pSuite) { + fprintf(stderr, "Invalid suite id : %d\n", iSuite + 1); + continue; + } + + printf("Suite id = %d: Name '%s status: %s'\n", + iSuite + 1, suites[iSuite].pName, + pSuite->fActive ? "ENABLED" : "DISABLED"); + + for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL; iTest++) { - printf(" Test id %d: Name: '%s'\n", iTest + 1, - suites[iSuite].pTests[iTest].pName); + + pTest = CU_get_test_by_index((unsigned int) iTest + 1, + pSuite); + + if (!pTest) { + fprintf(stderr, "Invalid test id : %d\n", iTest + 1); + continue; + } + + printf("Test id %d: Name: '%s status: %s'\n", iTest + 1, + suites[iSuite].pTests[iTest].pName, + pSuite->fActive && pTest->fActive ? + "ENABLED" : "DISABLED"); } } } @@ -137,7 +223,7 @@ static void display_test_suites(void) /** Help string for command line parameters */ static const char usage[] = - "Usage: %s [-hlpr] [<-s > [-t ]] " + "Usage: %s [-hlpr] [<-s > [-t ] [-f]] " "[-b [-d ]]\n" "where:\n" " l - Display all suites and their tests\n" @@ -145,9 +231,10 @@ static const char usage[] = " b - Specify device's PCI bus id to run tests\n" " d - Specify device's PCI device id to run tests (optional)\n" " p - Display information of AMDGPU devices in system\n" + " f - Force executing inactive suite or test\n" " h - Display this help\n"; /** Specified options strings for getopt */ -static const char options[] = "hlrps:t:b:d:"; +static const char options[] = "hlrps:t:b:d:f"; /* Open AMD devices. * Return the number of AMD device openned. @@ -312,6 +399,18 @@ static int amdgpu_find_device(uint8_t bus, uint16_t dev) return -1; } +static void amdgpu_disable_suits() +{ + int i; + int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]); + + /* Set active status for suits based on their policies */ + for (i = 0; i < size; ++i) + if (amdgpu_set_suite_active(suites_active_stat[i].pName, + suites_active_stat[i].pActive())) + fprintf(stderr, "suit deactivation failed - %s\n", CU_get_error_msg()); +} + /* The main() function for setting up and running the tests. * Returns a CUE_SUCCESS on successful running, another * CUnit error code on failure. @@ -328,6 +427,8 @@ int main(int argc, char **argv) CU_pSuite pSuite = NULL; CU_pTest pTest = NULL; int test_device_index; + int display_list = 0; + int force_run = 0; for (i = 0; i < MAX_CARDS_SUPPORTED; i++) drm_amdgpu[i] = -1; @@ -338,8 +439,8 @@ int main(int argc, char **argv) while ((c = getopt(argc, argv, options)) != -1) { switch (c) { case 'l': - display_test_suites(); - exit(EXIT_SUCCESS); + display_list = 1; + break; case 's': suite_id = atoi(optarg); break; @@ -358,6 +459,9 @@ int main(int argc, char **argv) case 'r': open_render_node = 1; break; + case 'f': + force_run = 1; + break; case '?': case 'h': fprintf(stderr, usage, argv[0]); @@ -423,17 +527,33 @@ int main(int argc, char **argv) /* Run tests using the CUnit Basic interface */ CU_basic_set_mode(CU_BRM_VERBOSE); + /* Disable suits and individual tests based on misc. conditions */ + amdgpu_disable_suits(); + + if (display_list) { + display_test_suites(); + goto end; + } + if (suite_id != -1) { /* If user specify particular suite? */ pSuite = CU_get_suite_by_index((unsigned int) suite_id, CU_get_registry()); if (pSuite) { + + if (force_run) + CU_set_suite_active(pSuite, CU_TRUE); + if (test_id != -1) { /* If user specify test id */ pTest = CU_get_test_by_index( (unsigned int) test_id, pSuite); - if (pTest) + if (pTest) { + if (force_run) + CU_set_test_active(pTest, CU_TRUE); + CU_basic_run_test(pSuite, pTest); + } else { fprintf(stderr, "Invalid test id: %d\n", test_id); @@ -453,6 +573,7 @@ int main(int argc, char **argv) } else CU_basic_run_tests(); +end: CU_cleanup_registry(); amdgpu_close_devices(); return CU_get_error(); diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 4fffbc62..9ccc1ffd 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -296,4 +296,35 @@ amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1, return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list); } + +static inline CU_ErrorCode amdgpu_set_suite_active(const char *suit_name, + CU_BOOL active) +{ + CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suit_name), active); + + if (r != CUE_SUCCESS) + fprintf(stderr, "Failed to obtain suite %s\n", suit_name); + + return r; +} + +static inline CU_ErrorCode amdgpu_set_test_active(const char *suit_name, + const char *test_name, CU_BOOL active) +{ + CU_ErrorCode r; + CU_pSuite pSuite = CU_get_suite(suit_name); + + if (!pSuite) { + fprintf(stderr, "Failed to obtain suite %s\n", + suit_name); + return CUE_NOSUITE; + } + + r = CU_set_test_active(CU_get_test(pSuite, test_name), active); + if (r != CUE_SUCCESS) + fprintf(stderr, "Failed to obtain test %s\n", test_name); + + return r; +} + #endif /* #ifdef _AMDGPU_TEST_H_ */ -- cgit v1.2.3-54-g00ecf From 806d0803600000faecb4025d8e9c7490cb097c25 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 9 Nov 2017 23:30:01 -0500 Subject: amdgpu: Use new suite/test disabling functionality. Switch from disabling tests during run to using the new disable API. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/amdgpu_test.c | 14 ++++++-- tests/amdgpu/amdgpu_test.h | 15 ++++++++ tests/amdgpu/deadlock_tests.c | 8 +---- tests/amdgpu/uvd_enc_tests.c | 81 +++++++++++++++++-------------------------- tests/amdgpu/vce_tests.c | 65 +++++++++++++++++----------------- tests/amdgpu/vcn_tests.c | 74 +++++++++++++++++---------------------- 6 files changed, 123 insertions(+), 134 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 68ec5d39..91010dcc 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -150,15 +150,15 @@ static Suites_Active_Status suites_active_stat[] = { }, { .pName = VCE_TESTS_STR, - .pActive = always_active, + .pActive = suite_vce_tests_enable, }, { .pName = VCN_TESTS_STR, - .pActive = always_active, + .pActive = suite_vcn_tests_enable, }, { .pName = UVD_ENC_TESTS_STR, - .pActive = always_active, + .pActive = suite_uvd_enc_tests_enable, }, { .pName = DEADLOCK_TESTS_STR, @@ -409,6 +409,14 @@ static void amdgpu_disable_suits() if (amdgpu_set_suite_active(suites_active_stat[i].pName, suites_active_stat[i].pActive())) fprintf(stderr, "suit deactivation failed - %s\n", CU_get_error_msg()); + + /* Explicitly disable specific tests due to known bugs or preferences */ + /* + * BUG: Compute ring stalls and never recovers when the address is + * written after the command already submitted + */ + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, "compute ring block test", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); } /* The main() function for setting up and running the tests. diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 9ccc1ffd..dd236edc 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -99,6 +99,11 @@ int suite_vce_tests_init(); */ int suite_vce_tests_clean(); +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_vce_tests_enable(void); + /** * Tests in vce test suite */ @@ -114,6 +119,11 @@ int suite_vcn_tests_init(); + */ int suite_vcn_tests_clean(); +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_vcn_tests_enable(void); + /** + * Tests in vcn test suite + */ @@ -129,6 +139,11 @@ int suite_uvd_enc_tests_init(); */ int suite_uvd_enc_tests_clean(); +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_uvd_enc_tests_enable(void); + /** * Tests in uvd enc test suite */ diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index e23d903f..f5c4552a 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -119,13 +119,7 @@ int suite_deadlock_tests_clean(void) CU_TestInfo deadlock_tests[] = { { "gfx ring block test", amdgpu_deadlock_gfx }, - - /* - * BUG: Compute ring stalls and never recovers when the address is - * written after the command already submitted - */ - /* { "compute ring block test", amdgpu_deadlock_compute }, */ - + { "compute ring block test", amdgpu_deadlock_compute }, CU_TEST_INFO_NULL, }; diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index bbda1312..bed8494a 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -79,7 +79,6 @@ static void amdgpu_cs_uvd_enc_session_init(void); static void amdgpu_cs_uvd_enc_encode(void); static void amdgpu_cs_uvd_enc_destroy(void); -static bool uvd_enc_support(void); CU_TestInfo uvd_enc_tests[] = { { "UVD ENC create", amdgpu_cs_uvd_enc_create }, @@ -89,6 +88,27 @@ CU_TestInfo uvd_enc_tests[] = { CU_TEST_INFO_NULL, }; +CU_BOOL suite_uvd_enc_tests_enable(void) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info); + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + if (!info.available_rings) + printf("\n\nThe ASIC NOT support UVD ENC, suite disabled.\n"); + + return (r == 0 && (info.available_rings ? CU_TRUE : CU_FALSE)); +} + + int suite_uvd_enc_tests_init(void) { int r; @@ -100,11 +120,6 @@ int suite_uvd_enc_tests_init(void) family_id = device_handle->info.family_id; - if (!uvd_enc_support()) { - printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will pass\n"); - return CUE_SUCCESS; - } - r = amdgpu_cs_ctx_create(device_handle, &context_handle); if (r) return CUE_SINIT_FAILED; @@ -123,28 +138,18 @@ int suite_uvd_enc_tests_clean(void) { int r; - if (!uvd_enc_support()) { - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; - } else { - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; return CUE_SUCCESS; } @@ -240,26 +245,10 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); } -static bool uvd_enc_support(void) -{ - int r; - struct drm_amdgpu_info_hw_ip info; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info); - - if (r) - return false; - else - return (info.available_rings?true:false); -} - static void amdgpu_cs_uvd_enc_create(void) { int len, r; - if (!uvd_enc_support()) - return; - enc.width = 160; enc.height = 128; @@ -296,9 +285,6 @@ static void amdgpu_cs_uvd_enc_session_init(void) { int len, r; - if (!uvd_enc_support()) - return; - len = 0; memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); len += sizeof(uve_session_info) / 4; @@ -354,8 +340,6 @@ static void amdgpu_cs_uvd_enc_encode(void) vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; cpb_size = vbuf_size * 10; - if (!uvd_enc_support()) - return; num_resources = 0; alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM); @@ -489,9 +473,6 @@ static void amdgpu_cs_uvd_enc_destroy(void) struct amdgpu_uvd_enc_bo sw_ctx; int len, r; - if (!uvd_enc_support()) - return; - num_resources = 0; resources[num_resources++] = ib_handle; diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c index cf44c132..75821bbb 100644 --- a/tests/amdgpu/vce_tests.c +++ b/tests/amdgpu/vce_tests.c @@ -88,6 +88,27 @@ CU_TestInfo vce_tests[] = { CU_TEST_INFO_NULL, }; + +CU_BOOL suite_vce_tests_enable(void) +{ + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + family_id = device_handle->info.family_id; + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { + printf("\n\nThe ASIC NOT support VCE, suite disabled\n"); + return CU_FALSE; + } + + return CU_TRUE; +} + int suite_vce_tests_init(void) { int r; @@ -106,11 +127,6 @@ int suite_vce_tests_init(void) family_id = device_handle->info.family_id; vce_harvest_config = device_handle->info.vce_harvest_config; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); - return CUE_SUCCESS; - } - r = amdgpu_cs_ctx_create(device_handle, &context_handle); if (r) return CUE_SINIT_FAILED; @@ -131,24 +147,18 @@ int suite_vce_tests_clean(void) { int r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } else { - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; return CUE_SUCCESS; } @@ -248,9 +258,6 @@ static void amdgpu_cs_vce_create(void) unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; int len, r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - enc.width = vce_create[6]; enc.height = vce_create[7]; @@ -444,9 +451,6 @@ static void amdgpu_cs_vce_encode(void) unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; int i, r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; cpb_size = vbuf_size * 10; num_resources = 0; @@ -525,9 +529,6 @@ static void amdgpu_cs_vce_destroy(void) { int len, r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - num_resources = 0; alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); resources[num_resources++] = enc.fb[0].handle; diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c index 2b1696dd..53a2d08e 100644 --- a/tests/amdgpu/vcn_tests.c +++ b/tests/amdgpu/vcn_tests.c @@ -82,6 +82,27 @@ CU_TestInfo vcn_tests[] = { CU_TEST_INFO_NULL, }; +CU_BOOL suite_vcn_tests_enable(void) +{ + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + family_id = device_handle->info.family_id; + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + + if (family_id < AMDGPU_FAMILY_RV) { + printf("\n\nThe ASIC NOT support VCN, suite disabled\n"); + return CU_FALSE; + } + + return CU_TRUE; +} + int suite_vcn_tests_init(void) { int r; @@ -93,11 +114,6 @@ int suite_vcn_tests_init(void) family_id = device_handle->info.family_id; - if (family_id < AMDGPU_FAMILY_RV) { - printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n"); - return CUE_SUCCESS; - } - r = amdgpu_cs_ctx_create(device_handle, &context_handle); if (r) return CUE_SINIT_FAILED; @@ -116,26 +132,18 @@ int suite_vcn_tests_clean(void) { int r; - if (family_id < AMDGPU_FAMILY_RV) { - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } else { - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; - return CUE_SUCCESS; + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; } static int submit(unsigned ndw, unsigned ip) @@ -244,9 +252,6 @@ static void amdgpu_cs_vcn_dec_create(void) struct amdgpu_vcn_bo msg_buf; int len, r; - if (family_id < AMDGPU_FAMILY_RV) - return; - num_resources = 0; alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT); resources[num_resources++] = msg_buf.handle; @@ -282,9 +287,6 @@ static void amdgpu_cs_vcn_dec_decode(void) int size, len, i, r; uint8_t *dec; - if (family_id < AMDGPU_FAMILY_RV) - return; - size = 4*1024; /* msg */ size += 4*1024; /* fb */ size += 4096; /*it_scaling_table*/ @@ -355,9 +357,6 @@ static void amdgpu_cs_vcn_dec_destroy(void) struct amdgpu_vcn_bo msg_buf; int len, r; - if (family_id < AMDGPU_FAMILY_RV) - return; - num_resources = 0; alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT); resources[num_resources++] = msg_buf.handle; @@ -387,24 +386,15 @@ static void amdgpu_cs_vcn_dec_destroy(void) static void amdgpu_cs_vcn_enc_create(void) { - if (family_id < AMDGPU_FAMILY_RV) - return; - /* TODO */ } static void amdgpu_cs_vcn_enc_encode(void) { - if (family_id < AMDGPU_FAMILY_RV) - return; - /* TODO */ } static void amdgpu_cs_vcn_enc_destroy(void) { - if (family_id < AMDGPU_FAMILY_RV) - return; - /* TODO */ } -- cgit v1.2.3-54-g00ecf From 818a0d4245801edd9a85ea95429bac4eb6ec2ef8 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 9 Nov 2017 23:30:02 -0500 Subject: amdgpu: Move memory alloc tests in bo suite. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/basic_tests.c | 49 ---------------------------------------------- tests/amdgpu/bo_tests.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 18bcf919..e7f48e39 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -44,7 +44,6 @@ static uint32_t minor_version; static uint32_t family_id; static void amdgpu_query_info_test(void); -static void amdgpu_memory_alloc(void); static void amdgpu_command_submission_gfx(void); static void amdgpu_command_submission_compute(void); static void amdgpu_command_submission_multi_fence(void); @@ -58,7 +57,6 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type); CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, - { "Memory alloc Test", amdgpu_memory_alloc }, { "Userptr Test", amdgpu_userptr_test }, { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, { "Command submission Test (Compute)", amdgpu_command_submission_compute }, @@ -277,53 +275,6 @@ static void amdgpu_query_info_test(void) CU_ASSERT_EQUAL(r, 0); } -static void amdgpu_memory_alloc(void) -{ - amdgpu_bo_handle bo; - amdgpu_va_handle va_handle; - uint64_t bo_mc; - int r; - - /* Test visible VRAM */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test invisible VRAM */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_NO_CPU_ACCESS, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test GART Cacheable */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, - 0, &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test GART USWC */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_CPU_GTT_USWC, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); -} - static void amdgpu_command_submission_gfx_separate_ibs(void) { amdgpu_context_handle context_handle; diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c index 74b5e77b..45451960 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -46,6 +46,7 @@ static amdgpu_va_handle va_handle; static void amdgpu_bo_export_import(void); static void amdgpu_bo_metadata(void); static void amdgpu_bo_map_unmap(void); +static void amdgpu_memory_alloc(void); CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, @@ -53,6 +54,7 @@ CU_TestInfo bo_tests[] = { { "Metadata", amdgpu_bo_metadata }, #endif { "CPU map/unmap", amdgpu_bo_map_unmap }, + { "Memory alloc Test", amdgpu_memory_alloc }, CU_TEST_INFO_NULL, }; @@ -195,3 +197,50 @@ static void amdgpu_bo_map_unmap(void) r = amdgpu_bo_cpu_unmap(buffer_handle); CU_ASSERT_EQUAL(r, 0); } + +static void amdgpu_memory_alloc(void) +{ + amdgpu_bo_handle bo; + amdgpu_va_handle va_handle; + uint64_t bo_mc; + int r; + + /* Test visible VRAM */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + &bo_mc, &va_handle); + + r = gpu_mem_free(bo, va_handle, bo_mc, 4096); + CU_ASSERT_EQUAL(r, 0); + + /* Test invisible VRAM */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_NO_CPU_ACCESS, + &bo_mc, &va_handle); + + r = gpu_mem_free(bo, va_handle, bo_mc, 4096); + CU_ASSERT_EQUAL(r, 0); + + /* Test GART Cacheable */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, + 0, &bo_mc, &va_handle); + + r = gpu_mem_free(bo, va_handle, bo_mc, 4096); + CU_ASSERT_EQUAL(r, 0); + + /* Test GART USWC */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_CREATE_CPU_GTT_USWC, + &bo_mc, &va_handle); + + r = gpu_mem_free(bo, va_handle, bo_mc, 4096); + CU_ASSERT_EQUAL(r, 0); +} -- cgit v1.2.3-54-g00ecf From 9ad9b7e91ee8af621bb80bb80ecd0f76eba7c51c Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 13 Nov 2017 12:01:42 -0500 Subject: amdgpu: Add memory over allocation test. Allocates 1 TB of memory. Test is disabled by default since it's triggers OOM killer. v2: FIx the test to only alloc the BO and assert if return value not equal to -ENOMEM and remove test disable on start. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/bo_tests.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c index 45451960..53e76c1b 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -47,6 +47,7 @@ static void amdgpu_bo_export_import(void); static void amdgpu_bo_metadata(void); static void amdgpu_bo_map_unmap(void); static void amdgpu_memory_alloc(void); +static void amdgpu_mem_fail_alloc(void); CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, @@ -55,6 +56,7 @@ CU_TestInfo bo_tests[] = { #endif { "CPU map/unmap", amdgpu_bo_map_unmap }, { "Memory alloc Test", amdgpu_memory_alloc }, + { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, CU_TEST_INFO_NULL, }; @@ -244,3 +246,25 @@ static void amdgpu_memory_alloc(void) r = gpu_mem_free(bo, va_handle, bo_mc, 4096); CU_ASSERT_EQUAL(r, 0); } + +static void amdgpu_mem_fail_alloc(void) +{ + amdgpu_bo_handle bo; + int r; + struct amdgpu_bo_alloc_request req = {0}; + amdgpu_bo_handle buf_handle; + + /* Test impossible mem allocation, 1TB */ + req.alloc_size = 0xE8D4A51000; + req.phys_alignment = 4096; + req.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; + req.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; + + r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); + CU_ASSERT_EQUAL(r, -ENOMEM); + + if (!r) { + r = amdgpu_bo_free(bo); + CU_ASSERT_EQUAL(r, 0); + } +} -- cgit v1.2.3-54-g00ecf From 18ffe485cdfa41d48b6f2d3080cb990d28c27d57 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 14 Nov 2017 09:02:48 -0500 Subject: amdgpu: Disable deadlock test suite for Vega 10 The test stalls the CP, until RCA is done the test is disabled to not disrupt regression testing. Signed-off-by: Andrey Grodzovsky --- tests/amdgpu/amdgpu_test.c | 2 +- tests/amdgpu/amdgpu_test.h | 5 +++++ tests/amdgpu/deadlock_tests.c | 19 +++++++++++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 91010dcc..ee64152e 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -162,7 +162,7 @@ static Suites_Active_Status suites_active_stat[] = { }, { .pName = DEADLOCK_TESTS_STR, - .pActive = always_active, + .pActive = suite_deadlock_tests_enable, }, { .pName = VM_TESTS_STR, diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index dd236edc..414fcb81 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -159,6 +159,11 @@ int suite_deadlock_tests_init(); */ int suite_deadlock_tests_clean(); +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_deadlock_tests_enable(void); + /** * Tests in uvd enc test suite */ diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index f5c4552a..84f4debe 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -36,6 +36,7 @@ #include "amdgpu_test.h" #include "amdgpu_drm.h" +#include "amdgpu_internal.h" #include @@ -87,6 +88,24 @@ static void amdgpu_deadlock_helper(unsigned ip_type); static void amdgpu_deadlock_gfx(void); static void amdgpu_deadlock_compute(void); +CU_BOOL suite_deadlock_tests_enable(void) +{ + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + + if (device_handle->info.family_id == AMDGPU_FAMILY_AI) { + printf("\n\nCurrently hangs the CP on this ASIC, deadlock suite disabled\n"); + return CU_FALSE; + } + + return CU_TRUE; +} + int suite_deadlock_tests_init(void) { struct amdgpu_gpu_info gpu_info = {0}; -- cgit v1.2.3-54-g00ecf From 0ab36dafaf818c35a258dac0c75b779ab2ae792b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 27 Nov 2017 13:38:29 -0600 Subject: Android: disable warnings causing errors AOSP master has changed the build default to -Werror making all the warnings errors. Override that with -Wno-error. Signed-off-by: Rob Herring --- Android.common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/Android.common.mk b/Android.common.mk index d487acb9..e3de1069 100644 --- a/Android.common.mk +++ b/Android.common.mk @@ -5,6 +5,7 @@ LOCAL_CFLAGS += \ -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 LOCAL_CFLAGS += \ + -Wno-error \ -Wno-unused-parameter \ -Wno-missing-field-initializers \ -Wno-pointer-arith \ -- cgit v1.2.3-54-g00ecf From 1a129004a82d557695fad1a7b9c37fe18b00c79f Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 24 Nov 2017 15:50:51 -0500 Subject: amdgpu: Switch amdgpu CS tests enabling to the new way. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/amdgpu_test.c | 2 +- tests/amdgpu/amdgpu_test.h | 5 ++++ tests/amdgpu/cs_tests.c | 64 +++++++++++++++++++++++----------------------- 3 files changed, 38 insertions(+), 33 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index ee64152e..e611276d 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -146,7 +146,7 @@ static Suites_Active_Status suites_active_stat[] = { }, { .pName = CS_TESTS_STR, - .pActive = always_active, + .pActive = suite_cs_tests_enable, }, { .pName = VCE_TESTS_STR, diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 414fcb81..3238e05f 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -84,6 +84,11 @@ int suite_cs_tests_init(); */ int suite_cs_tests_clean(); +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_cs_tests_enable(void); + /** * Tests in cs test suite */ diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 3b2f17db..4880b74f 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -66,6 +66,26 @@ CU_TestInfo cs_tests[] = { CU_TEST_INFO_NULL, }; +CU_BOOL suite_cs_tests_enable(void) +{ + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + family_id = device_handle->info.family_id; + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + + if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { + printf("\n\nThe ASIC NOT support UVD, suite disabled\n"); + return CU_FALSE; + } + + return CU_TRUE; +} + int suite_cs_tests_init(void) { amdgpu_bo_handle ib_result_handle; @@ -90,11 +110,6 @@ int suite_cs_tests_init(void) chip_rev = device_handle->info.chip_rev; chip_id = device_handle->info.chip_external_rev; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n"); - return CUE_SUCCESS; - } - r = amdgpu_cs_ctx_create(device_handle, &context_handle); if (r) return CUE_SINIT_FAILED; @@ -119,24 +134,18 @@ int suite_cs_tests_clean(void) { int r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } else { - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, + ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; return CUE_SUCCESS; } @@ -203,9 +212,6 @@ static void amdgpu_cs_uvd_create(void) void *msg; int i, r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - req.alloc_size = 4*1024; req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; @@ -277,9 +283,6 @@ static void amdgpu_cs_uvd_decode(void) uint8_t *ptr; int i, r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - req.alloc_size = 4*1024; /* msg */ req.alloc_size += 4*1024; /* fb */ if (family_id >= AMDGPU_FAMILY_VI) @@ -419,9 +422,6 @@ static void amdgpu_cs_uvd_destroy(void) void *msg; int i, r; - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) - return; - req.alloc_size = 4*1024; req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; -- cgit v1.2.3-54-g00ecf From aeab24aa9e074043965cf911f60a3736c4f6455d Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 27 Nov 2017 07:26:13 -0500 Subject: amdgpu: Dynamicly disable BO suite "Metadata" test. Disable the test instead of doing #ifdef 0 Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/amdgpu_test.c | 3 +++ tests/amdgpu/bo_tests.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index e611276d..50da17ca 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -417,6 +417,9 @@ static void amdgpu_disable_suits() */ if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, "compute ring block test", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); } /* The main() function for setting up and running the tests. diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c index 53e76c1b..24698bcb 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -51,9 +51,7 @@ static void amdgpu_mem_fail_alloc(void); CU_TestInfo bo_tests[] = { { "Export/Import", amdgpu_bo_export_import }, -#if 0 { "Metadata", amdgpu_bo_metadata }, -#endif { "CPU map/unmap", amdgpu_bo_map_unmap }, { "Memory alloc Test", amdgpu_memory_alloc }, { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, -- cgit v1.2.3-54-g00ecf From 1749d56ea00f350a74f662bdad82bcafa19889da Mon Sep 17 00:00:00 2001 From: David Mao Date: Tue, 28 Nov 2017 11:22:26 +0800 Subject: amdgpu: Adding amdgpu_cs_create_syncobj2 to create syncobj as signaled initially Signed-off-by: David Mao Reviewed-by: Christian König Signed-off-by: Alex Deucher --- amdgpu/amdgpu.h | 15 +++++++++++++++ amdgpu/amdgpu_cs.c | 10 ++++++++++ 2 files changed, 25 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index df85a24c..c95cb03c 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1341,6 +1341,21 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); */ const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); +/** + * Create kernel sync object + * + * \param dev - \c [in] device handle + * \param flags - \c [in] flags that affect creation + * \param syncobj - \c [out] sync object handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, + uint32_t flags, + uint32_t *syncobj); + /** * Create kernel sync object * diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index b9fc01e7..9e157a84 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -606,6 +606,16 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) return amdgpu_cs_unreference_sem(sem); } +int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, + uint32_t flags, + uint32_t *handle) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjCreate(dev->fd, flags, handle); +} + int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, uint32_t *handle) { -- cgit v1.2.3-54-g00ecf From f71e95108de9a414226b0421ae2af99902ea28a5 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 30 Nov 2017 15:52:50 +0100 Subject: amdgpu: Add amdgpu_cs_create_syncobj2 to amdgpu-symbol-check Fixes make check. Trivial. --- amdgpu/amdgpu-symbol-check | 1 + 1 file changed, 1 insertion(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index d476038b..59db3cfe 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -29,6 +29,7 @@ amdgpu_cs_chunk_fence_info_to_data amdgpu_cs_chunk_fence_to_dep amdgpu_cs_create_semaphore amdgpu_cs_create_syncobj +amdgpu_cs_create_syncobj2 amdgpu_cs_ctx_create amdgpu_cs_ctx_create2 amdgpu_cs_ctx_free -- cgit v1.2.3-54-g00ecf From bc21168fa924d3fc4a000492e861f50a1a135b25 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 24 Nov 2017 15:19:09 -0500 Subject: amdgpu: Add explicit dependency test. The test is as following: 1) Create context A & B 2) Send a command submission using context A which fires up a compute shader. 3) The shader wait a bit and then write a value to a memory location. 4) Send a command submission using context B which writes another value to the same memory location, but having an explicit dependency on the first command submission. 5) Wait with the CPU for both submissions to finish and inspect the written value. Test passes if the value seen in the memory location after both submissions is from command B. Signed-off-by: Andrey Grodzovsky Acked-by: Christian König --- tests/amdgpu/amdgpu_test.c | 18 ++++ tests/amdgpu/basic_tests.c | 264 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 282 insertions(+) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 50da17ca..8fa3399a 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -49,6 +49,7 @@ #include "CUnit/Basic.h" #include "amdgpu_test.h" +#include "amdgpu_internal.h" /* Test suit names */ #define BASIC_TESTS_STR "Basic Tests" @@ -401,9 +402,20 @@ static int amdgpu_find_device(uint8_t bus, uint16_t dev) static void amdgpu_disable_suits() { + amdgpu_device_handle device_handle; + uint32_t major_version, minor_version, family_id; int i; int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]); + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return; + + family_id = device_handle->info.family_id; + + if (amdgpu_device_deinitialize(device_handle)) + return; + /* Set active status for suits based on their policies */ for (i = 0; i < size; ++i) if (amdgpu_set_suite_active(suites_active_stat[i].pName, @@ -420,6 +432,12 @@ static void amdgpu_disable_suits() if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + + /* This test was ran on GFX8 and GFX9 only */ + if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); } /* The main() function for setting up and running the tests. diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index e7f48e39..a78cf521 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -50,6 +50,7 @@ static void amdgpu_command_submission_multi_fence(void); static void amdgpu_command_submission_sdma(void); static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); +static void amdgpu_sync_dependency_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); @@ -63,6 +64,7 @@ CU_TestInfo basic_tests[] = { { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, { "SW semaphore Test", amdgpu_semaphore_test }, + { "Sync dependency Test", amdgpu_sync_dependency_test }, CU_TEST_INFO_NULL, }; #define BUFFER_SIZE (8 * 1024) @@ -226,6 +228,60 @@ CU_TestInfo basic_tests[] = { */ # define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31) + +#define PKT3_CONTEXT_CONTROL 0x28 +#define CONTEXT_CONTROL_LOAD_ENABLE(x) (((unsigned)(x) & 0x1) << 31) +#define CONTEXT_CONTROL_LOAD_CE_RAM(x) (((unsigned)(x) & 0x1) << 28) +#define CONTEXT_CONTROL_SHADOW_ENABLE(x) (((unsigned)(x) & 0x1) << 31) + +#define PKT3_CLEAR_STATE 0x12 + +#define PKT3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 + +#define PACKET3_DISPATCH_DIRECT 0x15 + + +/* gfx 8 */ +#define mmCOMPUTE_PGM_LO 0x2e0c +#define mmCOMPUTE_PGM_RSRC1 0x2e12 +#define mmCOMPUTE_TMPRING_SIZE 0x2e18 +#define mmCOMPUTE_USER_DATA_0 0x2e40 +#define mmCOMPUTE_USER_DATA_1 0x2e41 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 +#define mmCOMPUTE_NUM_THREAD_X 0x2e07 + + + +#define SWAP_32(num) ((num>>24)&0xff) | \ + ((num<<8)&0xff0000) | \ + ((num>>8)&0xff00) | \ + ((num<<24)&0xff000000) + + +/* Shader code + * void main() +{ + + float x = some_input; + for (unsigned i = 0; i < 1000000; i++) + x = sin(x); + + u[0] = 42u; +} +*/ + +static uint32_t shader_bin[] = { + SWAP_32(0x800082be), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0x040085bf), + SWAP_32(0x02810281), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0xfcff84bf), + SWAP_32(0xff0083be), SWAP_32(0x00f00000), SWAP_32(0xc10082be), SWAP_32(0xaa02007e), + SWAP_32(0x000070e0), SWAP_32(0x00000080), SWAP_32(0x000081bf) +}; + +#define CODE_OFFSET 512 +#define DATA_OFFSET 1024 + + int suite_basic_tests_init(void) { struct amdgpu_gpu_info gpu_info = {0}; @@ -1386,3 +1442,211 @@ static void amdgpu_userptr_test(void) wait(NULL); } + +static void amdgpu_sync_dependency_test(void) +{ + amdgpu_context_handle context_handle[2]; + amdgpu_bo_handle ib_result_handle; + void *ib_result_cpu; + uint64_t ib_result_mc_address; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + struct amdgpu_cs_fence fence_status; + uint32_t expired; + int i, j, r, instance; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle; + static uint32_t *ptr; + uint64_t seq_no; + + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 8192, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, + &bo_list); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu; + i = 0; + + memcpy(ptr + CODE_OFFSET , shader_bin, sizeof(shader_bin)); + + /* Dispatch minimal init config and verify it's executed */ + ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1); + ptr[i++] = 0x80000000; + ptr[i++] = 0x80000000; + + ptr[i++] = PACKET3(PKT3_CLEAR_STATE, 0); + ptr[i++] = 0x80000000; + + + /* Program compute regs */ + ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); + ptr[i++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; + ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 8; + ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 40; + + + ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); + ptr[i++] = mmCOMPUTE_PGM_RSRC1 - PACKET3_SET_SH_REG_START; + /* + * 002c0040 COMPUTE_PGM_RSRC1 <- VGPRS = 0 + SGPRS = 1 + PRIORITY = 0 + FLOAT_MODE = 192 (0xc0) + PRIV = 0 + DX10_CLAMP = 1 + DEBUG_MODE = 0 + IEEE_MODE = 0 + BULKY = 0 + CDBG_USER = 0 + * + */ + ptr[i++] = 0x002c0040; + + + /* + * 00000010 COMPUTE_PGM_RSRC2 <- SCRATCH_EN = 0 + USER_SGPR = 8 + TRAP_PRESENT = 0 + TGID_X_EN = 0 + TGID_Y_EN = 0 + TGID_Z_EN = 0 + TG_SIZE_EN = 0 + TIDIG_COMP_CNT = 0 + EXCP_EN_MSB = 0 + LDS_SIZE = 0 + EXCP_EN = 0 + * + */ + ptr[i++] = 0x00000010; + + +/* + * 00000100 COMPUTE_TMPRING_SIZE <- WAVES = 256 (0x100) + WAVESIZE = 0 + * + */ + ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1); + ptr[i++] = mmCOMPUTE_TMPRING_SIZE - PACKET3_SET_SH_REG_START; + ptr[i++] = 0x00000100; + + ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); + ptr[i++] = mmCOMPUTE_USER_DATA_0 - PACKET3_SET_SH_REG_START; + ptr[i++] = 0xffffffff & (ib_result_mc_address + DATA_OFFSET * 4); + ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32; + + ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1); + ptr[i++] = mmCOMPUTE_RESOURCE_LIMITS - PACKET3_SET_SH_REG_START; + ptr[i++] = 0; + + ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3); + ptr[i++] = mmCOMPUTE_NUM_THREAD_X - PACKET3_SET_SH_REG_START; + ptr[i++] = 1; + ptr[i++] = 1; + ptr[i++] = 1; + + + /* Dispatch */ + ptr[i++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); + ptr[i++] = 1; + ptr[i++] = 1; + ptr[i++] = 1; + ptr[i++] = 0x00000045; /* DISPATCH DIRECT field */ + + + while (i & 7) + ptr[i++] = 0xffff1000; /* type3 nop packet */ + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address; + ib_info.size = i; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + ibs_request.fence_info.handle = NULL; + + r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + seq_no = ibs_request.seq_no; + + + + /* Prepare second command with dependency on the first */ + j = i; + ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3); + ptr[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + ptr[i++] = 0xfffffffc & ib_result_mc_address + DATA_OFFSET * 4; + ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32; + ptr[i++] = 99; + + while (i & 7) + ptr[i++] = 0xffff1000; /* type3 nop packet */ + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address + j * 4; + ib_info.size = i - j; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + ibs_request.fence_info.handle = NULL; + + ibs_request.number_of_dependencies = 1; + + ibs_request.dependencies = calloc(1, sizeof(*ibs_request.dependencies)); + ibs_request.dependencies[0].context = context_handle[1]; + ibs_request.dependencies[0].ip_instance = 0; + ibs_request.dependencies[0].ring = 0; + ibs_request.dependencies[0].fence = seq_no; + + + r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + + + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); + fence_status.context = context_handle[0]; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.ring = 0; + fence_status.fence = ibs_request.seq_no; + + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE,0, &expired); + CU_ASSERT_EQUAL(r, 0); + + /* Expect the second command to wait for shader to complete */ + CU_ASSERT_EQUAL(ptr[DATA_OFFSET], 99); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle[0]); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_free(context_handle[1]); + CU_ASSERT_EQUAL(r, 0); + + free(ibs_request.dependencies); +} -- cgit v1.2.3-54-g00ecf From 85c6b0b00ab894116880d2338776727ccff2d5c3 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 30 Nov 2017 18:28:01 +0100 Subject: amdgpu: Clean up amdgpu_parse_asic_ids error handling * Move error message printing into amdgpu_parse_asic_ids and make it return void * Print only "Invalid format" error message if parse_one_line returns -EINVAL * Use strerror instead of printing the (negative) error code in hex Acked-by: Slava Abramov Reviewed-by: Alex Deucher --- amdgpu/amdgpu_asic_id.c | 16 ++++++++++------ amdgpu/amdgpu_device.c | 6 +----- amdgpu/amdgpu_internal.h | 2 +- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c index e8218974..eb42bbc2 100644 --- a/amdgpu/amdgpu_asic_id.c +++ b/amdgpu/amdgpu_asic_id.c @@ -109,7 +109,7 @@ out: return r; } -int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) +void amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) { struct amdgpu_asic_id *asic_id_table; struct amdgpu_asic_id *id; @@ -126,7 +126,7 @@ int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) if (!fp) { fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE, strerror(errno)); - return -EINVAL; + return; } asic_id_table = calloc(table_max_size + 1, @@ -177,8 +177,6 @@ int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) line_num++; continue; } - fprintf(stderr, "Invalid format: %s: line %d: %s\n", - AMDGPU_ASIC_ID_TABLE, line_num, line); goto free; } @@ -201,6 +199,14 @@ int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) memset(id, 0, sizeof(struct amdgpu_asic_id)); free: + if (r == -EINVAL) { + fprintf(stderr, "Invalid format: %s: line %d: %s\n", + AMDGPU_ASIC_ID_TABLE, line_num, line); + } else if (r) { + fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n", + __func__, strerror(-r)); + } + free(line); if (r && asic_id_table) { @@ -215,6 +221,4 @@ close: fclose(fp); *p_asic_id_table = asic_id_table; - - return r; } diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 344e87ed..e7aaf4fc 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -280,11 +280,7 @@ int amdgpu_device_initialize(int fd, amdgpu_vamgr_init(&dev->vamgr, start, max, dev->dev_info.virtual_address_alignment); - r = amdgpu_parse_asic_ids(&dev->asic_ids); - if (r) { - fprintf(stderr, "%s: Cannot parse ASIC IDs, 0x%x.", - __func__, r); - } + amdgpu_parse_asic_ids(&dev->asic_ids); *major_version = dev->major_version; *minor_version = dev->minor_version; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index e26e5190..1aff7f8e 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -148,7 +148,7 @@ drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr); -drm_private int amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids); +drm_private void amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids); drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); -- cgit v1.2.3-54-g00ecf From 5219809a3223e0328ae43a8975bfd6bf713c9ef1 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Fri, 1 Dec 2017 16:59:38 +0100 Subject: amdgpu: Simplify error handling in parse_one_line * Move empty/commented line check before the strdup and return -EAGAIN directly * Initialize r = -EAGAIN and remove redundant assignments * Set r = -ENOMEM if last strdup fails, and remove redundant goto Acked-by: Slava Abramov Reviewed-by: Alex Deucher --- amdgpu/amdgpu_asic_id.c | 45 ++++++++++++++++----------------------------- 1 file changed, 16 insertions(+), 29 deletions(-) diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c index eb42bbc2..0b5f2962 100644 --- a/amdgpu/amdgpu_asic_id.c +++ b/amdgpu/amdgpu_asic_id.c @@ -45,63 +45,50 @@ static int parse_one_line(const char *line, struct amdgpu_asic_id *id) char *s_rid; char *s_name; char *endptr; - int r = 0; + int r = -EINVAL; + + /* ignore empty line and commented line */ + if (strlen(line) == 0 || line[0] == '#') + return -EAGAIN; buf = strdup(line); if (!buf) return -ENOMEM; - /* ignore empty line and commented line */ - if (strlen(line) == 0 || line[0] == '#') { - r = -EAGAIN; - goto out; - } - /* device id */ s_did = strtok_r(buf, ",", &saveptr); - if (!s_did) { - r = -EINVAL; + if (!s_did) goto out; - } id->did = strtol(s_did, &endptr, 16); - if (*endptr) { - r = -EINVAL; + if (*endptr) goto out; - } /* revision id */ s_rid = strtok_r(NULL, ",", &saveptr); - if (!s_rid) { - r = -EINVAL; + if (!s_rid) goto out; - } id->rid = strtol(s_rid, &endptr, 16); - if (*endptr) { - r = -EINVAL; + if (*endptr) goto out; - } /* marketing name */ s_name = strtok_r(NULL, ",", &saveptr); - if (!s_name) { - r = -EINVAL; + if (!s_name) goto out; - } + /* trim leading whitespaces or tabs */ while (isblank(*s_name)) s_name++; - if (strlen(s_name) == 0) { - r = -EINVAL; + if (strlen(s_name) == 0) goto out; - } id->marketing_name = strdup(s_name); - if (id->marketing_name == NULL) { - r = -EINVAL; - goto out; - } + if (id->marketing_name) + r = 0; + else + r = -ENOMEM; out: free(buf); -- cgit v1.2.3-54-g00ecf From f05a2b4cb1aedb906524718db8ba2e62383f3064 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 30 Nov 2017 18:52:06 +0100 Subject: amdgpu: Only remember the device's marketing name There's no point in keeping around the full table of marketing names, when amdgpu_get_marketing_name only ever returns the device's marketing name. Acked-by: Slava Abramov Reviewed-by: Alex Deucher --- amdgpu/Android.mk | 3 +- amdgpu/Makefile.am | 5 +-- amdgpu/amdgpu_asic_id.c | 88 ++++++++++++------------------------------------ amdgpu/amdgpu_device.c | 23 ++----------- amdgpu/amdgpu_internal.h | 11 ++---- 5 files changed, 28 insertions(+), 102 deletions(-) diff --git a/amdgpu/Android.mk b/amdgpu/Android.mk index ce273019..1f028d0b 100644 --- a/amdgpu/Android.mk +++ b/amdgpu/Android.mk @@ -11,8 +11,7 @@ LOCAL_SHARED_LIBRARIES := libdrm LOCAL_SRC_FILES := $(LIBDRM_AMDGPU_FILES) LOCAL_CFLAGS := \ - -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\" \ - -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' $(LIBDRM_TOP)/data/amdgpu.ids) + -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\" LOCAL_REQUIRED_MODULES := amdgpu.ids diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am index 66f6f676..a1b0d05c 100644 --- a/amdgpu/Makefile.am +++ b/amdgpu/Makefile.am @@ -31,10 +31,7 @@ AM_CFLAGS = \ -I$(top_srcdir)/include/drm libdrmdatadir = @libdrmdatadir@ -ASIC_ID_TABLE_NUM_ENTRIES := $(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' \ - $(top_srcdir)/data/amdgpu.ids) -AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\" \ - -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(ASIC_ID_TABLE_NUM_ENTRIES) +AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\" libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la libdrm_amdgpu_ladir = $(libdir) diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c index 0b5f2962..0c8925e5 100644 --- a/amdgpu/amdgpu_asic_id.c +++ b/amdgpu/amdgpu_asic_id.c @@ -38,11 +38,13 @@ #include "amdgpu_drm.h" #include "amdgpu_internal.h" -static int parse_one_line(const char *line, struct amdgpu_asic_id *id) +static int parse_one_line(struct amdgpu_device *dev, const char *line) { char *buf, *saveptr; char *s_did; + uint32_t did; char *s_rid; + uint32_t rid; char *s_name; char *endptr; int r = -EINVAL; @@ -60,19 +62,29 @@ static int parse_one_line(const char *line, struct amdgpu_asic_id *id) if (!s_did) goto out; - id->did = strtol(s_did, &endptr, 16); + did = strtol(s_did, &endptr, 16); if (*endptr) goto out; + if (did != dev->info.asic_id) { + r = -EAGAIN; + goto out; + } + /* revision id */ s_rid = strtok_r(NULL, ",", &saveptr); if (!s_rid) goto out; - id->rid = strtol(s_rid, &endptr, 16); + rid = strtol(s_rid, &endptr, 16); if (*endptr) goto out; + if (rid != dev->info.pci_rev_id) { + r = -EAGAIN; + goto out; + } + /* marketing name */ s_name = strtok_r(NULL, ",", &saveptr); if (!s_name) @@ -84,8 +96,8 @@ static int parse_one_line(const char *line, struct amdgpu_asic_id *id) if (strlen(s_name) == 0) goto out; - id->marketing_name = strdup(s_name); - if (id->marketing_name) + dev->marketing_name = strdup(s_name); + if (dev->marketing_name) r = 0; else r = -ENOMEM; @@ -96,17 +108,13 @@ out: return r; } -void amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) +void amdgpu_parse_asic_ids(struct amdgpu_device *dev) { - struct amdgpu_asic_id *asic_id_table; - struct amdgpu_asic_id *id; FILE *fp; char *line = NULL; size_t len = 0; ssize_t n; int line_num = 1; - size_t table_size = 0; - size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES; int r = 0; fp = fopen(AMDGPU_ASIC_ID_TABLE, "r"); @@ -116,13 +124,6 @@ void amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) return; } - asic_id_table = calloc(table_max_size + 1, - sizeof(struct amdgpu_asic_id)); - if (!asic_id_table) { - r = -ENOMEM; - goto close; - } - /* 1st valid line is file version */ while ((n = getline(&line, &len, fp)) != -1) { /* trim trailing newline */ @@ -140,52 +141,17 @@ void amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) } while ((n = getline(&line, &len, fp)) != -1) { - if (table_size > table_max_size) { - /* double table size */ - table_max_size *= 2; - id = realloc(asic_id_table, (table_max_size + 1) * - sizeof(struct amdgpu_asic_id)); - if (!id) { - r = -ENOMEM; - goto free; - } - asic_id_table = id; - } - - id = asic_id_table + table_size; - /* trim trailing newline */ if (line[n - 1] == '\n') line[n - 1] = '\0'; - r = parse_one_line(line, id); - if (r) { - if (r == -EAGAIN) { - line_num++; - continue; - } - goto free; - } + r = parse_one_line(dev, line); + if (r != -EAGAIN) + break; line_num++; - table_size++; } - if (table_size != table_max_size) { - id = realloc(asic_id_table, (table_size + 1) * - sizeof(struct amdgpu_asic_id)); - if (!id) { - r = -ENOMEM; - goto free; - } - asic_id_table = id; - } - - /* end of table */ - id = asic_id_table + table_size; - memset(id, 0, sizeof(struct amdgpu_asic_id)); - -free: if (r == -EINVAL) { fprintf(stderr, "Invalid format: %s: line %d: %s\n", AMDGPU_ASIC_ID_TABLE, line_num, line); @@ -195,17 +161,5 @@ free: } free(line); - - if (r && asic_id_table) { - while (table_size--) { - id = asic_id_table + table_size; - free(id->marketing_name); - } - free(asic_id_table); - asic_id_table = NULL; - } -close: fclose(fp); - - *p_asic_id_table = asic_id_table; } diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index e7aaf4fc..eb4b2745 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -130,7 +130,6 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - const struct amdgpu_asic_id *id; amdgpu_vamgr_deinit(&dev->vamgr_32); amdgpu_vamgr_deinit(&dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); @@ -140,12 +139,7 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev) close(dev->fd); if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd)) close(dev->flink_fd); - if (dev->asic_ids) { - for (id = dev->asic_ids; id->did; id++) - free(id->marketing_name); - - free(dev->asic_ids); - } + free(dev->marketing_name); free(dev); } @@ -280,7 +274,7 @@ int amdgpu_device_initialize(int fd, amdgpu_vamgr_init(&dev->vamgr, start, max, dev->dev_info.virtual_address_alignment); - amdgpu_parse_asic_ids(&dev->asic_ids); + amdgpu_parse_asic_ids(dev); *major_version = dev->major_version; *minor_version = dev->minor_version; @@ -306,16 +300,5 @@ int amdgpu_device_deinitialize(amdgpu_device_handle dev) const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) { - const struct amdgpu_asic_id *id; - - if (!dev->asic_ids) - return NULL; - - for (id = dev->asic_ids; id->did; id++) { - if ((id->did == dev->info.asic_id) && - (id->rid == dev->info.pci_rev_id)) - return id->marketing_name; - } - - return NULL; + return dev->marketing_name; } diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 1aff7f8e..3e044f11 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -69,12 +69,6 @@ struct amdgpu_va { struct amdgpu_bo_va_mgr *vamgr; }; -struct amdgpu_asic_id { - uint32_t did; - uint32_t rid; - char *marketing_name; -}; - struct amdgpu_device { atomic_t refcount; int fd; @@ -82,8 +76,7 @@ struct amdgpu_device { unsigned major_version; unsigned minor_version; - /** Lookup table of asic device id, revision id and marketing name */ - struct amdgpu_asic_id *asic_ids; + char *marketing_name; /** List of buffer handles. Protected by bo_table_mutex. */ struct util_hash_table *bo_handles; /** List of buffer GEM flink names. Protected by bo_table_mutex. */ @@ -148,7 +141,7 @@ drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr); -drm_private void amdgpu_parse_asic_ids(struct amdgpu_asic_id **asic_ids); +drm_private void amdgpu_parse_asic_ids(struct amdgpu_device *dev); drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); -- cgit v1.2.3-54-g00ecf From 47419a1497fa585ff74b41732b267356b9d5b949 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 5 Dec 2017 12:59:35 +0100 Subject: amdgpu.ids: Refresh from AMD 17.40 release Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Michel Dänzer --- data/amdgpu.ids | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/data/amdgpu.ids b/data/amdgpu.ids index f6c65dd9..1828e410 100644 --- a/data/amdgpu.ids +++ b/data/amdgpu.ids @@ -62,6 +62,7 @@ 67DF, C6, Radeon RX 570 Series 67DF, C7, AMD Radeon (TM) RX 480 Graphics 67DF, CF, AMD Radeon (TM) RX 470 Graphics +67DF, D7, Radeon(TM) RX 470 Graphics 67DF, E3, Radeon RX Series 67DF, E7, Radeon RX 580 Series 67DF, EF, Radeon RX 570 Series @@ -84,13 +85,16 @@ 67EF, C5, AMD Radeon (TM) RX 460 Graphics 67EF, C7, AMD Radeon (TM) RX Graphics 67EF, CF, AMD Radeon (TM) RX 460 Graphics +67EF, E0, Radeon RX 560 Series 67EF, E1, Radeon RX Series 67EF, E3, Radeon RX Series -67EF, E7, Radeon RX Series +67EF, E5, Radeon RX 560 Series 67EF, EF, AMD Radeon (TM) RX Graphics -67EF, FF, Radeon RX Series +67EF, FF, Radeon(TM) RX 460 Graphics 67FF, C0, AMD Radeon (TM) RX Graphics 67FF, C1, AMD Radeon (TM) RX Graphics +67FF, CF, Radeon RX 560 Series +67FF, EF, Radeon RX 560 Series 67FF, FF, Radeon RX 550 Series 6800, 0, AMD Radeon HD 7970M 6801, 0, AMD Radeon(TM) HD8970M @@ -122,6 +126,25 @@ 6837, 0, AMD Radeon HD7700 Series 683D, 0, AMD Radeon HD 7700 Series 683F, 0, AMD Radeon HD 7700 Series +6860, 00, Radeon Instinct MI25 +6860, 01, Radeon Pro V320 +6860, 02, Radeon Instinct MI25 +6860, 03, Radeon Pro V340 +6860, 04, Radeon Instinct MI25x2 +6861, 00, Radeon(TM) Pro WX9100 +6862, 00, Radeon Pro SSG +6863, 00, Radeon Vega Frontier Edition +6864, 03, Radeon Pro V340 +6864, 04, Instinct MI25x2 +6868, 00, Radeon(TM) Pro WX8100 +686C, 00, GLXT (Radeon Instinct MI25) MxGPU VFID +686C, 01, GLXT (Radeon Pro V320) MxGPU +686C, 02, GLXT (Radeon Instinct MI25) MxGPU +686C, 03, GLXT (Radeon Pro V340) MxGPU +686C, 04, GLXT (Radeon Instinct MI25x2) MxGPU +687F, C0, Radeon RX Vega +687F, C1, Radeon RX Vega +687F, C3, Radeon RX Vega 6900, 0, AMD Radeon R7 M260 6900, 81, AMD Radeon (TM) R7 M360 6900, 83, AMD Radeon (TM) R7 M340 @@ -139,8 +162,12 @@ 6939, F0, AMD Radeon R9 200 Series 6939, 0, AMD Radeon R9 200 Series 6939, F1, AMD Radeon (TM) R9 380 Series +6980, 00, Radeon Pro WX3100 6985, 00, AMD Radeon Pro WX3100 +6987, 80, AMD Embedded Radeon E9171 6995, 00, AMD Radeon Pro WX2100 +6997, 00, Radeon Pro WX2100 +699F, 81, AMD Embedded Radeon E9170 Series 699F, C0, Radeon 500 Series 699F, C3, Radeon 500 Series 699F, C7, Radeon RX 550 Series -- cgit v1.2.3-54-g00ecf From 7f2993948cc13b4f526cfe6b7fe272581a633928 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 12 Dec 2017 08:33:09 -0500 Subject: amdgpu: Remove dummy CU_ASSERT_EQUAL. Fixes test failure on rhel. Signed-off-by: Andrey Grodzovsky Reviewed-by: Qiang Yu --- tests/amdgpu/basic_tests.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index a78cf521..474a679c 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -1459,8 +1459,6 @@ static void amdgpu_sync_dependency_test(void) static uint32_t *ptr; uint64_t seq_no; - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]); CU_ASSERT_EQUAL(r, 0); r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]); -- cgit v1.2.3-54-g00ecf From 8d8ab9812ca6224c31d01f4664742b24a7364a67 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Fri, 15 Dec 2017 08:43:38 +0100 Subject: etnaviv: sync uapi header Import the etnaviv header changes from kernel commit 05916bed1 (drm-next) The drm_etnaviv_gem_submit structure was extended to include performance monitor requests. Also two new ioctls got added to be able to readout performance monitor domains and their signals. Signed-off-by: Christian Gmeiner Acked-by: Lucas Stach --- etnaviv/etnaviv_drm.h | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/etnaviv/etnaviv_drm.h b/etnaviv/etnaviv_drm.h index 76f6f78a..110cc73b 100644 --- a/etnaviv/etnaviv_drm.h +++ b/etnaviv/etnaviv_drm.h @@ -150,6 +150,19 @@ struct drm_etnaviv_gem_submit_bo { __u64 presumed; /* in/out, presumed buffer address */ }; +/* performance monitor request (pmr) */ +#define ETNA_PM_PROCESS_PRE 0x0001 +#define ETNA_PM_PROCESS_POST 0x0002 +struct drm_etnaviv_gem_submit_pmr { + __u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */ + __u8 domain; /* in, pm domain */ + __u8 pad; + __u16 signal; /* in, pm signal */ + __u32 sequence; /* in, sequence number */ + __u32 read_offset; /* in, offset from read_bo */ + __u32 read_idx; /* in, index of read_bo buffer */ +}; + /* Each cmdstream submit consists of a table of buffers involved, and * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. @@ -175,6 +188,9 @@ struct drm_etnaviv_gem_submit { __u64 stream; /* in, ptr to cmdstream */ __u32 flags; /* in, mask of ETNA_SUBMIT_x */ __s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */ + __u64 pmrs; /* in, ptr to array of submit_pmr's */ + __u32 nr_pmrs; /* in, number of submit_pmr's */ + __u32 pad; }; /* The normal way to synchronize with the GPU is just to CPU_PREP on @@ -210,6 +226,27 @@ struct drm_etnaviv_gem_wait { struct drm_etnaviv_timespec timeout; /* in */ }; +/* + * Performance Monitor (PM): + */ + +struct drm_etnaviv_pm_domain { + __u32 pipe; /* in */ + __u8 iter; /* in/out, select pm domain at index iter */ + __u8 id; /* out, id of domain */ + __u16 nr_signals; /* out, how many signals does this domain provide */ + char name[64]; /* out, name of domain */ +}; + +struct drm_etnaviv_pm_signal { + __u32 pipe; /* in */ + __u8 domain; /* in, pm domain index */ + __u8 pad; + __u16 iter; /* in/out, select pm source at index iter */ + __u16 id; /* out, id of signal */ + char name[64]; /* out, name of domain */ +}; + #define DRM_ETNAVIV_GET_PARAM 0x00 /* placeholder: #define DRM_ETNAVIV_SET_PARAM 0x01 @@ -222,7 +259,9 @@ struct drm_etnaviv_gem_wait { #define DRM_ETNAVIV_WAIT_FENCE 0x07 #define DRM_ETNAVIV_GEM_USERPTR 0x08 #define DRM_ETNAVIV_GEM_WAIT 0x09 -#define DRM_ETNAVIV_NUM_IOCTLS 0x0a +#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a +#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b +#define DRM_ETNAVIV_NUM_IOCTLS 0x0c #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) @@ -233,6 +272,8 @@ struct drm_etnaviv_gem_wait { #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) +#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain) +#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal) #if defined(__cplusplus) } -- cgit v1.2.3-54-g00ecf From 305c1d113ca26cadf695bd41eeed20cff79aa671 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Fri, 15 Dec 2017 08:43:39 +0100 Subject: etnaviv: add permon support Query all domains and their signals and provide it this information via struct etna_perfmon and the corresponding api functions. v2: - code style changes - etna_perfmon_create(..): add missing clean up in error case Signed-off-by: Christian Gmeiner Reviewed-by: Lucas Stach --- etnaviv/Makefile.sources | 1 + etnaviv/etnaviv-symbol-check | 4 + etnaviv/etnaviv_drmif.h | 11 +++ etnaviv/etnaviv_perfmon.c | 189 +++++++++++++++++++++++++++++++++++++++++++ etnaviv/etnaviv_priv.h | 21 +++++ 5 files changed, 226 insertions(+) create mode 100644 etnaviv/etnaviv_perfmon.c diff --git a/etnaviv/Makefile.sources b/etnaviv/Makefile.sources index 52580567..0eb73783 100644 --- a/etnaviv/Makefile.sources +++ b/etnaviv/Makefile.sources @@ -3,6 +3,7 @@ LIBDRM_ETNAVIV_FILES := \ etnaviv_gpu.c \ etnaviv_bo.c \ etnaviv_bo_cache.c \ + etnaviv_perfmon.c \ etnaviv_pipe.c \ etnaviv_cmd_stream.c \ etnaviv_drm.h \ diff --git a/etnaviv/etnaviv-symbol-check b/etnaviv/etnaviv-symbol-check index 0e2030e4..bd95b459 100755 --- a/etnaviv/etnaviv-symbol-check +++ b/etnaviv/etnaviv-symbol-check @@ -42,6 +42,10 @@ etna_cmd_stream_flush etna_cmd_stream_flush2 etna_cmd_stream_finish etna_cmd_stream_reloc +etna_perfmon_create +etna_perfmon_del +etna_perfmon_get_dom_by_name +etna_perfmon_get_sig_by_name EOF done) diff --git a/etnaviv/etnaviv_drmif.h b/etnaviv/etnaviv_drmif.h index 87704acd..949b9b62 100644 --- a/etnaviv/etnaviv_drmif.h +++ b/etnaviv/etnaviv_drmif.h @@ -35,6 +35,9 @@ struct etna_pipe; struct etna_gpu; struct etna_device; struct etna_cmd_stream; +struct etna_perfmon; +struct etna_perfmon_domain; +struct etna_perfmon_signal; enum etna_pipe_id { ETNA_PIPE_3D = 0, @@ -190,4 +193,12 @@ struct etna_reloc { void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r); +/* performance monitoring functions: + */ + +struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe); +void etna_perfmon_del(struct etna_perfmon *perfmon); +struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name); +struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name); + #endif /* ETNAVIV_DRMIF_H_ */ diff --git a/etnaviv/etnaviv_perfmon.c b/etnaviv/etnaviv_perfmon.c new file mode 100644 index 00000000..aa5130a6 --- /dev/null +++ b/etnaviv/etnaviv_perfmon.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2017 Etnaviv Project + * Copyright (C) 2017 Zodiac Inflight Innovations + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Christian Gmeiner + */ + +#ifdef HAVE_CONFIG_H +# include +#endif + +#include "etnaviv_priv.h" + +static int etna_perfmon_query_signals(struct etna_perfmon *pm, struct etna_perfmon_domain *dom) +{ + struct etna_device *dev = pm->pipe->gpu->dev; + struct drm_etnaviv_pm_signal req = { + .pipe = pm->pipe->id, + .domain = dom->id + }; + + do { + struct etna_perfmon_signal *sig; + int ret; + + ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_SIG, &req, sizeof(req)); + if (ret) + break; + + sig = calloc(1, sizeof(*sig)); + if (!sig) + return -ENOMEM; + + INFO_MSG("perfmon signal:"); + INFO_MSG("id = %d", req.id); + INFO_MSG("name = %s", req.name); + + sig->domain = dom; + sig->signal = req.id; + strncpy(sig->name, req.name, sizeof(sig->name)); + list_addtail(&sig->head, &dom->signals); + } while (req.iter != 0xffff); + + return 0; +} + +static int etna_perfmon_query_domains(struct etna_perfmon *pm) +{ + struct etna_device *dev = pm->pipe->gpu->dev; + struct drm_etnaviv_pm_domain req = { + .pipe = pm->pipe->id + }; + + do { + struct etna_perfmon_domain *dom; + int ret; + + ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_DOM, &req, sizeof(req)); + if (ret) + break; + + dom = calloc(1, sizeof(*dom)); + if (!dom) + return -ENOMEM; + + list_inithead(&dom->signals); + dom->id = req.id; + strncpy(dom->name, req.name, sizeof(dom->name)); + list_addtail(&dom->head, &pm->domains); + + INFO_MSG("perfmon domain:"); + INFO_MSG("id = %d", req.id); + INFO_MSG("name = %s", req.name); + INFO_MSG("nr_signals = %d", req.nr_signals); + + /* Query all available signals for this domain. */ + if (req.nr_signals > 0) { + ret = etna_perfmon_query_signals(pm, dom); + if (ret) + return ret; + } + } while (req.iter != 0xff); + + return 0; +} + +static void etna_perfmon_free_signals(struct etna_perfmon_domain *dom) +{ + struct etna_perfmon_signal *sig, *next; + + LIST_FOR_EACH_ENTRY_SAFE(sig, next, &dom->signals, head) { + list_del(&sig->head); + free(sig); + } +} + +static void etna_perfmon_free_domains(struct etna_perfmon *pm) +{ + struct etna_perfmon_domain *dom, *next; + + LIST_FOR_EACH_ENTRY_SAFE(dom, next, &pm->domains, head) { + etna_perfmon_free_signals(dom); + list_del(&dom->head); + free(dom); + } +} + +struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe) +{ + struct etna_perfmon *pm; + int ret; + + pm = calloc(1, sizeof(*pm)); + if (!pm) { + ERROR_MSG("allocation failed"); + return NULL; + } + + list_inithead(&pm->domains); + pm->pipe = pipe; + + /* query all available domains and sources for this device */ + ret = etna_perfmon_query_domains(pm); + if (ret) + goto fail; + + return pm; + +fail: + etna_perfmon_del(pm); + return NULL; +} + +void etna_perfmon_del(struct etna_perfmon *pm) +{ + if (!pm) + return; + + etna_perfmon_free_domains(pm); + free(pm); +} + +struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name) +{ + struct etna_perfmon_domain *dom; + + if (pm) { + LIST_FOR_EACH_ENTRY(dom, &pm->domains, head) { + if (!strcmp(dom->name, name)) + return dom; + } + } + + return NULL; +} + +struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name) +{ + struct etna_perfmon_signal *signal; + + if (dom) { + LIST_FOR_EACH_ENTRY(signal, &dom->signals, head) { + if (!strcmp(signal->name, name)) + return signal; + } + } + + return NULL; +} diff --git a/etnaviv/etnaviv_priv.h b/etnaviv/etnaviv_priv.h index 1334ba3f..7b289b61 100644 --- a/etnaviv/etnaviv_priv.h +++ b/etnaviv/etnaviv_priv.h @@ -151,6 +151,27 @@ struct etna_cmd_stream_priv { void *reset_notify_priv; }; +struct etna_perfmon { + struct list_head domains; + struct etna_pipe *pipe; +}; + +struct etna_perfmon_domain +{ + struct list_head head; + struct list_head signals; + uint8_t id; + char name[64]; +}; + +struct etna_perfmon_signal +{ + struct list_head head; + struct etna_perfmon_domain *domain; + uint8_t signal; + char name[64]; +}; + #define ALIGN(v,a) (((v) + (a) - 1) & ~((a) - 1)) #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) -- cgit v1.2.3-54-g00ecf From 6a6b7432bfe94f8047b688fd6875ad93d153c6d0 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Fri, 15 Dec 2017 08:43:40 +0100 Subject: etnaviv: support performance monitor requests Add etna_cmd_stream_perf(..) to submit perform requests. Userspace can submit pmrs via submit ioctl to sample perfmon signals. v3: - mark perfmon bos as RW Signed-off-by: Christian Gmeiner Reviewed-by: Lucas Stach --- etnaviv/etnaviv-symbol-check | 1 + etnaviv/etnaviv_cmd_stream.c | 20 ++++++++++++++++++++ etnaviv/etnaviv_drmif.h | 12 ++++++++++++ etnaviv/etnaviv_priv.h | 4 ++++ 4 files changed, 37 insertions(+) diff --git a/etnaviv/etnaviv-symbol-check b/etnaviv/etnaviv-symbol-check index bd95b459..bc509615 100755 --- a/etnaviv/etnaviv-symbol-check +++ b/etnaviv/etnaviv-symbol-check @@ -41,6 +41,7 @@ etna_cmd_stream_timestamp etna_cmd_stream_flush etna_cmd_stream_flush2 etna_cmd_stream_finish +etna_cmd_stream_perf etna_cmd_stream_reloc etna_perfmon_create etna_perfmon_del diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c index 8d0e8135..e8c58cd5 100644 --- a/etnaviv/etnaviv_cmd_stream.c +++ b/etnaviv/etnaviv_cmd_stream.c @@ -105,6 +105,7 @@ void etna_cmd_stream_del(struct etna_cmd_stream *stream) free(stream->buffer); free(priv->submit.relocs); + free(priv->submit.pmrs); free(priv); } @@ -115,6 +116,7 @@ static void reset_buffer(struct etna_cmd_stream *stream) stream->offset = 0; priv->submit.nr_bos = 0; priv->submit.nr_relocs = 0; + priv->submit.nr_pmrs = 0; priv->nr_bos = 0; if (priv->reset_notify) @@ -191,6 +193,8 @@ static void flush(struct etna_cmd_stream *stream, int in_fence_fd, .nr_bos = priv->submit.nr_bos, .relocs = VOID2U64(priv->submit.relocs), .nr_relocs = priv->submit.nr_relocs, + .pmrs = VOID2U64(priv->submit.pmrs), + .nr_pmrs = priv->submit.nr_pmrs, .stream = VOID2U64(stream->buffer), .stream_size = stream->offset * 4, /* in bytes */ }; @@ -260,3 +264,19 @@ void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_rel etna_cmd_stream_emit(stream, addr); } + +void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p) +{ + struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream); + struct drm_etnaviv_gem_submit_pmr *pmr; + uint32_t idx = APPEND(&priv->submit, pmrs); + + pmr = &priv->submit.pmrs[idx]; + + pmr->flags = p->flags; + pmr->sequence = p->sequence; + pmr->read_offset = p->offset; + pmr->read_idx = bo2idx(stream, p->bo, ETNA_SUBMIT_BO_READ | ETNA_SUBMIT_BO_WRITE); + pmr->domain = p->signal->domain->id; + pmr->signal = p->signal->signal; +} diff --git a/etnaviv/etnaviv_drmif.h b/etnaviv/etnaviv_drmif.h index 949b9b62..5a6bef8d 100644 --- a/etnaviv/etnaviv_drmif.h +++ b/etnaviv/etnaviv_drmif.h @@ -201,4 +201,16 @@ void etna_perfmon_del(struct etna_perfmon *perfmon); struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name); struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name); +struct etna_perf { +#define ETNA_PM_PROCESS_PRE 0x0001 +#define ETNA_PM_PROCESS_POST 0x0002 + uint32_t flags; + uint32_t sequence; + struct etna_perfmon_signal *signal; + struct etna_bo *bo; + uint32_t offset; +}; + +void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p); + #endif /* ETNAVIV_DRMIF_H_ */ diff --git a/etnaviv/etnaviv_priv.h b/etnaviv/etnaviv_priv.h index 7b289b61..e45d364c 100644 --- a/etnaviv/etnaviv_priv.h +++ b/etnaviv/etnaviv_priv.h @@ -140,6 +140,10 @@ struct etna_cmd_stream_priv { /* reloc's table: */ struct drm_etnaviv_gem_submit_reloc *relocs; uint32_t nr_relocs, max_relocs; + + /* perf's table: */ + struct drm_etnaviv_gem_submit_pmr *pmrs; + uint32_t nr_pmrs, max_pmrs; } submit; /* should have matching entries in submit.bos: */ -- cgit v1.2.3-54-g00ecf From 4f8e426884a51b6786459ea2505f1ce82a13a87c Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 15 Dec 2017 13:21:02 -0500 Subject: tests/amdgpu: Add return CUE_SUCCESS to suite_vcn_tests_clean. fixes: 806d0803600000faecb4025d8e9c7490cb097c25 (amdgpu: Use new suite/test disabling functionality.) bug: https://bugs.freedesktop.org/show_bug.cgi?id=104280 Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- tests/amdgpu/vcn_tests.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c index 53a2d08e..9224bc37 100644 --- a/tests/amdgpu/vcn_tests.c +++ b/tests/amdgpu/vcn_tests.c @@ -144,6 +144,8 @@ int suite_vcn_tests_clean(void) r = amdgpu_device_deinitialize(device_handle); if (r) return CUE_SCLEAN_FAILED; + + return CUE_SUCCESS; } static int submit(unsigned ndw, unsigned ip) -- cgit v1.2.3-54-g00ecf From 7d984e609470aa38d4c3f7d48e26fa763a03af13 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 15 Dec 2017 11:30:26 +0100 Subject: etnaviv: fix BO cache to properly work with different flags Currently if the oldest BO in a bucket has different flags than what we look for we'll miss the cache.Fix this by iterating over the cached BOs until we find the oldest one with matching flags. This improves the hit ratio for some of the buckets. Signed-off-by: Lucas Stach Reviewed-by: Philipp Zabel Reviewed-by: Christian Gmeiner --- etnaviv/etnaviv_bo_cache.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/etnaviv/etnaviv_bo_cache.c b/etnaviv/etnaviv_bo_cache.c index 8924651f..6208230d 100644 --- a/etnaviv/etnaviv_bo_cache.c +++ b/etnaviv/etnaviv_bo_cache.c @@ -124,20 +124,32 @@ static int is_idle(struct etna_bo *bo) static struct etna_bo *find_in_bucket(struct etna_bo_bucket *bucket, uint32_t flags) { - struct etna_bo *bo = NULL; + struct etna_bo *bo = NULL, *tmp; pthread_mutex_lock(&table_lock); - while (!LIST_IS_EMPTY(&bucket->list)) { - bo = LIST_ENTRY(struct etna_bo, bucket->list.next, list); - if (bo->flags == flags && is_idle(bo)) { - list_del(&bo->list); - break; + if (LIST_IS_EMPTY(&bucket->list)) + goto out_unlock; + + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &bucket->list, list) { + /* skip BOs with different flags */ + if (bo->flags != flags) + continue; + + /* check if the first BO with matching flags is idle */ + if (is_idle(bo)) { + list_delinit(&bo->list); + goto out_unlock; } - bo = NULL; + /* If the oldest BO is still busy, don't try younger ones */ break; } + + /* There was no matching buffer found */ + bo = NULL; + +out_unlock: pthread_mutex_unlock(&table_lock); return bo; -- cgit v1.2.3-54-g00ecf From 1abccedc4d18305e8c3e3dd00d3262c134ef1d44 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sun, 17 Dec 2017 00:27:09 +0100 Subject: drm: Add drmSyncobjReset & drmSyncobjSignal wrappers. anv already uses the ioctls but does not use libdrm, so these were not wrapped yet. Signed-off-by: Dave Airlie --- xf86drm.c | 26 ++++++++++++++++++++++++++ xf86drm.h | 2 ++ 2 files changed, 28 insertions(+) diff --git a/xf86drm.c b/xf86drm.c index c44621c1..deb76e4b 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -4247,3 +4247,29 @@ int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, *first_signaled = args.first_signaled; return ret; } + +int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count) +{ + struct drm_syncobj_array args; + int ret; + + memclear(args); + args.handles = (uintptr_t)handles; + args.count_handles = handle_count; + + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_RESET, &args); + return ret; +} + +int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count) +{ + struct drm_syncobj_array args; + int ret; + + memclear(args); + args.handles = (uintptr_t)handles; + args.count_handles = handle_count; + + ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_SIGNAL, &args); + return ret; +} diff --git a/xf86drm.h b/xf86drm.h index ea650eff..0dbf4941 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -863,6 +863,8 @@ extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd); extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, int64_t timeout_nsec, unsigned flags, uint32_t *first_signaled); +extern int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count); +extern int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count); #if defined(__cplusplus) } -- cgit v1.2.3-54-g00ecf From 5889f6ba1a250777ff8b6ba96a35dba3f02071ff Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sun, 17 Dec 2017 00:27:10 +0100 Subject: amdgpu: Add syncobj reset & signal wrappers. Signed-off-by: Dave Airlie --- amdgpu/amdgpu-symbol-check | 2 ++ amdgpu/amdgpu.h | 28 ++++++++++++++++++++++++++++ amdgpu/amdgpu_cs.c | 18 ++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 59db3cfe..3f298d13 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -45,6 +45,8 @@ amdgpu_cs_submit amdgpu_cs_submit_raw amdgpu_cs_syncobj_export_sync_file amdgpu_cs_syncobj_import_sync_file +amdgpu_cs_syncobj_reset +amdgpu_cs_syncobj_signal amdgpu_cs_syncobj_wait amdgpu_cs_wait_fences amdgpu_cs_wait_semaphore diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index c95cb03c..2eb03bf1 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1381,6 +1381,34 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, uint32_t syncobj); +/** + * Reset kernel sync objects to unsignalled state. + * + * \param dev - \c [in] device handle + * \param syncobjs - \c [in] array of sync object handles + * \param syncobj_count - \c [in] number of handles in syncobjs + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, + const uint32_t *syncobjs, uint32_t syncobj_count); + +/** + * Signal kernel sync objects. + * + * \param dev - \c [in] device handle + * \param syncobjs - \c [in] array of sync object handles + * \param syncobj_count - \c [in] number of handles in syncobjs + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, + const uint32_t *syncobjs, uint32_t syncobj_count); + /** * Wait for one or all sync objects to signal. * diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 9e157a84..987daa40 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -634,6 +634,24 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, return drmSyncobjDestroy(dev->fd, handle); } +int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, + const uint32_t *syncobjs, uint32_t syncobj_count) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjReset(dev->fd, syncobjs, syncobj_count); +} + +int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, + const uint32_t *syncobjs, uint32_t syncobj_count) +{ + if (NULL == dev) + return -EINVAL; + + return drmSyncobjSignal(dev->fd, syncobjs, syncobj_count); +} + int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, uint32_t *handles, unsigned num_handles, int64_t timeout_nsec, unsigned flags, -- cgit v1.2.3-54-g00ecf From c4171535389d72e9135c9615cecd07b346fd6d7e Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 16 Mar 2017 18:11:05 -0700 Subject: drm: Add drm mode lease ioctl wrappers [v3] drmModeCreateLease drmModeListLessees drmModeGetLease drmModeRevokeLease Changes for v2: Remove lessee id from GetLease Remove lessor_id from ListLeases Add revoke Renumber to track kernel rebase on drm-next Signed-off-by: Keith Packard Signed-off-by: Dave Airlie --- xf86drmMode.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ xf86drmMode.h | 22 +++++++++++++++ 2 files changed, 111 insertions(+) diff --git a/xf86drmMode.c b/xf86drmMode.c index 2b3887b3..eddad8c4 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -1485,3 +1485,92 @@ drmModeDestroyPropertyBlob(int fd, uint32_t id) destroy.blob_id = id; return DRM_IOCTL(fd, DRM_IOCTL_MODE_DESTROYPROPBLOB, &destroy); } + +int +drmModeCreateLease(int fd, const uint32_t *objects, int num_objects, int flags, uint32_t *lessee_id) +{ + struct drm_mode_create_lease create; + int ret; + + memclear(create); + create.object_ids = (uintptr_t) objects; + create.object_count = num_objects; + create.flags = flags; + + ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_CREATE_LEASE, &create); + if (ret == 0) { + *lessee_id = create.lessee_id; + return create.fd; + } + return -errno; +} + +drmModeLesseeListPtr +drmModeListLessees(int fd) +{ + struct drm_mode_list_lessees list; + uint32_t count; + drmModeLesseeListPtr ret; + + memclear(list); + + if (DRM_IOCTL(fd, DRM_IOCTL_MODE_LIST_LESSEES, &list)) + return NULL; + + count = list.count_lessees; + ret = drmMalloc(sizeof (drmModeLesseeListRes) + count * sizeof (ret->lessees[0])); + if (!ret) + return NULL; + + list.lessees_ptr = VOID2U64(&ret->lessees[0]); + if (DRM_IOCTL(fd, DRM_IOCTL_MODE_LIST_LESSEES, &list)) { + drmFree(ret); + return NULL; + } + + ret->count = count; + return ret; +} + +drmModeObjectListPtr +drmModeGetLease(int fd) +{ + struct drm_mode_get_lease get; + uint32_t count; + drmModeObjectListPtr ret; + + memclear(get); + + if (DRM_IOCTL(fd, DRM_IOCTL_MODE_GET_LEASE, &get)) + return NULL; + + count = get.count_objects; + ret = drmMalloc(sizeof (drmModeObjectListRes) + count * sizeof (ret->objects[0])); + if (!ret) + return NULL; + + get.objects_ptr = VOID2U64(&ret->objects[0]); + if (DRM_IOCTL(fd, DRM_IOCTL_MODE_GET_LEASE, &get)) { + drmFree(ret); + return NULL; + } + + ret->count = count; + return ret; +} + +int +drmModeRevokeLease(int fd, uint32_t lessee_id) +{ + struct drm_mode_revoke_lease revoke; + int ret; + + memclear(revoke); + + revoke.lessee_id = lessee_id; + + ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_REVOKE_LEASE, &revoke); + if (ret == 0) + return 0; + return -errno; +} diff --git a/xf86drmMode.h b/xf86drmMode.h index 6dbe3353..3cd27aee 100644 --- a/xf86drmMode.h +++ b/xf86drmMode.h @@ -521,6 +521,28 @@ extern int drmModeCreatePropertyBlob(int fd, const void *data, size_t size, uint32_t *id); extern int drmModeDestroyPropertyBlob(int fd, uint32_t id); +/* + * DRM mode lease APIs. These create and manage new drm_masters with + * access to a subset of the available DRM resources + */ + +extern int drmModeCreateLease(int fd, const uint32_t *objects, int num_objects, int flags, uint32_t *lessee_id); + +typedef struct drmModeLesseeList { + uint32_t count; + uint32_t lessees[0]; +} drmModeLesseeListRes, *drmModeLesseeListPtr; + +extern drmModeLesseeListPtr drmModeListLessees(int fd); + +typedef struct drmModeObjectList { + uint32_t count; + uint32_t objects[0]; +} drmModeObjectListRes, *drmModeObjectListPtr; + +extern drmModeObjectListPtr drmModeGetLease(int fd); + +extern int drmModeRevokeLease(int fd, uint32_t lessee_id); #if defined(__cplusplus) } -- cgit v1.2.3-54-g00ecf From d4331dda5b5969922c4f1e3ad6d53f23becb91ab Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sat, 1 Jul 2017 00:43:15 -0700 Subject: drm: Add CrtcGetSequence and CrtcQueueSequence IOCTLs [v2] These provide a crtc-id based interface to get the current sequence (frame) number and to queue an event to be delivered at a specific sequence. v2: Remove FIRST_PIXEL_OUT flag. This has been removed from the proposed kernel API Signed-off-by: Keith Packard Signed-off-by: Dave Airlie --- xf86drm.c | 37 +++++++++++++++++++++++++++++++++++++ xf86drm.h | 12 +++++++++++- xf86drmMode.c | 9 +++++++++ 3 files changed, 57 insertions(+), 1 deletion(-) diff --git a/xf86drm.c b/xf86drm.c index deb76e4b..74b4e230 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -1695,6 +1695,43 @@ int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, return 0; } +int drmCrtcGetSequence(int fd, uint32_t crtcId, uint64_t *sequence, uint64_t *ns) +{ + struct drm_crtc_get_sequence get_seq; + int ret; + + memclear(get_seq); + get_seq.crtc_id = crtcId; + ret = drmIoctl(fd, DRM_IOCTL_CRTC_GET_SEQUENCE, &get_seq); + if (ret) + return ret; + + if (sequence) + *sequence = get_seq.sequence; + if (ns) + *ns = get_seq.sequence_ns; + return 0; +} + +int drmCrtcQueueSequence(int fd, uint32_t crtcId, uint32_t flags, uint64_t sequence, + uint64_t *sequence_queued, uint64_t user_data) +{ + struct drm_crtc_queue_sequence queue_seq; + int ret; + + memclear(queue_seq); + queue_seq.crtc_id = crtcId; + queue_seq.flags = flags; + queue_seq.sequence = sequence; + queue_seq.user_data = user_data; + + ret = drmIoctl(fd, DRM_IOCTL_CRTC_QUEUE_SEQUENCE, &queue_seq); + if (ret == 0 && sequence_queued) + *sequence_queued = queue_seq.sequence; + + return ret; +} + /** * Acquire the AGP device. * diff --git a/xf86drm.h b/xf86drm.h index 0dbf4941..7773d71a 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -636,6 +636,12 @@ extern int drmCtlUninstHandler(int fd); extern int drmSetClientCap(int fd, uint64_t capability, uint64_t value); +extern int drmCrtcGetSequence(int fd, uint32_t crtcId, + uint64_t *sequence, uint64_t *ns); +extern int drmCrtcQueueSequence(int fd, uint32_t crtcId, + uint32_t flags, uint64_t sequence, + uint64_t *sequence_queued, + uint64_t user_data); /* General user-level programmer's API: authenticated client and/or X */ extern int drmMap(int fd, drm_handle_t handle, @@ -728,7 +734,7 @@ extern void drmMsg(const char *format, ...) DRM_PRINTFLIKE(1, 2); extern int drmSetMaster(int fd); extern int drmDropMaster(int fd); -#define DRM_EVENT_CONTEXT_VERSION 3 +#define DRM_EVENT_CONTEXT_VERSION 4 typedef struct _drmEventContext { @@ -755,6 +761,10 @@ typedef struct _drmEventContext { unsigned int crtc_id, void *user_data); + void (*sequence_handler)(int fd, + uint64_t sequence, + uint64_t ns, + uint64_t user_data); } drmEventContext, *drmEventContextPtr; extern int drmHandleEvent(int fd, drmEventContextPtr evctx); diff --git a/xf86drmMode.c b/xf86drmMode.c index eddad8c4..15957ffc 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -889,6 +889,7 @@ int drmHandleEvent(int fd, drmEventContextPtr evctx) int len, i; struct drm_event *e; struct drm_event_vblank *vblank; + struct drm_event_crtc_sequence *seq; void *user_data; /* The DRM read semantics guarantees that we always get only @@ -933,6 +934,14 @@ int drmHandleEvent(int fd, drmEventContextPtr evctx) vblank->tv_usec, user_data); break; + case DRM_EVENT_CRTC_SEQUENCE: + seq = (struct drm_event_crtc_sequence *) e; + if (evctx->version >= 4 && evctx->sequence_handler) + evctx->sequence_handler(fd, + seq->sequence, + seq->time_ns, + seq->user_data); + break; default: break; } -- cgit v1.2.3-54-g00ecf From 831036a6f62005da9fb4a75fe043bd96ce672d27 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 18 Dec 2017 11:24:34 +1000 Subject: configure.ac: bump version for release --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index b2d961b1..35378b33 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.88], + [2.4.89], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From ad3152fa698b128c9bd266522b0b48594b131055 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Thu, 4 Jan 2018 15:31:51 +0900 Subject: amdgpu: fix not to add amdgpu.ids when building without amdgpu The amdgpu.ids is only required when building with amdgpu support. Fix not to add it without amdgpu. Signed-off-by: Seung-Woo Kim Reviewed-by: Michel Dänzer --- data/Makefile.am | 2 ++ 1 file changed, 2 insertions(+) diff --git a/data/Makefile.am b/data/Makefile.am index eba915dd..897a7f35 100644 --- a/data/Makefile.am +++ b/data/Makefile.am @@ -20,4 +20,6 @@ # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. libdrmdatadir = @libdrmdatadir@ +if HAVE_AMDGPU dist_libdrmdata_DATA = amdgpu.ids +endif -- cgit v1.2.3-54-g00ecf From a8e436de5d444982e791470cfec505e6280c416a Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 2 Nov 2017 18:54:59 +0100 Subject: amdgpu: fix 32bit VA manager max address The range is exclusive not inclusive. Signed-off-by: Christian König Reviewed-by: Marek Olšák --- amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index eb4b2745..d7077184 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -265,7 +265,7 @@ int amdgpu_device_initialize(int fd, } start = dev->dev_info.virtual_address_offset; - max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); + max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); -- cgit v1.2.3-54-g00ecf From 0a3c01f4ad6a09450e59008085c7bf8151aeb5c4 Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 7 Nov 2017 15:31:45 +0100 Subject: headers: sync up amdgpu_drm.h with drm-next Sync up amdgpu changes from drm-next. Signed-off-by: Christian König Reviewed-by: Marek Olšák --- include/drm/amdgpu_drm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 919248fb..a023b476 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -869,6 +869,10 @@ struct drm_amdgpu_info_device { __u32 _pad1; /* always on cu bitmap */ __u32 cu_ao_bitmap[4][4]; + /** Starting high virtual address for UMDs. */ + __u64 high_va_offset; + /** The maximum high virtual address */ + __u64 high_va_max; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3-54-g00ecf From 07ea20d5beb24315b721adf83bbfa72ce016e146 Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 7 Nov 2017 15:31:45 +0100 Subject: amdgpu: use the high VA range if possible v2 Retire the low range on Vega10 this frees up everything below 0xffff800000000000 for HMM. v2: keep the 32bit range working. Signed-off-by: Christian König Reviewed-by: Marek Olšák --- amdgpu/amdgpu_device.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index d7077184..a0d01727 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -264,13 +264,23 @@ int amdgpu_device_initialize(int fd, goto cleanup; } - start = dev->dev_info.virtual_address_offset; - max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL); + if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) { + start = dev->dev_info.high_va_offset; + max = dev->dev_info.high_va_max; + } else { + start = dev->dev_info.virtual_address_offset; + max = dev->dev_info.virtual_address_max; + } + + max = MIN2(max, (start & ~0xffffffff) + 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); - start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL); - max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); + start = max; + if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) + max = dev->dev_info.high_va_max; + else + max = dev->dev_info.virtual_address_max; amdgpu_vamgr_init(&dev->vamgr, start, max, dev->dev_info.virtual_address_alignment); -- cgit v1.2.3-54-g00ecf From de807d1a740effe60da62d07dcfeae7c01012d15 Mon Sep 17 00:00:00 2001 From: Christian König Date: Sun, 7 Jan 2018 10:10:15 +0100 Subject: test/amdgpu: fix compiler warnings SWAP_32() should mask first and then shift. Signed-off-by: Christian König Reviewed-by: Marek Olšák --- tests/amdgpu/basic_tests.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 474a679c..9c918951 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -253,10 +253,10 @@ CU_TestInfo basic_tests[] = { -#define SWAP_32(num) ((num>>24)&0xff) | \ - ((num<<8)&0xff0000) | \ - ((num>>8)&0xff00) | \ - ((num<<24)&0xff000000) +#define SWAP_32(num) (((num & 0xff000000) >> 24) | \ + ((num & 0x0000ff00) << 8) | \ + ((num & 0x00ff0000) >> 8) | \ + ((num & 0x000000ff) << 24)) /* Shader code -- cgit v1.2.3-54-g00ecf From d3cb58831517d4d42869a7c1f518c861baafdc8e Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Wed, 10 Jan 2018 15:51:02 -0800 Subject: intel: Add more Coffeelake PCI IDs Cc: Rodrigo Vivi Cc: Anusha Srivatsa Signed-off-by: Anuj Phogat Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index d81b1646..3818e71e 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -223,15 +223,23 @@ #define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 #define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 +#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99 #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 +#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 -#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 -#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 -#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 -#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 +#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 +#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 +#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 +#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 +#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 +#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 #define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A @@ -477,17 +485,25 @@ #define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3) + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4) #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) -#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4) + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5) #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ IS_CFL_H(devid) || \ -- cgit v1.2.3-54-g00ecf From 168dbe9a0ee29dbe5ddd16706147f2e6d8ad5576 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 8 Jan 2018 11:20:28 +0800 Subject: tests/amdgpu: execute write linear on all the available rings Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher --- tests/amdgpu/basic_tests.c | 111 +++++++++++++++++++++++---------------------- 1 file changed, 58 insertions(+), 53 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 9c918951..837ee9aa 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -868,9 +868,10 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) struct amdgpu_cs_request *ibs_request; uint64_t bo_mc; volatile uint32_t *bo_cpu; - int i, j, r, loop; + int i, j, r, loop, ring_id; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; + struct drm_amdgpu_info_hw_ip hw_ip_info; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -881,6 +882,9 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) ibs_request = calloc(1, sizeof(*ibs_request)); CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -888,65 +892,66 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) resources = calloc(1, sizeof(amdgpu_bo_handle)); CU_ASSERT_NOT_EQUAL(resources, NULL); - loop = 0; - while(loop < 2) { - /* allocate UC bo for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length * sizeof(uint32_t), - 4096, AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop], &bo, (void**)&bo_cpu, - &bo_mc, &va_handle); - CU_ASSERT_EQUAL(r, 0); + for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { + loop = 0; + while(loop < 2) { + /* allocate UC bo for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length * sizeof(uint32_t), + 4096, AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop], &bo, (void**)&bo_cpu, + &bo_mc, &va_handle); + CU_ASSERT_EQUAL(r, 0); - /* clear bo */ - memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); + /* clear bo */ + memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); + resources[0] = bo; - resources[0] = bo; + /* fulfill PM4: test DMA write-linear */ + i = j = 0; + if (ip_type == AMDGPU_HW_IP_DMA) { + if (family_id == AMDGPU_FAMILY_SI) + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, + sdma_write_length); + else + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else if (family_id != AMDGPU_FAMILY_SI) + pm4[i++] = sdma_write_length; + while(j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { + pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); + pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + while(j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; + } - /* fulfill PM4: test DMA write-linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, - sdma_write_length); - else - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else if (family_id != AMDGPU_FAMILY_SI) - pm4[i++] = sdma_write_length; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); - pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; - } + amdgpu_test_exec_cs_helper(context_handle, + ip_type, ring_id, + i, pm4, + 1, resources, + ib_info, ibs_request); - amdgpu_test_exec_cs_helper(context_handle, - ip_type, 0, - i, pm4, - 1, resources, - ib_info, ibs_request); + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + } - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, + sdma_write_length * sizeof(uint32_t)); + CU_ASSERT_EQUAL(r, 0); + loop++; } - - r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, - sdma_write_length * sizeof(uint32_t)); - CU_ASSERT_EQUAL(r, 0); - loop++; } /* clean resources */ free(resources); -- cgit v1.2.3-54-g00ecf From cbbb8a332d972a4ab18622f1c53de21324735fef Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 8 Jan 2018 11:20:29 +0800 Subject: tests/amdgpu: execute const fill on all the available rings Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher --- tests/amdgpu/basic_tests.c | 147 ++++++++++++++++++++++++--------------------- 1 file changed, 77 insertions(+), 70 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 837ee9aa..0a198e48 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -981,9 +981,10 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) struct amdgpu_cs_request *ibs_request; uint64_t bo_mc; volatile uint32_t *bo_cpu; - int i, j, r, loop; + int i, j, r, loop, ring_id; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; + struct drm_amdgpu_info_hw_ip hw_ip_info; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -994,6 +995,9 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) ibs_request = calloc(1, sizeof(*ibs_request)); CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -1001,83 +1005,86 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) resources = calloc(1, sizeof(amdgpu_bo_handle)); CU_ASSERT_NOT_EQUAL(resources, NULL); - loop = 0; - while(loop < 2) { - /* allocate UC bo for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop], &bo, (void**)&bo_cpu, - &bo_mc, &va_handle); - CU_ASSERT_EQUAL(r, 0); + for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { + loop = 0; + while(loop < 2) { + /* allocate UC bo for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop], &bo, (void**)&bo_cpu, + &bo_mc, &va_handle); + CU_ASSERT_EQUAL(r, 0); - /* clear bo */ - memset((void*)bo_cpu, 0, sdma_write_length); + /* clear bo */ + memset((void*)bo_cpu, 0, sdma_write_length); - resources[0] = bo; + resources[0] = bo; - /* fulfill PM4: test DMA const fill */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, 0, 0, 0, - sdma_write_length / 4); - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, - SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0xdeadbeaf; - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else + /* fulfill PM4: test DMA const fill */ + i = j = 0; + if (ip_type == AMDGPU_HW_IP_DMA) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, + 0, 0, 0, + sdma_write_length / 4); + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; + } else { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, + SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0xdeadbeaf; + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; + } + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); + pm4[i++] = 0xdeadbeaf; + pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | + PACKET3_DMA_DATA_SI_DST_SEL(0) | + PACKET3_DMA_DATA_SI_SRC_SEL(2) | + PACKET3_DMA_DATA_SI_CP_SYNC; + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; pm4[i++] = sdma_write_length; + } else { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(2) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = 0; + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; + } } - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); - pm4[i++] = 0xdeadbeaf; - pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | - PACKET3_DMA_DATA_SI_DST_SEL(0) | - PACKET3_DMA_DATA_SI_SRC_SEL(2) | - PACKET3_DMA_DATA_SI_CP_SYNC; - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; - } else { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(2) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = 0; - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; - } - } - amdgpu_test_exec_cs_helper(context_handle, - ip_type, 0, - i, pm4, - 1, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + ip_type, ring_id, + i, pm4, + 1, resources, + ib_info, ibs_request); - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < (sdma_write_length / 4)) { - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); - } + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < (sdma_write_length / 4)) { + CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + } - r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - loop++; + r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + loop++; + } } /* clean resources */ free(resources); -- cgit v1.2.3-54-g00ecf From f115de819bc10bb36565f344a66fa619219911b9 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 8 Jan 2018 11:20:30 +0800 Subject: tests/amdgpu: execute copy linear on all the available rings Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher --- tests/amdgpu/basic_tests.c | 200 +++++++++++++++++++++++---------------------- 1 file changed, 104 insertions(+), 96 deletions(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 0a198e48..0f75e896 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -1114,9 +1114,10 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) struct amdgpu_cs_request *ibs_request; uint64_t bo1_mc, bo2_mc; volatile unsigned char *bo1_cpu, *bo2_cpu; - int i, j, r, loop1, loop2; + int i, j, r, loop1, loop2, ring_id; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle bo1_va_handle, bo2_va_handle; + struct drm_amdgpu_info_hw_ip hw_ip_info; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -1127,6 +1128,9 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) ibs_request = calloc(1, sizeof(*ibs_request)); CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -1134,107 +1138,111 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) resources = calloc(2, sizeof(amdgpu_bo_handle)); CU_ASSERT_NOT_EQUAL(resources, NULL); - loop1 = loop2 = 0; - /* run 9 circle to test all mapping combination */ - while(loop1 < 2) { - while(loop2 < 2) { - /* allocate UC bo1for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop1], &bo1, - (void**)&bo1_cpu, &bo1_mc, - &bo1_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* set bo1 */ - memset((void*)bo1_cpu, 0xaa, sdma_write_length); - - /* allocate UC bo2 for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop2], &bo2, - (void**)&bo2_cpu, &bo2_mc, - &bo2_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* clear bo2 */ - memset((void*)bo2_cpu, 0, sdma_write_length); - - resources[0] = bo1; - resources[1] = bo2; - - /* fulfill PM4: test DMA copy linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, - sdma_write_length); - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else + for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { + loop1 = loop2 = 0; + /* run 9 circle to test all mapping combination */ + while(loop1 < 2) { + while(loop2 < 2) { + /* allocate UC bo1for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop1], &bo1, + (void**)&bo1_cpu, &bo1_mc, + &bo1_va_handle); + CU_ASSERT_EQUAL(r, 0); + + /* set bo1 */ + memset((void*)bo1_cpu, 0xaa, sdma_write_length); + + /* allocate UC bo2 for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop2], &bo2, + (void**)&bo2_cpu, &bo2_mc, + &bo2_va_handle); + CU_ASSERT_EQUAL(r, 0); + + /* clear bo2 */ + memset((void*)bo2_cpu, 0, sdma_write_length); + + resources[0] = bo1; + resources[1] = bo2; + + /* fulfill PM4: test DMA copy linear */ + i = j = 0; + if (ip_type == AMDGPU_HW_IP_DMA) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, + 0, 0, 0, + sdma_write_length); + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + } else { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, + SDMA_COPY_SUB_OPCODE_LINEAR, + 0); + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; + pm4[i++] = 0; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + } + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); + pm4[i++] = 0xfffffffc & bo1_mc; + pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | + PACKET3_DMA_DATA_SI_DST_SEL(0) | + PACKET3_DMA_DATA_SI_SRC_SEL(0) | + PACKET3_DMA_DATA_SI_CP_SYNC | + (0xffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xfffffffc & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; pm4[i++] = sdma_write_length; - pm4[i++] = 0; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - } - - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); - pm4[i++] = 0xfffffffc & bo1_mc; - pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | - PACKET3_DMA_DATA_SI_DST_SEL(0) | - PACKET3_DMA_DATA_SI_SRC_SEL(0) | - PACKET3_DMA_DATA_SI_CP_SYNC | - (0xffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xfffffffc & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = sdma_write_length; - } else { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(0) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xfffffffc & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xfffffffc & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = sdma_write_length; + } else { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(0) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xfffffffc & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xfffffffc & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = sdma_write_length; + } } - } - amdgpu_test_exec_cs_helper(context_handle, - ip_type, 0, - i, pm4, - 2, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + ip_type, ring_id, + i, pm4, + 2, resources, + ib_info, ibs_request); - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); + } + r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + loop2++; } - r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - loop2++; + loop1++; } - loop1++; } /* clean resources */ free(resources); -- cgit v1.2.3-54-g00ecf From 5f7deb50787b82038cc35fb1e31b761e33e5a341 Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Wed, 13 Sep 2017 11:46:13 -0700 Subject: Add meson build system This patch adds a complete meson build system, including tests and install. It has the necessary hooks to allow it be used as a subproject for other meson based builds such as mesa. Signed-off-by: Dylan Baker Reviewed-and-tested-by: Igor Gnatenko Reviewed-by: Eric Engestrom --- .editorconfig | 4 + amdgpu/.editorconfig | 4 + amdgpu/meson.build | 65 ++++++++ data/meson.build | 27 ++++ etnaviv/meson.build | 59 +++++++ exynos/meson.build | 53 +++++++ freedreno/meson.build | 76 +++++++++ intel/meson.build | 105 +++++++++++++ libkms/meson.build | 74 +++++++++ man/meson.build | 67 ++++++++ meson.build | 367 ++++++++++++++++++++++++++++++++++++++++++++ meson_options.txt | 143 +++++++++++++++++ nouveau/meson.build | 58 +++++++ omap/meson.build | 53 +++++++ radeon/meson.build | 63 ++++++++ tegra/meson.build | 52 +++++++ tests/amdgpu/meson.build | 34 ++++ tests/etnaviv/meson.build | 45 ++++++ tests/exynos/meson.build | 54 +++++++ tests/kms/meson.build | 49 ++++++ tests/kmstest/meson.build | 30 ++++ tests/meson.build | 86 +++++++++++ tests/modeprint/meson.build | 29 ++++ tests/modetest/meson.build | 29 ++++ tests/nouveau/meson.build | 30 ++++ tests/proptest/meson.build | 28 ++++ tests/radeon/meson.build | 27 ++++ tests/tegra/meson.build | 27 ++++ tests/util/meson.build | 28 ++++ tests/vbltest/meson.build | 28 ++++ vc4/meson.build | 28 ++++ 31 files changed, 1822 insertions(+) create mode 100644 amdgpu/meson.build create mode 100644 data/meson.build create mode 100644 etnaviv/meson.build create mode 100644 exynos/meson.build create mode 100644 freedreno/meson.build create mode 100644 intel/meson.build create mode 100644 libkms/meson.build create mode 100644 man/meson.build create mode 100644 meson.build create mode 100644 meson_options.txt create mode 100644 nouveau/meson.build create mode 100644 omap/meson.build create mode 100644 radeon/meson.build create mode 100644 tegra/meson.build create mode 100644 tests/amdgpu/meson.build create mode 100644 tests/etnaviv/meson.build create mode 100644 tests/exynos/meson.build create mode 100644 tests/kms/meson.build create mode 100644 tests/kmstest/meson.build create mode 100644 tests/meson.build create mode 100644 tests/modeprint/meson.build create mode 100644 tests/modetest/meson.build create mode 100644 tests/nouveau/meson.build create mode 100644 tests/proptest/meson.build create mode 100644 tests/radeon/meson.build create mode 100644 tests/tegra/meson.build create mode 100644 tests/util/meson.build create mode 100644 tests/vbltest/meson.build create mode 100644 vc4/meson.build diff --git a/.editorconfig b/.editorconfig index 893b7be0..29b4f393 100644 --- a/.editorconfig +++ b/.editorconfig @@ -17,3 +17,7 @@ indent_style = tab [*.m4] indent_style = space indent_size = 2 + +[{meson.build,meson_options.txt}] +indent_style = space +indent_size = 2 diff --git a/amdgpu/.editorconfig b/amdgpu/.editorconfig index 2528d675..426273fd 100644 --- a/amdgpu/.editorconfig +++ b/amdgpu/.editorconfig @@ -7,3 +7,7 @@ indent_style = tab indent_size = 8 tab_width = 8 insert_final_newline = true + +[meson.build] +indent_style = space +indent_size = 2 diff --git a/amdgpu/meson.build b/amdgpu/meson.build new file mode 100644 index 00000000..55ab9d1d --- /dev/null +++ b/amdgpu/meson.build @@ -0,0 +1,65 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + + +datadir_amdgpu = join_paths(get_option('datadir'), 'libdrm', 'amdgpu.ids') + +libdrm_amdgpu = shared_library( + 'drm_amdgpu', + [ + files( + 'amdgpu_asic_id.c', 'amdgpu_bo.c', 'amdgpu_cs.c', 'amdgpu_device.c', + 'amdgpu_gpu_info.c', 'amdgpu_vamgr.c', 'amdgpu_vm.c', 'util_hash.c', + 'util_hash_table.c', + ), + config_file, + ], + c_args : [ + warn_c_args, + '-DAMDGPU_ASIC_ID_TABLE="@0@"'.format(datadir_amdgpu), + ], + include_directories : [inc_root, inc_drm], + link_with : libdrm, + dependencies : dep_pthread_stubs, + version : '1.0.0', + install : true, +) + +install_headers('amdgpu.h', subdir : 'libdrm') + +pkg.generate( + name : 'libdrm_amdgpu', + libraries : libdrm_amdgpu, + subdirs : ['.', 'libdrm'], + version : meson.project_version(), + requires_private : 'libdrm', + description : 'Userspace interface to kernel DRM services for amdgpu', +) + +ext_libdrm_amdgpu = declare_dependency( + link_with : [libdrm, libdrm_amdgpu], + include_directories : [inc_drm, include_directories('.')], +) + +test( + 'amdgpu-symbol-check', + prog_bash, + args : [files('amdgpu-symbol-check'), libdrm_amdgpu] +) diff --git a/data/meson.build b/data/meson.build new file mode 100644 index 00000000..9c26b66e --- /dev/null +++ b/data/meson.build @@ -0,0 +1,27 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +if with_amdgpu + install_data( + 'amdgpu.ids', + install_mode : 'rw-r--r--', + install_dir : datadir_amdgpu, + ) +endif diff --git a/etnaviv/meson.build b/etnaviv/meson.build new file mode 100644 index 00000000..1767733b --- /dev/null +++ b/etnaviv/meson.build @@ -0,0 +1,59 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + + +libdrm_etnaviv = shared_library( + 'drm_etnaviv', + [ + files( + 'etnaviv_device.c', 'etnaviv_gpu.c', 'etnaviv_bo.c', 'etnaviv_bo_cache.c', + 'etnaviv_perfmon.c', 'etnaviv_pipe.c', 'etnaviv_cmd_stream.c', + ), + config_file + ], + include_directories : [inc_root, inc_drm], + link_with : libdrm, + c_args : warn_c_args, + dependencies : [dep_pthread_stubs, dep_rt], + version : '1.0.0', + install : true, +) + +install_headers('etnaviv_drmif.h', subdir : 'libdrm') + +pkg.generate( + name : 'libdrm_etnaviv', + libraries : libdrm_etnaviv, + subdirs : ['.', 'libdrm'], + version : meson.project_version(), + requires_private : 'libdrm', + description : 'Userspace interface to Tegra kernel DRM services', +) + +ext_libdrm_etnaviv = declare_dependency( + link_with : [libdrm, libdrm_etnaviv], + include_directories : [inc_drm, include_directories('.')], +) + +test( + 'etnaviv-symbol-check', + prog_bash, + args : [files('etnaviv-symbol-check'), libdrm_etnaviv] +) diff --git a/exynos/meson.build b/exynos/meson.build new file mode 100644 index 00000000..c96ad4e0 --- /dev/null +++ b/exynos/meson.build @@ -0,0 +1,53 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +libdrm_exynos = shared_library( + 'drm_exynos', + [files('exynos_drm.c', 'exynos_fimg2d.c'), config_file], + c_args : warn_c_args, + include_directories : [inc_root, inc_drm], + link_with : libdrm, + dependencies : [dep_pthread_stubs], + version : '1.0.0', + install : true, +) + +install_headers('exynos_drmif.h', subdir : 'libdrm') +install_headers('exynos_drm.h', 'exynos_fimg2d.h', subdir : 'exynos') + +ext_libdrm_exynos = declare_dependency( + link_with : [libdrm, libdrm_exynos], + include_directories : [inc_drm, include_directories('.')], +) + +pkg.generate( + name : 'libdrm_exynos', + libraries : libdrm_exynos, + subdirs : ['.', 'libdrm', 'exynos'], + version : '0.7', + requires_private : 'libdrm', + description : 'Userspace interface to exynos kernel DRM services', +) + +test( + 'exynos-symbol-check', + prog_bash, + args : [files('exynos-symbol-check'), libdrm_exynos] +) diff --git a/freedreno/meson.build b/freedreno/meson.build new file mode 100644 index 00000000..b4035e19 --- /dev/null +++ b/freedreno/meson.build @@ -0,0 +1,76 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +files_freedreno = files( + 'freedreno_device.c', + 'freedreno_pipe.c', + 'freedreno_ringbuffer.c', + 'freedreno_bo.c', + 'freedreno_bo_cache.c', + 'msm/msm_bo.c', + 'msm/msm_device.c', + 'msm/msm_pipe.c', + 'msm/msm_ringbuffer.c', +) + +if with_freedreno_kgsl + files_freedreno += files( + 'kgsl/kgsl_bo.c', + 'kgsl/kgsl_device.c', + 'kgsl/kgsl_pipe.c', + 'kgsl/kgsl_ringbuffer.c', + ) +endif + +libdrm_freedreno = shared_library( + 'drm_freedreno', + [files_freedreno, config_file], + c_args : warn_c_args, + include_directories : [inc_root, inc_drm], + dependencies : [dep_valgrind, dep_pthread_stubs, dep_rt], + link_with : libdrm, + version : '1.0.0', + install : true, +) + +ext_libdrm_freedreno = declare_dependency( + link_with : [libdrm, libdrm_freedreno], + include_directories : [inc_drm, include_directories('.')], +) + +install_headers( + 'freedreno_drmif.h', 'freedreno_ringbuffer.h', + subdir : 'freedreno' +) + +pkg.generate( + name : 'libdrm_freedreno', + libraries : libdrm_freedreno, + subdirs : ['.', 'libdrm', 'freedreno'], + version : '0.7', + requires_private : 'libdrm', + description : 'Userspace interface to freedreno kernel DRM services', +) + +test( + 'freedreno-symbol-check', + prog_bash, + args : [files('freedreno-symbol-check'), libdrm_freedreno] +) diff --git a/intel/meson.build b/intel/meson.build new file mode 100644 index 00000000..ad877274 --- /dev/null +++ b/intel/meson.build @@ -0,0 +1,105 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +libdrm_intel = shared_library( + 'drm_intel', + [ + files( + 'intel_bufmgr.c', 'intel_bufmgr_fake.c', 'intel_bufmgr_gem.c', + 'intel_decode.c', 'mm.c', + ), + config_file, + ], + include_directories : [inc_root, inc_drm], + link_with : libdrm, + dependencies : [dep_pciaccess, dep_pthread_stubs, dep_rt, dep_valgrind], + c_args : warn_c_args, + version : '1.0.0', + install : true, +) + +ext_libdrm_intel = declare_dependency( + link_with : [libdrm, libdrm_intel], + include_directories : [inc_drm, include_directories('.')], +) + +install_headers( + 'intel_bufmgr.h', 'intel_aub.h', 'intel_debug.h', + subdir : 'libdrm', +) + +pkg.generate( + name : 'libdrm_intel', + libraries : libdrm_intel, + subdirs : ['.', 'libdrm'], + version : meson.project_version(), + requires : 'libdrm', + description : 'Userspace interface to intel kernel DRM services', +) + +test_decode = executable( + 'test_decode', + files('test_decode.c'), + include_directories : [inc_root, inc_drm], + link_with : [libdrm, libdrm_intel], + c_args : warn_c_args, +) + +test( + 'gen4-3d.batch', + prog_bash, + args : files('tests/gen4-3d.batch.sh'), + workdir : meson.current_build_dir(), +) +test( + 'gen45-3d.batch', + prog_bash, + args : files('tests/gm45-3d.batch.sh'), + workdir : meson.current_build_dir(), +) +test( + 'gen5-3d.batch', + prog_bash, + args : files('tests/gen5-3d.batch.sh'), + workdir : meson.current_build_dir(), +) +test( + 'gen6-3d.batch', + prog_bash, + args : files('tests/gen6-3d.batch.sh'), + workdir : meson.current_build_dir(), +) +test( + 'gen7-3d.batch', + prog_bash, + args : files('tests/gen7-3d.batch.sh'), + workdir : meson.current_build_dir(), +) +test( + 'gen7-2d-copy.batch', + prog_bash, + args : files('tests/gen7-2d-copy.batch.sh'), + workdir : meson.current_build_dir(), +) +test( + 'intel-symbol-check', + prog_bash, + args : [files('intel-symbol-check'), libdrm_intel] +) diff --git a/libkms/meson.build b/libkms/meson.build new file mode 100644 index 00000000..9eff4313 --- /dev/null +++ b/libkms/meson.build @@ -0,0 +1,74 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +libkms_include = [inc_root, inc_drm] +files_libkms = files( + 'linux.c', + 'dumb.c', + 'api.c', +) +if with_vmwgfx + files_libkms += files('vmwgfx.c') +endif +if with_intel + files_libkms += files('intel.c') +endif +if with_nouveau + files_libkms += files('nouveau.c') +endif +if with_radeon + files_libkms += files('radeon.c') +endif +if with_exynos + files_libkms += files('exynos.c') + libkms_include += include_directories('../exynos') +endif + +libkms = shared_library( + 'kms', + [files_libkms, config_file], + c_args : warn_c_args, + include_directories : libkms_include, + link_with : libdrm, + version : '1.0.0', + install : true, +) + +ext_libkms = declare_dependency( + link_with : [libdrm, libkms], + include_directories : [libkms_include], +) + +install_headers('libkms.h', subdir : 'libkms') + +pkg.generate( + name : 'libkms', + libraries : libkms, + subdirs : ['libkms'], + version : '1.0.0', + requires_private : 'libdrm', + description : 'Library that abstracts away the different mm interfaces for kernel drivers', +) + +test( + 'kms-symbol-check', + prog_bash, + args : [files('kms-symbol-check'), libkms] +) diff --git a/man/meson.build b/man/meson.build new file mode 100644 index 00000000..45eaeda0 --- /dev/null +++ b/man/meson.build @@ -0,0 +1,67 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +xsltproc_args = [ + '--stringparam', 'man.authors.section.enabled', '0', + '--stringparam', 'man.copyright.section.enabled', '0', + '--stringparam', 'funcsynopsis.style', 'ansi', + '--stringparam', 'man.output.quietly', '1', + '--nonet', manpage_style, +] + +xmls = [ + ['drm', '7'], ['drm-kms', '7'], ['drm-memory', '7'], ['drmAvailable', '3'], + ['drmHandleEvent', '3'], ['drmModeGetResources', '3'] +] +foreach x : xmls + m = x[0] + s = x[1] + custom_target( + m, + input : files('@0@.xml'.format(m)), + output : '@0@.@1@'.format(m, s), + command : [prog_xslt, '-o', '@OUTPUT@', xsltproc_args, '@INPUT0@'], + install : true, + install_dir : join_paths(get_option('mandir'), 'man@0@'.format(s)), + build_by_default : true, + ) +endforeach + +foreach x : ['drm-mm', 'drm-gem', 'drm-ttm'] + gen = custom_target( + 'gen-@0@'.format(x), + input : 'drm-memory.xml', + output : '@0@.xml'.format(x), + command : [ + prog_sed, '-e', 's@^\.so \([a-z_]\+\)\.\([0-9]\)$$@\.so man\2\/\1\.\2@', + '@INPUT@', + ], + capture : true, + ) + custom_target( + '@0@.7'.format(x), + input : gen, + output : '@0@.7'.format(x, '7'), + command : [prog_xslt, '-o', '@OUTPUT@', xsltproc_args, '@INPUT@'], + install : true, + install_dir : join_paths(get_option('mandir'), 'man7'), + build_by_default : true, + ) +endforeach diff --git a/meson.build b/meson.build new file mode 100644 index 00000000..05566081 --- /dev/null +++ b/meson.build @@ -0,0 +1,367 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +project( + 'libdrm', + ['c'], + version : '2.4.89', + license : 'MIT', + meson_version : '>= 0.42', + default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], +) + +pkg = import('pkgconfig') + +with_udev = get_option('udev') +with_freedreno_kgsl = get_option('freedreno-kgsl') +with_install_tests = get_option('install-test-programs') +with_cairo_tests = get_option('cairo-tests') +with_valgrind = get_option('valgrind') + +config = configuration_data() + +# TODO: openbsd is guess, the others are correct +if ['freebsd', 'dragonfly', 'netbsd', 'openbsd'].contains(host_machine.system()) + dep_pthread_stubs = dependency('pthread-stubs', version : '>= 0.4') +else + dep_pthread_stubs = [] +endif +dep_threads = dependency('threads') + +cc = meson.get_compiler('c') + +# Check for atomics +intel_atomics = false +lib_atomics = false + +if cc.compiles(''' + int atomic_add(int *i) { return __sync_add_and_fetch (i, 1); } + int atomic_cmpxchg(int *i, int j, int k) { return __sync_val_compare_and_swap (i, j, k); } + ''', + name : 'Intel Atomics') + intel_atomics = true + with_atomics = true +elif cc.has_header('atomic_ops.h') + lib_atomics = true + with_atomics = true +elif cc.has_function('atomic_cas_uint') + with_atomics = true +else + with_atomics = false +endif + +config.set10('HAVE_LIBDRM_ATOMIC_PRIMITIVES', intel_atomics) +config.set10('HAVE_LIB_ATOMIC_OPS', lib_atomics) + +with_intel = false +_intel = get_option('intel') +if _intel != 'false' + if _intel == 'true' and not with_atomics + error('libdrm_intel requires atomics.') + else + with_intel = _intel == 'true' or host_machine.cpu_family().startswith('x86') + endif +endif + +with_radeon = false +_radeon = get_option('radeon') +if _radeon != 'false' + if _radeon == 'true' and not with_atomics + error('libdrm_radeon requires atomics.') + endif + with_radeon = true +endif + +with_amdgpu = false +_amdgpu = get_option('amdgpu') +if _amdgpu != 'false' + if _amdgpu == 'true' and not with_atomics + error('libdrm_amdgpu requires atomics.') + endif + with_amdgpu = true +endif + +with_nouveau = false +_nouveau = get_option('nouveau') +if _nouveau != 'false' + if _nouveau == 'true' and not with_atomics + error('libdrm_nouveau requires atomics.') + endif + with_nouveau = true +endif + +with_vmwgfx = false +_vmwgfx = get_option('vmwgfx') +if _vmwgfx != 'false' + with_vmwgfx = true +endif + +with_omap = false +_omap = get_option('omap') +if _omap == 'true' + if not with_atomics + error('libdrm_omap requires atomics.') + endif + with_omap = true +endif + +with_freedreno = false +_freedreno = get_option('freedreno') +if _freedreno != 'false' + if _freedreno == 'true' and not with_atomics + error('libdrm_freedreno requires atomics.') + else + with_freedreno = _freedreno == 'true' or ['arm', 'aarch64'].contains(host_machine.cpu_family()) + endif +endif + +with_tegra = false +_tegra = get_option('tegra') +if _tegra == 'true' + if not with_atomics + error('libdrm_tegra requires atomics.') + endif + with_tegra = true +endif + +with_etnaviv = false +_etnaviv = get_option('etnaviv') +if _etnaviv == 'true' + if not with_atomics + error('libdrm_etnaviv requires atomics.') + endif + with_etnaviv = true +endif + +with_exynos = get_option('exynos') == 'true' + +with_vc4 = false +_vc4 = get_option('vc4') +if _vc4 != 'false' + with_vc4 = _vc4 == 'true' or ['arm', 'aarch64'].contains(host_machine.cpu_family()) +endif + +# XXX: Aparently only freebsd and dragonfly bsd actually need this (and +# gnu/kfreebsd), not openbsd and netbsd +with_libkms = false +_libkms = get_option('libkms') +if _libkms != 'false' + with_libkms = _libkms == 'true' or ['linux', 'freebsd', 'dragonfly'].contains(host_machine.system()) +endif + +if with_udev + dep_udev = dependency('udev') + config.set10('UDEV', true) +else + dep_udev = [] +endif + +# Among others FreeBSD does not have a separate dl library. +if not cc.has_function('dlsym') + dep_dl = cc.find_library('dl', required : with_nouveau) +else + dep_dl = [] +endif +# clock_gettime might require -rt, or it might not. find out +if not cc.has_function('clock_gettime', prefix : '#define _GNU_SOURCE\n#include ') + # XXX: untested + dep_rt = cc.find_library('rt') +else + dep_rt = [] +endif +dep_m = cc.find_library('m', required : false) +if cc.has_header('sys/sysctl.h') + config.set10('HAVE_SYS_SYSCTL_H', true) +endif +if cc.has_header('sys/select.h') + config.set10('HAVE_SYS_SELECT_H', true) +endif +if cc.has_header_symbol('sys/sysmacros.h', 'major') + config.set10('MAJOR_IN_SYSMACROS', true) +elif cc.has_header_symbol('sys/mkdev.h', 'major') + config.set10('MAJOR_IN_MKDEV', true) +endif +if cc.has_function('open_memstream') + config.set10('HAVE_OPEN_MEMSTREAM', true) +endif + +warn_c_args = [] +foreach a : ['-Wall', '-Wextra', '-Wsign-compare', + '-Werror-implicit-function-declaration', '-Wpointer-arith', + '-Wwrite-strings', '-Wstrict-prototypes', '-Wmissing-prototypes', + '-Wmissing-declarations', '-Wnested-externs', '-Wpacked', + '-Wswitch-enum', '-Wmissing-format-attribute', + '-Wstrict-aliasing=2', '-Winit-self', '-Winline', '-Wshadow', + '-Wdeclaration-after-statement', '-Wold-style-definition'] + if cc.has_argument(a) + warn_c_args += a + endif +endforeach +# GCC will never error for -Wno-*, so check for -W* then add -Wno-* to the list +# of options +foreach a : ['unused-parameter', 'attributes', 'long-long', + 'missing-field-initializers'] + if cc.has_argument('-W@0@'.format(a)) + warn_c_args += '-Wno-@0@'.format(a) + endif +endforeach + + +dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : with_intel) +dep_cunit = dependency('cunit', version : '>= 2.1', required : false) +dep_cairo = dependency('cairo', required : with_cairo_tests == 'true') +dep_valgrind = dependency('valgrind', required : with_valgrind == 'true') + +with_man_pages = get_option('man-pages') +prog_xslt = find_program('xsltproc', required : with_man_pages == 'true') +prog_sed = find_program('sed', required : with_man_pages == 'true') +manpage_style = 'http://docbook.sourceforge.net/release/xsl/current/manpages/docbook.xsl' +if prog_xslt.found() + if run_command(prog_xslt, '--nonet', manpage_style).returncode() != 0 + if with_man_pages == 'true' + error('Manpage style sheet cannot be found') + endif + with_man_pages = 'false' + endif +endif +with_man_pages = with_man_pages != 'false' and prog_xslt.found() and prog_sed.found() + +# Used for tets +prog_bash = find_program('bash') + +if cc.compiles('''int foo_hidden(void) __attribute__((visibility(("hidden"))));''', + name : 'compiler supports __attribute__(("hidden"))') + config.set10('HAVE_VISIBILITY', true) +endif + +foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], + [with_nouveau, 'NOUVEAU'], [with_omap, 'OMAP'], + [with_exynos, 'EXYNOS'], [with_freedreno, 'FREEDRENO'], + [with_tegra, 'TEGRA'], [with_vc4, 'VC4'], + [with_etnaviv, 'ETNAVIV']] + if t[0] + config.set10('HAVE_@0@'.format(t[1]), true) + endif +endforeach +if with_freedreno_kgsl + if not with_freedreno + error('cannot enable freedreno-kgsl without freedreno support') + endif + config.set10('HAVE_FREEDRENO_KGSL', true) +endif +if dep_cairo.found() + config.set10('HAVE_CAIRO', true) +endif +if dep_valgrind.found() + config.set10('HAVE_VALGRIND', true) +endif + +config.set10('_GNU_SOURCE', true) +config_file = configure_file( + configuration : config, + output : 'config.h', +) +add_project_arguments('-DHAVE_CONFIG_H', language : 'c') + +inc_root = include_directories('.') +inc_drm = include_directories('include/drm') + +libdrm = shared_library( + 'drm', + [files( + 'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c', + 'xf86drmMode.c' + ), + config_file, + ], + c_args : warn_c_args, + dependencies : [dep_udev, dep_valgrind, dep_rt, dep_m], + include_directories : inc_drm, + version : '2.4.0', + install : true, +) + +ext_libdrm = declare_dependency( + link_with : libdrm, + include_directories : inc_drm, +) + +install_headers('libsync.h', 'xf86drm.h', 'xf86drmMode.h') +install_headers( + 'include/drm/drm.h', 'include/drm/drm_fourcc.h', 'include/drm/drm_mode.h', + 'include/drm/drm_sarea.h', 'include/drm/i915_drm.h', + 'include/drm/mach64_drm.h', 'include/drm/mga_drm.h', + 'include/drm/nouveau_drm.h', 'include/drm/qxl_drm.h', + 'include/drm/r128_drm.h', 'include/drm/radeon_drm.h', + 'include/drm/amdgpu_drm.h', 'include/drm/savage_drm.h', + 'include/drm/sis_drm.h', 'include/drm/tegra_drm.h', 'include/drm/vc4_drm.h', + 'include/drm/via_drm.h', 'include/drm/virtgpu_drm.h', + subdir : 'libdrm', +) +if with_vmwgfx + install_headers('include/drm/vmwgfx_drm.h', subdir : 'libdrm') +endif + +pkg.generate( + name : 'libdrm', + libraries : libdrm, + subdirs : ['.', 'libdrm'], + version : meson.project_version(), + description : 'Userspace interface to kernel DRM services', +) + +if with_libkms + subdir('libkms') +endif +if with_intel + subdir('intel') +endif +if with_nouveau + subdir('nouveau') +endif +if with_radeon + subdir('radeon') +endif +if with_amdgpu + subdir('amdgpu') +endif +if with_omap + subdir('omap') +endif +if with_exynos + subdir('exynos') +endif +if with_freedreno + subdir('freedreno') +endif +if with_tegra + subdir('tegra') +endif +if with_vc4 + subdir('vc4') +endif +if with_etnaviv + subdir('etnaviv') +endif +if with_man_pages + subdir('man') +endif +subdir('data') +subdir('tests') diff --git a/meson_options.txt b/meson_options.txt new file mode 100644 index 00000000..8af33f1c --- /dev/null +++ b/meson_options.txt @@ -0,0 +1,143 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +option( + 'libkms', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : 'Build libkms mm abstraction library.', +) +option( + 'intel', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : '''Enable support for Intel's KMS API.''', +) +option( + 'radeon', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : '''Enable support for radeons's KMS API.''', +) +option( + 'amdgpu', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : '''Enable support for amdgpu's KMS API.''', +) +option( + 'nouveau', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : '''Enable support for nouveau's KMS API.''', +) +option( + 'vmwgfx', + type : 'combo', + value : 'true', + choices : ['true', 'false', 'auto'], + description : '''Enable support for vmgfx's KMS API.''', +) +option( + 'omap', + type : 'combo', + value : 'false', + choices : ['true', 'false', 'auto'], + description : '''Enable support for OMAP's experimental KMS API.''', +) +option( + 'exynos', + type : 'combo', + value : 'false', + choices : ['true', 'false', 'auto'], + description : '''Enable support for EXYNOS's experimental KMS API.''', +) +option( + 'freedreno', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : '''Enable support for freedreno's KMS API.''', +) +option( + 'tegra', + type : 'combo', + value : 'false', + choices : ['true', 'false', 'auto'], + description : '''Enable support for Tegra's experimental KMS API.''', +) +option( + 'vc4', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : '''Enable support for vc4's KMS API.''', +) +option( + 'etnaviv', + type : 'combo', + value : 'false', + choices : ['true', 'false', 'auto'], + description : '''Enable support for etnaviv's experimental KMS API.''', +) +option( + 'cairo-tests', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : 'Enable support for Cairo rendering in tests.', +) +option( + 'man-pages', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : 'Enable manpage generation and installation.', +) +option( + 'valgrind', + type : 'combo', + value : 'auto', + choices : ['true', 'false', 'auto'], + description : 'Build libdrm with valgrind support.', +) +option( + 'freedreno-kgsl', + type : 'boolean', + value : false, + description : 'Enable support for freedreno to use downstream android kernel API.', +) +option( + 'install-test-programs', + type : 'boolean', + value : false, + description : 'Install test programs.', +) +option( + 'udev', + type : 'boolean', + value : false, + description : 'Enable support for using udev instead of mknod.', +) diff --git a/nouveau/meson.build b/nouveau/meson.build new file mode 100644 index 00000000..bfecf84b --- /dev/null +++ b/nouveau/meson.build @@ -0,0 +1,58 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + + +libdrm_nouveau = shared_library( + 'drm_nouveau', + [files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file], + c_args : warn_c_args, + include_directories : [inc_root, inc_drm], + link_with : libdrm, + dependencies : dep_threads, + version : '2.0.0', + install : true, +) + +ext_libdrm_nouveau = declare_dependency( + link_with : [libdrm, libdrm_nouveau], + include_directories : [inc_drm, include_directories('.')], +) + +install_headers('nouveau.h', subdir : 'libdrm/nouveau') +install_headers( + 'nvif/class.h', 'nvif/cl0080.h', 'nvif/cl9097.h', 'nvif/if0002.h', + 'nvif/if0003.h', 'nvif/ioctl.h', 'nvif/unpack.h', + subdir : 'libdrm/nouveau/nvif' +) + +pkg.generate( + name : 'libdrm_nouveau', + libraries : libdrm_nouveau, + subdirs : ['.', 'nouveau'], + version : meson.project_version(), + requires_private : 'libdrm', + description : 'Userspace interface to nouveau kernel DRM services', +) + +test( + 'nouveau-symbol-check', + prog_bash, + args : [files('nouveau-symbol-check'), libdrm_nouveau] +) diff --git a/omap/meson.build b/omap/meson.build new file mode 100644 index 00000000..1881087f --- /dev/null +++ b/omap/meson.build @@ -0,0 +1,53 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +libdrm_omap = shared_library( + 'drm_omap', + [files('omap_drm.c'), config_file], + include_directories : [inc_root, inc_drm], + c_args : warn_c_args, + link_with : libdrm, + dependencies : [dep_pthread_stubs], + version : '1.0.0', + install : true, +) + +ext_libdrm_omap = declare_dependency( + link_with : [libdrm, libdrm_omap], + include_directories : [inc_drm, include_directories('.')], +) + +install_headers('omap_drmif.h', subdir : 'libdrm') +install_headers('omap_drm.h', subdir : 'omap') + +pkg.generate( + name : 'libdrm_omap', + libraries : libdrm_omap, + subdirs : ['.', 'libdrm', 'omap'], + version : '0.6', + requires_private : 'libdrm', + description : 'Userspace interface to omap kernel DRM services', +) + +test( + 'omap-symbol-check', + prog_bash, + args : [files('omap-symbol-check'), libdrm_omap] +) diff --git a/radeon/meson.build b/radeon/meson.build new file mode 100644 index 00000000..b02166fe --- /dev/null +++ b/radeon/meson.build @@ -0,0 +1,63 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + + +libdrm_radeon = shared_library( + 'drm_radeon', + [ + files( + 'radeon_bo_gem.c', 'radeon_cs_gem.c', 'radeon_cs_space.c', 'radeon_bo.c', + 'radeon_cs.c', 'radeon_surface.c', + ), + config_file, + ], + c_args : warn_c_args, + include_directories : [inc_root, inc_drm], + link_with : libdrm, + dependencies : [dep_pthread_stubs], + version : '1.0.1', + install : true, +) + +ext_libdrm_radeon = declare_dependency( + link_with : [libdrm, libdrm_radeon], + include_directories : [inc_drm, include_directories('.')], +) + +install_headers( + 'radeon_bo.h', 'radeon_cs.h', 'radeon_surface.h', 'radeon_bo_gem.h', + 'radeon_cs_gem.h', 'radeon_bo_int.h', 'radeon_cs_int.h', 'r600_pci_ids.h', + subdir : 'libdrm' +) + +pkg.generate( + name : 'libdrm_radeon', + libraries : libdrm_radeon, + subdirs : ['.', 'libdrm'], + version : meson.project_version(), + requires_private : 'libdrm', + description : 'Userspace interface to kernel DRM services for radeon', +) + +test( + 'radeon-symbol-check', + prog_bash, + args : [files('radeon-symbol-check'), libdrm_radeon] +) diff --git a/tegra/meson.build b/tegra/meson.build new file mode 100644 index 00000000..99fdd194 --- /dev/null +++ b/tegra/meson.build @@ -0,0 +1,52 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +libdrm_tegra = shared_library( + 'drm_tegra', + [files('tegra.c'), config_file], + include_directories : [inc_root, inc_drm], + link_with : libdrm, + dependencies : [dep_pthread_stubs], + c_args : warn_c_args, + version : '0.0.0', + install : true, +) + +ext_libdrm_tegra = declare_dependency( + link_with : [libdrm, libdrm_tegra], + include_directories : [inc_drm, include_directories('.')], +) + +install_headers('tegra.h', subdir : 'libdrm') + +pkg.generate( + name : 'libdrm_tegra', + libraries : libdrm_tegra, + subdirs : ['.', 'libdrm'], + version : meson.project_version(), + requires_private : 'libdrm', + description : 'Userspace interface to Tegra kernel DRM services', +) + +test( + 'tegra-symbol-check', + prog_bash, + args : [files('tegra-symbol-check'), libdrm_tegra] +) diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build new file mode 100644 index 00000000..4c1237c6 --- /dev/null +++ b/tests/amdgpu/meson.build @@ -0,0 +1,34 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +if dep_cunit.found() + amdgpu_test = executable( + 'amdgpu_test', + files( + 'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c', + 'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c', + 'vm_tests.c', + ), + dependencies : [dep_cunit, dep_threads], + include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')], + link_with : [libdrm, libdrm_amdgpu], + install : with_install_tests, + ) +endif diff --git a/tests/etnaviv/meson.build b/tests/etnaviv/meson.build new file mode 100644 index 00000000..8b4a3cfb --- /dev/null +++ b/tests/etnaviv/meson.build @@ -0,0 +1,45 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +inc_etnaviv_tests = [inc_root, inc_drm, include_directories('../../etnaviv')] + +etnaviv_2d_test = executable( + 'etnaviv_2d_test', + files('etnaviv_2d_test.c', 'write_bmp.c'), + include_directories : inc_etnaviv_tests, + link_with : [libdrm, libdrm_etnaviv], + install : with_install_tests, +) + +etnaviv_cmd_stream_test = executable( + 'etnaviv_cmd_stream_test', + files('etnaviv_cmd_stream_test.c'), + include_directories : inc_etnaviv_tests, + link_with : [libdrm, libdrm_etnaviv], + install : with_install_tests, +) + +etnaviv_bo_cache_test = executable( + 'etnaviv_bo_cache_test', + files('etnaviv_bo_cache_test.c'), + include_directories : inc_etnaviv_tests, + link_with : [libdrm, libdrm_etnaviv], + install : with_install_tests, +) diff --git a/tests/exynos/meson.build b/tests/exynos/meson.build new file mode 100644 index 00000000..940c3ce4 --- /dev/null +++ b/tests/exynos/meson.build @@ -0,0 +1,54 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +inc_exynos = include_directories('../../exynos') + +if with_libkms + exynos_fimg2d_test = executable( + 'exynos_fimg2d_test', + files('exynos_fimg2d_test.c'), + c_args : warn_c_args, + include_directories : [inc_root, inc_drm, inc_exynos, + include_directories('../../libkms')], + link_with : [libdrm, libkms, libdrm_exynos], + dependencies : dep_threads, + install : with_install_tests, + ) +endif + +exynos_fimg2d_perf = executable( + 'exynos_fimg2d_perf', + files('exynos_fimg2d_perf.c'), + c_args : warn_c_args, + include_directories : [inc_root, inc_drm, inc_exynos], + link_with : [libdrm, libdrm_exynos], + dependencies : dep_threads, + install : with_install_tests, +) + +exynos_fimg2d_event = executable( + 'exynos_fimg2d_event', + files('exynos_fimg2d_event.c'), + c_args : warn_c_args, + include_directories : [inc_root, inc_drm, inc_exynos], + link_with : [libdrm, libdrm_exynos], + dependencies : dep_threads, + install : with_install_tests, +) diff --git a/tests/kms/meson.build b/tests/kms/meson.build new file mode 100644 index 00000000..1f7f724d --- /dev/null +++ b/tests/kms/meson.build @@ -0,0 +1,49 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + + +libkms_test = static_library( + 'kms-test', + files( + 'libkms-test-crtc.c', 'libkms-test-device.c', 'libkms-test-framebuffer.c', + 'libkms-test-plane.c', 'libkms-test-screen.c', + ), + include_directories : [inc_root, inc_tests, inc_drm], + link_with : libdrm, + c_args : warn_c_args, +) + +kms_steal_crtc = executable( + 'kms-steal-crtc', + files('kms-steal-crtc.c'), + dependencies : dep_cairo, + include_directories : [inc_root, inc_tests, inc_drm], + link_with : [libkms_test, libutil], + install : with_install_tests, +) + +kms_universal_planes = executable( + 'kms-universal-planes', + files('kms-universal-planes.c'), + dependencies : dep_cairo, + include_directories : [inc_root, inc_tests, inc_drm], + link_with : [libkms_test], + install : with_install_tests, +) diff --git a/tests/kmstest/meson.build b/tests/kmstest/meson.build new file mode 100644 index 00000000..a47d4951 --- /dev/null +++ b/tests/kmstest/meson.build @@ -0,0 +1,30 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +kmstest = executable( + 'kmstest', + files('main.c'), + c_args : warn_c_args, + include_directories : [ + inc_root, inc_tests, include_directories('../../libkms'), inc_drm, + ], + link_with : [libutil, libkms, libdrm], + install : with_install_tests, +) diff --git a/tests/meson.build b/tests/meson.build new file mode 100644 index 00000000..fdf950b7 --- /dev/null +++ b/tests/meson.build @@ -0,0 +1,86 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +inc_tests = include_directories('.') + +subdir('util') +subdir('kms') +subdir('modeprint') +subdir('proptest') +subdir('modetest') +subdir('vbltest') +if with_libkms + subdir('kmstest') +endif +if with_radeon + subdir('radeon') +endif +if with_amdgpu + subdir('amdgpu') +endif +if with_exynos + subdir('exynos') +endif +if with_tegra + subdir('tegra') +endif +if with_etnaviv + subdir('etnaviv') +endif +if with_nouveau + subdir('nouveau') +endif + +drmsl = executable( + 'drmsl', + files('drmsl.c'), + include_directories : [inc_root, inc_drm], + link_with : libdrm, + c_args : warn_c_args, +) + +hash = executable( + 'hash', + files('hash.c'), + include_directories : [inc_root, inc_drm], + link_with : libdrm, + c_args : warn_c_args, +) + +random = executable( + 'random', + files('random.c'), + include_directories : [inc_root, inc_drm], + link_with : libdrm, + c_args : warn_c_args, +) + +drmdevice = executable( + 'drmdevice', + files('drmdevice.c'), + include_directories : [inc_root, inc_drm], + link_with : libdrm, + c_args : warn_c_args, +) + +test('random', random, timeout : 240) +test('hash', hash) +test('drmsl', drmsl) +test('drmdevice', drmdevice) diff --git a/tests/modeprint/meson.build b/tests/modeprint/meson.build new file mode 100644 index 00000000..5f0eb24b --- /dev/null +++ b/tests/modeprint/meson.build @@ -0,0 +1,29 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +modeprint = executable( + 'modeprint', + files('modeprint.c'), + c_args : warn_c_args, + include_directories : [inc_root, inc_tests, inc_drm], + link_with : libdrm, + dependencies : dep_threads, + install : with_install_tests, +) diff --git a/tests/modetest/meson.build b/tests/modetest/meson.build new file mode 100644 index 00000000..2a081845 --- /dev/null +++ b/tests/modetest/meson.build @@ -0,0 +1,29 @@ +# Copyright © 2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +modetest = executable( + 'modetest', + files('buffers.c', 'cursor.c', 'modetest.c'), + c_args : [warn_c_args, '-Wno-pointer-arith'], + include_directories : [inc_root, inc_tests, inc_drm], + dependencies : [dep_threads, dep_cairo], + link_with : [libdrm, libutil], + install : with_install_tests, +) diff --git a/tests/nouveau/meson.build b/tests/nouveau/meson.build new file mode 100644 index 00000000..f5d73c1e --- /dev/null +++ b/tests/nouveau/meson.build @@ -0,0 +1,30 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +threaded = executable( + 'threaded', + files('threaded.c'), + dependencies : [dep_dl, dep_threads], + include_directories : [inc_root, inc_drm, include_directories('../../nouveau')], + link_with : [libdrm, libdrm_nouveau], + c_args : warn_c_args, +) + +test('threaded', threaded) diff --git a/tests/proptest/meson.build b/tests/proptest/meson.build new file mode 100644 index 00000000..22d7473e --- /dev/null +++ b/tests/proptest/meson.build @@ -0,0 +1,28 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +proptest = executable( + 'proptest', + files('proptest.c'), + c_args : warn_c_args, + include_directories : [inc_root, inc_tests, inc_drm], + link_with : [libdrm, libutil], + install : with_install_tests, +) diff --git a/tests/radeon/meson.build b/tests/radeon/meson.build new file mode 100644 index 00000000..9e4f916e --- /dev/null +++ b/tests/radeon/meson.build @@ -0,0 +1,27 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +radeon_ttm = executable( + 'radeon_ttm', + files('rbo.c', 'radeon_ttm.c'), + include_directories : [inc_root, inc_drm], + link_with : libdrm, + c_args : warn_c_args, +) diff --git a/tests/tegra/meson.build b/tests/tegra/meson.build new file mode 100644 index 00000000..9c74ac4a --- /dev/null +++ b/tests/tegra/meson.build @@ -0,0 +1,27 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +openclose = executable( + 'openclose', + files('openclose.c'), + include_directories : [inc_root, inc_drm, include_directories('../../tegra')], + c_args : warn_c_args, + link_with : [libdrm, libdrm_tegra], +) diff --git a/tests/util/meson.build b/tests/util/meson.build new file mode 100644 index 00000000..7fa1a4b7 --- /dev/null +++ b/tests/util/meson.build @@ -0,0 +1,28 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + + +libutil = static_library( + 'util', + [files('format.c', 'kms.c', 'pattern.c'), config_file], + include_directories : [inc_root, inc_drm], + link_with : libdrm, + dependencies : dep_cairo +) diff --git a/tests/vbltest/meson.build b/tests/vbltest/meson.build new file mode 100644 index 00000000..ae52ab88 --- /dev/null +++ b/tests/vbltest/meson.build @@ -0,0 +1,28 @@ +# Copyright © 2017-2018 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +vbltest = executable( + 'vbltest', + files('vbltest.c'), + c_args : warn_c_args, + include_directories : [inc_root, inc_tests, inc_drm], + link_with : [libdrm, libutil], + install : with_install_tests, +) diff --git a/vc4/meson.build b/vc4/meson.build new file mode 100644 index 00000000..0136987b --- /dev/null +++ b/vc4/meson.build @@ -0,0 +1,28 @@ +# Copyright © 2017 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +install_headers('vc4_packet.h', 'vc4_qpu_defines.h', subdir : 'libdrm') + +pkg.generate( + name : 'libdrm_vc4', + version : meson.project_version(), + requires_private : 'libdrm', + description : 'Userspace interface to vc4 kernel DRM services', +) -- cgit v1.2.3-54-g00ecf From cc86cbfb1cb79ade0d2261e0a7e848bd7d14a8be Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Fri, 15 Dec 2017 14:34:02 -0800 Subject: autotools: Include meson.build files in tarball Signed-off-by: Dylan Baker Reviewed-by: Eric Engestrom --- Makefile.am | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/Makefile.am b/Makefile.am index 7b86214e..faf0f750 100644 --- a/Makefile.am +++ b/Makefile.am @@ -135,7 +135,37 @@ if HAVE_VMWGFX klibdrminclude_HEADERS += $(LIBDRM_INCLUDE_VMWGFX_H_FILES) endif -EXTRA_DIST = include/drm/README +EXTRA_DIST = \ + include/drm/README \ + amdgpu/meson.build \ + data/meson.build \ + etnaviv/meson.build \ + exynos/meson.build \ + freedreno/meson.build \ + intel/meson.build \ + libkms/meson.build \ + man/meson.build \ + nouveau/meson.build \ + omap/meson.build \ + radeon/meson.build \ + tegra/meson.build \ + tests/amdgpu/meson.build \ + tests/etnaviv/meson.build \ + tests/exynos/meson.build \ + tests/kms/meson.build \ + tests/kmstest/meson.build \ + tests/meson.build \ + tests/modeprint/meson.build \ + tests/modetest/meson.build \ + tests/nouveau/meson.build \ + tests/proptest/meson.build \ + tests/radeon/meson.build \ + tests/tegra/meson.build \ + tests/util/meson.build \ + tests/vbltest/meson.build \ + vc4/meson.build \ + meson.build \ + meson_options.txt copy-headers : cp -r $(kernel_source)/include/uapi/drm/*.h $(top_srcdir)/include/drm/ -- cgit v1.2.3-54-g00ecf From fd9bcb73e9c5a01085069b37c2f5e04300a9b4d4 Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Fri, 15 Dec 2017 14:40:29 -0800 Subject: README: Add note about meson Signed-off-by: Dylan Baker Reviewed-by: Eric Engestrom --- README | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/README b/README index 26cab9d3..f3df9ac1 100644 --- a/README +++ b/README @@ -15,9 +15,27 @@ with an older kernel. Compiling --------- -libdrm is a standard autotools package and follows the normal -configure, build and install steps. The first step is to configure -the package, which is done by running the configure shell script: +libdrm has two build systems, a legacy autotools build system, and a newer +meson build system. The meson build system is much faster, and offers a +slightly different interface, but otherwise provides an equivalent feature set. + +To use it: + + meson builddir/ + +By default this will install into /usr/local, you can change your prefix +with --prefix=/usr (or `meson configure builddir/ -Dprefix=/usr` after +the initial meson setup). + +Then use ninja to build and install: + + ninja -C builddir/ install + +If you are installing into a system location you will need to run install +separately, and as root. + + +Alternatively you can invoke autotools configure: ./configure -- cgit v1.2.3-54-g00ecf From 57d3d4c96887cde016fe1d2766196accf77ca423 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Mon, 8 Jan 2018 11:20:25 +0100 Subject: amdgpu: Don't print error message if parse_one_line returned -EAGAIN It means it just didn't find an entry for the GPU in the amdgpu.ids file. Fixes spurious amdgpu_parse_asic_ids: Cannot parse ASIC IDs: Resource temporarily unavailable error messages in that case. Reported-by: Marek Olšák Reviewed-by: Marek Olšák --- amdgpu/amdgpu_asic_id.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c index 0c8925e5..62459c09 100644 --- a/amdgpu/amdgpu_asic_id.c +++ b/amdgpu/amdgpu_asic_id.c @@ -155,7 +155,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev) if (r == -EINVAL) { fprintf(stderr, "Invalid format: %s: line %d: %s\n", AMDGPU_ASIC_ID_TABLE, line_num, line); - } else if (r) { + } else if (r && r != -EAGAIN) { fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n", __func__, strerror(-r)); } -- cgit v1.2.3-54-g00ecf From 6fe93b8000757e77c3d94f8d8f1b7a22f928de73 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 16 Jan 2018 16:55:53 +0100 Subject: amdgpu: Don't dereference device_handle after amdgpu_device_deinitialize Fixes use after free: ==2537== Invalid read of size 4 ==2537== at 0x1162C9: suite_deadlock_tests_enable (deadlock_tests.c:101) ==2537== by 0x10B157: amdgpu_disable_suits (amdgpu_test.c:421) ==2537== by 0x10B157: main (amdgpu_test.c:560) ==2537== Address 0x5e44f24 is 452 bytes inside a block of size 1,016 free'd ==2537== at 0x4C2BE1B: free (vg_replace_malloc.c:530) ==2537== by 0x504CD8B: amdgpu_device_reference (amdgpu_device.c:164) ==2537== by 0x504CD8B: amdgpu_device_deinitialize (amdgpu_device.c:307) ==2537== by 0x1162BB: suite_deadlock_tests_enable (deadlock_tests.c:97) ==2537== by 0x10B157: amdgpu_disable_suits (amdgpu_test.c:421) ==2537== by 0x10B157: main (amdgpu_test.c:560) ==2537== Block was alloc'd at ==2537== at 0x4C2CC05: calloc (vg_replace_malloc.c:711) ==2537== by 0x504CA5E: amdgpu_device_initialize (amdgpu_device.c:212) ==2537== by 0x116298: suite_deadlock_tests_enable (deadlock_tests.c:93) ==2537== by 0x10B157: amdgpu_disable_suits (amdgpu_test.c:421) ==2537== by 0x10B157: main (amdgpu_test.c:560) Reviewed-by: Christian König --- tests/amdgpu/deadlock_tests.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index 84f4debe..cd34cdf6 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -90,20 +90,21 @@ static void amdgpu_deadlock_compute(void); CU_BOOL suite_deadlock_tests_enable(void) { + CU_BOOL enable = CU_TRUE; + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - if (device_handle->info.family_id == AMDGPU_FAMILY_AI) { printf("\n\nCurrently hangs the CP on this ASIC, deadlock suite disabled\n"); - return CU_FALSE; + enable = CU_FALSE; } - return CU_TRUE; + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + return enable; } int suite_deadlock_tests_init(void) -- cgit v1.2.3-54-g00ecf From 032bb3b11d2d559d2f03008e14dcf8ec10e28150 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Wed, 17 Jan 2018 17:05:31 +0100 Subject: amdgpu: Symlink .editorconfig to tests/amdgpu In order to use consistent editorconfig settings in both amdgpu directories. Reviewed-by: Christian König --- tests/amdgpu/.editorconfig | 1 + 1 file changed, 1 insertion(+) create mode 120000 tests/amdgpu/.editorconfig diff --git a/tests/amdgpu/.editorconfig b/tests/amdgpu/.editorconfig new file mode 120000 index 00000000..70734e42 --- /dev/null +++ b/tests/amdgpu/.editorconfig @@ -0,0 +1 @@ +../../amdgpu/.editorconfig \ No newline at end of file -- cgit v1.2.3-54-g00ecf From 3509e7cd2b9098193b9f8c97ecd68fae929eb131 Mon Sep 17 00:00:00 2001 From: Christoph Haag Date: Thu, 18 Jan 2018 19:01:55 +0100 Subject: meson: fix the install path of amdgpu.ids Signed-off-by: Dylan Baker --- amdgpu/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/amdgpu/meson.build b/amdgpu/meson.build index 55ab9d1d..8b045205 100644 --- a/amdgpu/meson.build +++ b/amdgpu/meson.build @@ -19,7 +19,7 @@ # SOFTWARE. -datadir_amdgpu = join_paths(get_option('datadir'), 'libdrm', 'amdgpu.ids') +datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm') libdrm_amdgpu = shared_library( 'drm_amdgpu', @@ -33,7 +33,7 @@ libdrm_amdgpu = shared_library( ], c_args : [ warn_c_args, - '-DAMDGPU_ASIC_ID_TABLE="@0@"'.format(datadir_amdgpu), + '-DAMDGPU_ASIC_ID_TABLE="@0@"'.format(join_paths(datadir_amdgpu, 'amdgpu.ids')), ], include_directories : [inc_root, inc_drm], link_with : libdrm, -- cgit v1.2.3-54-g00ecf From 1cc17744b988106b4fe71ee9d3d17b651d6adb40 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 22 Jan 2018 13:17:30 +0100 Subject: amdgpu: fix high VA mask That constant needs to be 64bits. Fixes: amdgpu: use the high VA range if possible v2 Signed-off-by: Christian König Reviewed-by: Alex Deucher --- amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index a0d01727..f34e27a9 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -272,7 +272,7 @@ int amdgpu_device_initialize(int fd, max = dev->dev_info.virtual_address_max; } - max = MIN2(max, (start & ~0xffffffff) + 0x100000000ULL); + max = MIN2(max, (start & ~0xffffffffULL) + 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); -- cgit v1.2.3-54-g00ecf From 6736ad45d88c4ce16c6f76fd128fae73b51ea2dc Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Wed, 10 Jan 2018 11:16:41 +0900 Subject: modetest: Fix to check return value of asprintf() There is warning about ignoring return value of 'asprintf'. Fix to check return value of asprintf(). Signed-off-by: Seung-Woo Kim Reviewed-by: Eric Engestrom --- tests/modetest/modetest.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index 62d93327..0773bd02 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -656,10 +656,13 @@ static struct resources *get_resources(struct device *dev) for (i = 0; i < res->res->count_connectors; i++) { struct connector *connector = &res->connectors[i]; drmModeConnector *conn = connector->connector; + int num; - asprintf(&connector->name, "%s-%u", + num = asprintf(&connector->name, "%s-%u", util_lookup_connector_type_name(conn->connector_type), conn->connector_type_id); + if (num < 0) + goto error; } #define get_properties(_res, __res, type, Type) \ -- cgit v1.2.3-54-g00ecf From 7e28d73af018d02b5e1827769d61e04f73e50d69 Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Fri, 12 Jan 2018 11:51:17 -0800 Subject: meson: set proper pkg-config version for libdrm_freedreno Copy and paste error from exynos. Signed-off-by: Dylan Baker Reviewed-by: Emil Velikov Reviewed-by: Eric Engestrom --- freedreno/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/freedreno/meson.build b/freedreno/meson.build index b4035e19..de6a413f 100644 --- a/freedreno/meson.build +++ b/freedreno/meson.build @@ -64,7 +64,7 @@ pkg.generate( name : 'libdrm_freedreno', libraries : libdrm_freedreno, subdirs : ['.', 'libdrm', 'freedreno'], - version : '0.7', + version : meson.project_version(), requires_private : 'libdrm', description : 'Userspace interface to freedreno kernel DRM services', ) -- cgit v1.2.3-54-g00ecf From 5df936718df62a8d1f696ff0f5fe7984aa35150b Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Fri, 12 Jan 2018 11:53:39 -0800 Subject: meson: set the minimum version correctly Currently we ask for 0.42, but we actually require 0.43 because we pass file objects as arguments to tests. If someone needs version 0.42 it wouldn't be hard, just a lot of replacing files() with strings. Signed-off-by: Dylan Baker Reviewed-by: Emil Velikov Reviewed-by: Eric Engestrom --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 05566081..d7a50cf9 100644 --- a/meson.build +++ b/meson.build @@ -23,7 +23,7 @@ project( ['c'], version : '2.4.89', license : 'MIT', - meson_version : '>= 0.42', + meson_version : '>= 0.43', default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], ) -- cgit v1.2.3-54-g00ecf From 5e239f3e3d18e13e6ffa3128407d37b3c7582593 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 25 Jan 2018 13:00:54 -0500 Subject: amdgpu: Update deadlock test to not assert on ECANCELED Kernel will abort jobs for guilty (causing GPU hang) context with -ECANCELED don't assert if that the case. Signed-off-by: Andrey Grodzovsky Acked-by: Christian König --- tests/amdgpu/deadlock_tests.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index cd34cdf6..9a428858 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -230,7 +230,7 @@ static void amdgpu_deadlock_helper(unsigned ip_type) for (i = 0; i < 200; i++) { r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); } @@ -243,7 +243,7 @@ static void amdgpu_deadlock_helper(unsigned ip_type) r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE,0, &expired); - CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); r = amdgpu_bo_list_destroy(bo_list); CU_ASSERT_EQUAL(r, 0); -- cgit v1.2.3-54-g00ecf From 429bb5820d2bb1e99dba15c05e912226be1ad1fc Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 25 Jan 2018 13:03:32 -0500 Subject: amdgpu: Fix segfault in deadlock test. If amdgpu_cs_query_fence_status terminates prematurely the BO sometimes is unmapped before helper thread writes a vlaue into it causing a segfault. Signed-off-by: Andrey Grodzovsky --- tests/amdgpu/deadlock_tests.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index 9a428858..fc49c48a 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -245,6 +245,8 @@ static void amdgpu_deadlock_helper(unsigned ip_type) AMDGPU_TIMEOUT_INFINITE,0, &expired); CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); + pthread_join(stress_thread, NULL); + r = amdgpu_bo_list_destroy(bo_list); CU_ASSERT_EQUAL(r, 0); @@ -254,6 +256,4 @@ static void amdgpu_deadlock_helper(unsigned ip_type) r = amdgpu_cs_ctx_free(context_handle); CU_ASSERT_EQUAL(r, 0); - - pthread_join(stress_thread, NULL); } -- cgit v1.2.3-54-g00ecf From 8e75f5a1453b1699b91992493e2d2e2a6236965c Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 16 Jan 2018 16:48:45 +0100 Subject: amdgpu: Disable deadlock test suite by default for SI ASICs Hangs my Cape Verde. Acked-by: Christian König --- tests/amdgpu/deadlock_tests.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index fc49c48a..aaeea871 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -96,7 +96,8 @@ CU_BOOL suite_deadlock_tests_enable(void) &minor_version, &device_handle)) return CU_FALSE; - if (device_handle->info.family_id == AMDGPU_FAMILY_AI) { + if (device_handle->info.family_id == AMDGPU_FAMILY_AI || + device_handle->info.family_id == AMDGPU_FAMILY_SI) { printf("\n\nCurrently hangs the CP on this ASIC, deadlock suite disabled\n"); enable = CU_FALSE; } -- cgit v1.2.3-54-g00ecf From 82aef5f0cbeb5145408f8c5979dc826937d51b7b Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 16 Jan 2018 16:49:45 +0100 Subject: amdgpu: Disable VM test suite by default for SI ASICs Hangs my Cape Verde. Acked-by: Christian König --- tests/amdgpu/amdgpu_test.c | 2 +- tests/amdgpu/amdgpu_test.h | 5 +++++ tests/amdgpu/vm_tests.c | 20 ++++++++++++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 8fa3399a..cbeb1ee8 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -167,7 +167,7 @@ static Suites_Active_Status suites_active_stat[] = { }, { .pName = VM_TESTS_STR, - .pActive = always_active, + .pActive = suite_vm_tests_enable, }, }; diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 3238e05f..1db803c6 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -184,6 +184,11 @@ int suite_vm_tests_init(); */ int suite_vm_tests_clean(); +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_vm_tests_enable(void); + /** * Tests in vm test suite */ diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c index 5f183107..4b0121ff 100644 --- a/tests/amdgpu/vm_tests.c +++ b/tests/amdgpu/vm_tests.c @@ -25,6 +25,7 @@ #include "amdgpu_test.h" #include "amdgpu_drm.h" +#include "amdgpu_internal.h" static amdgpu_device_handle device_handle; static uint32_t major_version; @@ -33,6 +34,25 @@ static uint32_t minor_version; static void amdgpu_vmid_reserve_test(void); +CU_BOOL suite_vm_tests_enable(void) +{ + CU_BOOL enable = CU_TRUE; + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + if (device_handle->info.family_id == AMDGPU_FAMILY_SI) { + printf("\n\nCurrently hangs the CP on this ASIC, VM suite disabled\n"); + enable = CU_FALSE; + } + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + return enable; +} + int suite_vm_tests_init(void) { struct amdgpu_gpu_info gpu_info = {0}; -- cgit v1.2.3-54-g00ecf From 6f0f6cee5e9be1dcf816c144e05d26352c85a9e8 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 24 Jan 2018 15:08:46 -0500 Subject: freedreno: clamp priority based on # of rings In case of a kernel that is new enough to support multiple submit- queues, but with an adreno generation which doesn't support multiple prioritized ringbuffers, we'd attempt to open a submit-queue with prio=1 (medium), which is rejected by the kernel. This could happen either w/ an older mesa (which uses fd_pipe_new()) or a newer mesa which defaults to prio=1 if no pipe context priority flags are set. The simple answer to fix both cases is to clamp the requested priority according to the number of rings. This might not do exactly what you want, if we hypothetically had 2 rings (it would result in requested medium priority being high priority instead of low priority). But the number of rings (for hw gen's that support this) is purely a software construct, so the easy answer there is to have the kernel advertise at least 3 rings if it supports more than one. There isn't really any reason to do otherwise. Signed-off-by: Rob Clark --- freedreno/freedreno_priv.h | 2 +- freedreno/msm/msm_pipe.c | 28 +++++++++++++++++----------- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index 27307472..199ccb94 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -49,6 +49,7 @@ #include "xf86atomic.h" #include "util_double_list.h" +#include "util_math.h" #include "freedreno_drmif.h" #include "freedreno_ringbuffer.h" @@ -173,7 +174,6 @@ struct fd_bo { time_t free_time; /* time when added to bucket-list */ }; -#define ALIGN(v,a) (((v) + (a) - 1) & ~((a) - 1)) #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) #define enable_debug 0 /* TODO make dynamic */ diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c index 7395e573..12e4be59 100644 --- a/freedreno/msm/msm_pipe.c +++ b/freedreno/msm/msm_pipe.c @@ -100,42 +100,48 @@ static int msm_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp, return 0; } -static int open_submitqueue(struct fd_device *dev, uint32_t prio, - uint32_t *queue_id) +static int open_submitqueue(struct fd_pipe *pipe, uint32_t prio) { struct drm_msm_submitqueue req = { .flags = 0, .prio = prio, }; + uint64_t nr_rings = 1; int ret; - if (fd_device_version(dev) < FD_VERSION_SUBMIT_QUEUES) { - *queue_id = 0; + if (fd_device_version(pipe->dev) < FD_VERSION_SUBMIT_QUEUES) { + to_msm_pipe(pipe)->queue_id = 0; return 0; } - ret = drmCommandWriteRead(dev->fd, DRM_MSM_SUBMITQUEUE_NEW, &req, sizeof(req)); + msm_pipe_get_param(pipe, FD_NR_RINGS, &nr_rings); + + req.prio = MIN2(req.prio, MAX2(nr_rings, 1) - 1); + + ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_NEW, + &req, sizeof(req)); if (ret) { ERROR_MSG("could not create submitqueue! %d (%s)", ret, strerror(errno)); return ret; } - *queue_id = req.id; + to_msm_pipe(pipe)->queue_id = req.id; return 0; } -static void close_submitqueue(struct fd_device *dev, uint32_t queue_id) +static void close_submitqueue(struct fd_pipe *pipe, uint32_t queue_id) { - if (fd_device_version(dev) < FD_VERSION_SUBMIT_QUEUES) + if (fd_device_version(pipe->dev) < FD_VERSION_SUBMIT_QUEUES) return; - drmCommandWrite(dev->fd, DRM_MSM_SUBMITQUEUE_CLOSE, &queue_id, sizeof(queue_id)); + drmCommandWrite(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_CLOSE, + &queue_id, sizeof(queue_id)); } static void msm_pipe_destroy(struct fd_pipe *pipe) { struct msm_pipe *msm_pipe = to_msm_pipe(pipe); - close_submitqueue(pipe->dev, msm_pipe->queue_id); + close_submitqueue(pipe, msm_pipe->queue_id); free(msm_pipe); } @@ -193,7 +199,7 @@ drm_private struct fd_pipe * msm_pipe_new(struct fd_device *dev, INFO_MSG(" Chip-id: 0x%08x", msm_pipe->chip_id); INFO_MSG(" GMEM size: 0x%08x", msm_pipe->gmem); - if (open_submitqueue(dev, prio, &msm_pipe->queue_id)) + if (open_submitqueue(pipe, prio)) goto fail; return pipe; -- cgit v1.2.3-54-g00ecf From 089d45456b618f78d461c6271fbdfb42ce09fc3e Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 5 Jan 2018 15:32:14 +0000 Subject: remove unnecessary double-semicolon Signed-off-by: Eric Engestrom Reviewed-by: Christian König Reviewed-by: Emil Velikov --- amdgpu/amdgpu_cs.c | 2 +- tests/exynos/exynos_fimg2d_test.c | 2 +- tests/modeprint/modeprint.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 987daa40..46dffe1d 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -582,7 +582,7 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem) if (!sem || !sem->signal_fence.context) return -EINVAL; - sem->signal_fence.context = NULL;; + sem->signal_fence.context = NULL; sem->signal_fence.ip_type = 0; sem->signal_fence.ip_instance = 0; sem->signal_fence.ring = 0; diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index b71cf593..14d304d3 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -533,7 +533,7 @@ err_free_userptr: fail: g2d_fini(ctx); - return ret;; + return ret; } #if EXYNOS_G2D_USERPTR_TEST diff --git a/tests/modeprint/modeprint.c b/tests/modeprint/modeprint.c index 0d854103..c81dd91d 100644 --- a/tests/modeprint/modeprint.c +++ b/tests/modeprint/modeprint.c @@ -244,7 +244,7 @@ static int printFrameBuffer(int fd, drmModeResPtr res, drmModeFBPtr fb) printf("\thandle : %i\n", fb->handle); printf("\twidth : %i\n", fb->width); printf("\theight : %i\n", fb->height); - printf("\tpitch : %i\n", fb->pitch);; + printf("\tpitch : %i\n", fb->pitch); printf("\tbpp : %i\n", fb->bpp); printf("\tdepth : %i\n", fb->depth); printf("\tbuffer_id : %i\n", fb->handle); -- cgit v1.2.3-54-g00ecf From c6fcd176e8949148ad2e07b0ee970cd1ad287113 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 11:12:06 +0000 Subject: tests/amdgpu: add parentheses to make operation priority explicit While at it, align with the other half on the next line. Cc: Andrey Grodzovsky Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- tests/amdgpu/basic_tests.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 0f75e896..6ee0aa3b 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -1608,7 +1608,7 @@ static void amdgpu_sync_dependency_test(void) j = i; ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3); ptr[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; - ptr[i++] = 0xfffffffc & ib_result_mc_address + DATA_OFFSET * 4; + ptr[i++] = 0xfffffffc & (ib_result_mc_address + DATA_OFFSET * 4); ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32; ptr[i++] = 99; -- cgit v1.2.3-54-g00ecf From 80f33f4529710f5a24583ab5189d00cc7cb0d62b Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Thu, 25 Jan 2018 11:24:03 +0000 Subject: tests/amdgpu: drop unused variables Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- tests/amdgpu/amdgpu_test.c | 1 - tests/amdgpu/basic_tests.c | 4 ++-- tests/amdgpu/cs_tests.c | 2 +- tests/amdgpu/deadlock_tests.c | 3 +-- tests/amdgpu/uvd_enc_tests.c | 5 +---- tests/amdgpu/vcn_tests.c | 2 +- tests/amdgpu/vm_tests.c | 4 +--- 7 files changed, 7 insertions(+), 14 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index cbeb1ee8..4f766aaf 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -243,7 +243,6 @@ static const char options[] = "hlrps:t:b:d:f"; static int amdgpu_open_devices(int open_render_node) { drmDevicePtr devices[MAX_CARDS_SUPPORTED]; - int ret; int i; int drm_node; int amd_index = 0; diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 6ee0aa3b..354b0157 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -681,7 +681,7 @@ static void amdgpu_command_submission_compute_nop(void) struct amdgpu_cs_fence fence_status; uint32_t *ptr; uint32_t expired; - int i, r, instance; + int r, instance; amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle; struct drm_amdgpu_info_hw_ip info; @@ -1473,7 +1473,7 @@ static void amdgpu_sync_dependency_test(void) struct amdgpu_cs_ib_info ib_info; struct amdgpu_cs_fence fence_status; uint32_t expired; - int i, j, r, instance; + int i, j, r; amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle; static uint32_t *ptr; diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index 4880b74f..a5361cd5 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -273,7 +273,7 @@ static void amdgpu_cs_uvd_create(void) static void amdgpu_cs_uvd_decode(void) { - const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280; + const unsigned dpb_size = 15923584, dt_size = 737280; uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr; struct amdgpu_bo_alloc_request req = {0}; amdgpu_bo_handle buf_handle; diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index aaeea871..96c99c96 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -110,7 +110,6 @@ CU_BOOL suite_deadlock_tests_enable(void) int suite_deadlock_tests_init(void) { - struct amdgpu_gpu_info gpu_info = {0}; int r; r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, @@ -177,7 +176,7 @@ static void amdgpu_deadlock_helper(unsigned ip_type) struct amdgpu_cs_ib_info ib_info; struct amdgpu_cs_fence fence_status; uint32_t expired; - int i, r, instance; + int i, r; amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle; diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index bed8494a..0377c1a5 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -247,8 +247,6 @@ static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) static void amdgpu_cs_uvd_enc_create(void) { - int len, r; - enc.width = 160; enc.height = 128; @@ -263,7 +261,7 @@ static void check_result(struct amdgpu_uvd_enc *enc) uint64_t sum; uint32_t s = 175602; uint32_t *ptr, size; - int i, j, r; + int j, r; r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr); CU_ASSERT_EQUAL(r, 0); @@ -470,7 +468,6 @@ static void amdgpu_cs_uvd_enc_encode(void) static void amdgpu_cs_uvd_enc_destroy(void) { - struct amdgpu_uvd_enc_bo sw_ctx; int len, r; num_resources = 0; diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c index 9224bc37..2eb8c434 100644 --- a/tests/amdgpu/vcn_tests.c +++ b/tests/amdgpu/vcn_tests.c @@ -283,7 +283,7 @@ static void amdgpu_cs_vcn_dec_create(void) static void amdgpu_cs_vcn_dec_decode(void) { - const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280; + const unsigned dpb_size = 15923584, dt_size = 737280; uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum; struct amdgpu_vcn_bo dec_buf; int size, len, i, r; diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c index 4b0121ff..7b6dc5d6 100644 --- a/tests/amdgpu/vm_tests.c +++ b/tests/amdgpu/vm_tests.c @@ -55,7 +55,6 @@ CU_BOOL suite_vm_tests_enable(void) int suite_vm_tests_init(void) { - struct amdgpu_gpu_info gpu_info = {0}; int r; r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, @@ -98,10 +97,9 @@ static void amdgpu_vmid_reserve_test(void) struct amdgpu_cs_ib_info ib_info; struct amdgpu_cs_fence fence_status; uint32_t expired, flags; - int i, r, instance; + int i, r; amdgpu_bo_list_handle bo_list; amdgpu_va_handle va_handle; - union drm_amdgpu_vm vm; static uint32_t *ptr; r = amdgpu_cs_ctx_create(device_handle, &context_handle); -- cgit v1.2.3-54-g00ecf From 256cdc02a89a6ad51f9ba7bebc6d1ade20f8bfa8 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 11:05:28 +0000 Subject: tests/util: fix signed/unsigned comparisons Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- tests/util/pattern.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/util/pattern.c b/tests/util/pattern.c index 00b08a8c..095eadf2 100644 --- a/tests/util/pattern.c +++ b/tests/util/pattern.c @@ -549,7 +549,6 @@ static void make_pwetty(void *data, unsigned int width, unsigned int height, #ifdef HAVE_CAIRO cairo_surface_t *surface; cairo_t *cr; - int x, y; cairo_format_t cairo_format; /* we can ignore the order of R,G,B channels */ @@ -576,8 +575,8 @@ static void make_pwetty(void *data, unsigned int width, unsigned int height, cairo_surface_destroy(surface); cairo_set_line_cap(cr, CAIRO_LINE_CAP_SQUARE); - for (x = 0; x < width; x += 250) - for (y = 0; y < height; y += 250) { + for (unsigned x = 0; x < width; x += 250) + for (unsigned y = 0; y < height; y += 250) { char buf[64]; cairo_move_to(cr, x, y - 20); -- cgit v1.2.3-54-g00ecf From 28052ad589babf12938acc89d349c8b356e838aa Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 11:05:09 +0000 Subject: tests/util: drop unused parameters Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- tests/util/pattern.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/util/pattern.c b/tests/util/pattern.c index 095eadf2..2366b006 100644 --- a/tests/util/pattern.c +++ b/tests/util/pattern.c @@ -823,8 +823,8 @@ static void fill_tiles(const struct util_format_info *info, void *planes[3], } } -static void fill_plain(const struct util_format_info *info, void *planes[3], - unsigned int width, unsigned int height, +static void fill_plain(void *planes[3], + unsigned int height, unsigned int stride) { memset(planes[0], 0x77, stride * height); @@ -860,7 +860,7 @@ void util_fill_pattern(uint32_t format, enum util_fill_pattern pattern, return fill_smpte(info, planes, width, height, stride); case UTIL_PATTERN_PLAIN: - return fill_plain(info, planes, width, height, stride); + return fill_plain(planes, height, stride); default: printf("Error: unsupported test pattern %u.\n", pattern); -- cgit v1.2.3-54-g00ecf From 44867b0eefcd8f14923bc8849bcb38f445f9120e Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 11:03:32 +0000 Subject: tests/etnaviv: drop unused `return 0` Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- tests/etnaviv/write_bmp.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/etnaviv/write_bmp.c b/tests/etnaviv/write_bmp.c index 7ae0646c..f7b6bc69 100644 --- a/tests/etnaviv/write_bmp.c +++ b/tests/etnaviv/write_bmp.c @@ -63,7 +63,7 @@ struct dib_header { unsigned int unused[12]; } __attribute__((__packed__)); -static int +static void bmp_header_write(int fd, int width, int height, int bgra, int noflip, int alpha) { struct bmp_header bmp_header = { @@ -98,8 +98,6 @@ bmp_header_write(int fd, int width, int height, int bgra, int noflip, int alpha) write(fd, &bmp_header, sizeof(struct bmp_header)); write(fd, &dib_header, sizeof(struct dib_header)); - - return 0; } void -- cgit v1.2.3-54-g00ecf From 52689eebeb060df52fbca4009a076961cdf78edb Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 15:34:03 +0000 Subject: meson: add missing HAVE_RADEON Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index d7a50cf9..6bd528a6 100644 --- a/meson.build +++ b/meson.build @@ -255,7 +255,7 @@ foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_nouveau, 'NOUVEAU'], [with_omap, 'OMAP'], [with_exynos, 'EXYNOS'], [with_freedreno, 'FREEDRENO'], [with_tegra, 'TEGRA'], [with_vc4, 'VC4'], - [with_etnaviv, 'ETNAVIV']] + [with_etnaviv, 'ETNAVIV'], [with_radeon, 'RADEON']] if t[0] config.set10('HAVE_@0@'.format(t[1]), true) endif -- cgit v1.2.3-54-g00ecf From a7434d3618c5a1a3d3006fdb158acd86a5d9380e Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:05:03 +0000 Subject: configure: remove unused HAVE_CUNIT define Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 -- 1 file changed, 2 deletions(-) diff --git a/configure.ac b/configure.ac index 35378b33..1ea36020 100644 --- a/configure.ac +++ b/configure.ac @@ -424,8 +424,6 @@ AM_CONDITIONAL(HAVE_AMDGPU, [test "x$AMDGPU" = xyes]) if test "x$AMDGPU" = xyes; then AC_DEFINE(HAVE_AMDGPU, 1, [Have amdgpu support]) - AC_DEFINE(HAVE_CUNIT, [test "x$have_cunit" != "xno"], [Enable CUNIT Have amdgpu support]) - if test "x$have_cunit" = "xno"; then AC_MSG_WARN([Could not find cunit library. Disabling amdgpu tests]) fi -- cgit v1.2.3-54-g00ecf From c56db628c77ecc734bfa00d773cc1717c8c1f825 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:05:45 +0000 Subject: configure: remove unused HAVE_INSTALL_TESTS define Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 3 --- 1 file changed, 3 deletions(-) diff --git a/configure.ac b/configure.ac index 1ea36020..7f114a73 100644 --- a/configure.ac +++ b/configure.ac @@ -445,9 +445,6 @@ if test "x$ETNAVIV" = xyes; then fi AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) -if test "x$INSTALL_TESTS" = xyes; then - AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs]) -fi AC_ARG_ENABLE([cairo-tests], [AS_HELP_STRING([--enable-cairo-tests], -- cgit v1.2.3-54-g00ecf From de9be0bebf242a6ceb5ad41a714a9d0306c6f4f1 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:10:04 +0000 Subject: meson,configure: remove unused HAVE_OMAP define Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 3 --- meson.build | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index 7f114a73..11e94e13 100644 --- a/configure.ac +++ b/configure.ac @@ -371,9 +371,6 @@ if test "x$NOUVEAU" = xyes; then fi AM_CONDITIONAL(HAVE_OMAP, [test "x$OMAP" = xyes]) -if test "x$OMAP" = xyes; then - AC_DEFINE(HAVE_OMAP, 1, [Have OMAP support]) -fi AM_CONDITIONAL(HAVE_EXYNOS, [test "x$EXYNOS" = xyes]) if test "x$EXYNOS" = xyes; then diff --git a/meson.build b/meson.build index 6bd528a6..4310bdf2 100644 --- a/meson.build +++ b/meson.build @@ -252,7 +252,7 @@ if cc.compiles('''int foo_hidden(void) __attribute__((visibility(("hidden"))));' endif foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], - [with_nouveau, 'NOUVEAU'], [with_omap, 'OMAP'], + [with_nouveau, 'NOUVEAU'], [with_exynos, 'EXYNOS'], [with_freedreno, 'FREEDRENO'], [with_tegra, 'TEGRA'], [with_vc4, 'VC4'], [with_etnaviv, 'ETNAVIV'], [with_radeon, 'RADEON']] -- cgit v1.2.3-54-g00ecf From 052ef66f06ae10f49129020137e6cadf3298c540 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:16:13 +0000 Subject: meson,configure: remove unused HAVE_TEGRA define Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 3 --- meson.build | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index 11e94e13..c12f8b54 100644 --- a/configure.ac +++ b/configure.ac @@ -427,9 +427,6 @@ if test "x$AMDGPU" = xyes; then fi AM_CONDITIONAL(HAVE_TEGRA, [test "x$TEGRA" = xyes]) -if test "x$TEGRA" = xyes; then - AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support]) -fi AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) if test "x$VC4" = xyes; then diff --git a/meson.build b/meson.build index 4310bdf2..fc70c4f4 100644 --- a/meson.build +++ b/meson.build @@ -254,7 +254,7 @@ endif foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_nouveau, 'NOUVEAU'], [with_exynos, 'EXYNOS'], [with_freedreno, 'FREEDRENO'], - [with_tegra, 'TEGRA'], [with_vc4, 'VC4'], + [with_vc4, 'VC4'], [with_etnaviv, 'ETNAVIV'], [with_radeon, 'RADEON']] if t[0] config.set10('HAVE_@0@'.format(t[1]), true) -- cgit v1.2.3-54-g00ecf From 2cd9105db60714c4c9f9e89625da920b4940455f Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:17:53 +0000 Subject: meson,configure: remove unused HAVE_FREEDRENO define Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 3 --- meson.build | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index c12f8b54..83f2e4c2 100644 --- a/configure.ac +++ b/configure.ac @@ -378,9 +378,6 @@ if test "x$EXYNOS" = xyes; then fi AM_CONDITIONAL(HAVE_FREEDRENO, [test "x$FREEDRENO" = xyes]) -if test "x$FREEDRENO" = xyes; then - AC_DEFINE(HAVE_FREEDRENO, 1, [Have freedreno support]) -fi if test "x$FREEDRENO_KGSL" = xyes; then if test "x$FREEDRENO" != xyes; then diff --git a/meson.build b/meson.build index fc70c4f4..049ef3c3 100644 --- a/meson.build +++ b/meson.build @@ -253,7 +253,7 @@ endif foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_nouveau, 'NOUVEAU'], - [with_exynos, 'EXYNOS'], [with_freedreno, 'FREEDRENO'], + [with_exynos, 'EXYNOS'], [with_vc4, 'VC4'], [with_etnaviv, 'ETNAVIV'], [with_radeon, 'RADEON']] if t[0] -- cgit v1.2.3-54-g00ecf From 540827cc7da2228ae54947adcbf33555a48d0b1c Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:19:23 +0000 Subject: meson,configure: remove unused HAVE_ETNAVIV define Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 3 --- meson.build | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index 83f2e4c2..6bb8d9f5 100644 --- a/configure.ac +++ b/configure.ac @@ -431,9 +431,6 @@ if test "x$VC4" = xyes; then fi AM_CONDITIONAL(HAVE_ETNAVIV, [test "x$ETNAVIV" = xyes]) -if test "x$ETNAVIV" = xyes; then - AC_DEFINE(HAVE_ETNAVIV, 1, [Have etnaviv support]) -fi AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) diff --git a/meson.build b/meson.build index 049ef3c3..fa00254b 100644 --- a/meson.build +++ b/meson.build @@ -255,7 +255,7 @@ foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_nouveau, 'NOUVEAU'], [with_exynos, 'EXYNOS'], [with_vc4, 'VC4'], - [with_etnaviv, 'ETNAVIV'], [with_radeon, 'RADEON']] + [with_radeon, 'RADEON']] if t[0] config.set10('HAVE_@0@'.format(t[1]), true) endif -- cgit v1.2.3-54-g00ecf From ee47329bef727a109418f7134638e0fe67210748 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:21:30 +0000 Subject: meson,configure: always define HAVE_{INTEL,VMWGFX,NOUVEAU,EXYNOS,VC4,RADEON} Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 14 ++++++++++++++ libkms/linux.c | 10 +++++----- meson.build | 4 +--- 3 files changed, 20 insertions(+), 8 deletions(-) diff --git a/configure.ac b/configure.ac index 6bb8d9f5..32ceba69 100644 --- a/configure.ac +++ b/configure.ac @@ -358,16 +358,22 @@ AM_CONDITIONAL(HAVE_LIBKMS, [test "x$LIBKMS" = xyes]) AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" = xyes]) if test "x$INTEL" = xyes; then AC_DEFINE(HAVE_INTEL, 1, [Have intel support]) +else + AC_DEFINE(HAVE_INTEL, 0) fi AM_CONDITIONAL(HAVE_VMWGFX, [test "x$VMWGFX" = xyes]) if test "x$VMWGFX" = xyes; then AC_DEFINE(HAVE_VMWGFX, 1, [Have vmwgfx kernel headers]) +else + AC_DEFINE(HAVE_VMWGFX, 0) fi AM_CONDITIONAL(HAVE_NOUVEAU, [test "x$NOUVEAU" = xyes]) if test "x$NOUVEAU" = xyes; then AC_DEFINE(HAVE_NOUVEAU, 1, [Have nouveau (nvidia) support]) +else + AC_DEFINE(HAVE_NOUVEAU, 0) fi AM_CONDITIONAL(HAVE_OMAP, [test "x$OMAP" = xyes]) @@ -375,6 +381,8 @@ AM_CONDITIONAL(HAVE_OMAP, [test "x$OMAP" = xyes]) AM_CONDITIONAL(HAVE_EXYNOS, [test "x$EXYNOS" = xyes]) if test "x$EXYNOS" = xyes; then AC_DEFINE(HAVE_EXYNOS, 1, [Have EXYNOS support]) +else + AC_DEFINE(HAVE_EXYNOS, 0) fi AM_CONDITIONAL(HAVE_FREEDRENO, [test "x$FREEDRENO" = xyes]) @@ -392,6 +400,8 @@ fi AM_CONDITIONAL(HAVE_RADEON, [test "x$RADEON" = xyes]) if test "x$RADEON" = xyes; then AC_DEFINE(HAVE_RADEON, 1, [Have radeon support]) +else + AC_DEFINE(HAVE_RADEON, 0) fi if test "x$AMDGPU" != xno; then @@ -421,6 +431,8 @@ if test "x$AMDGPU" = xyes; then if test "x$have_cunit" = "xno"; then AC_MSG_WARN([Could not find cunit library. Disabling amdgpu tests]) fi +else + AC_DEFINE(HAVE_AMDGPU, 0) fi AM_CONDITIONAL(HAVE_TEGRA, [test "x$TEGRA" = xyes]) @@ -428,6 +440,8 @@ AM_CONDITIONAL(HAVE_TEGRA, [test "x$TEGRA" = xyes]) AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) if test "x$VC4" = xyes; then AC_DEFINE(HAVE_VC4, 1, [Have VC4 support]) +else + AC_DEFINE(HAVE_VC4, 0) fi AM_CONDITIONAL(HAVE_ETNAVIV, [test "x$ETNAVIV" = xyes]) diff --git a/libkms/linux.c b/libkms/linux.c index 0b50777e..1431eb10 100644 --- a/libkms/linux.c +++ b/libkms/linux.c @@ -110,27 +110,27 @@ linux_from_sysfs(int fd, struct kms_driver **out) if (ret) return ret; -#ifdef HAVE_INTEL +#if HAVE_INTEL if (!strcmp(name, "intel")) ret = intel_create(fd, out); else #endif -#ifdef HAVE_VMWGFX +#if HAVE_VMWGFX if (!strcmp(name, "vmwgfx")) ret = vmwgfx_create(fd, out); else #endif -#ifdef HAVE_NOUVEAU +#if HAVE_NOUVEAU if (!strcmp(name, "nouveau")) ret = nouveau_create(fd, out); else #endif -#ifdef HAVE_RADEON +#if HAVE_RADEON if (!strcmp(name, "radeon")) ret = radeon_create(fd, out); else #endif -#ifdef HAVE_EXYNOS +#if HAVE_EXYNOS if (!strcmp(name, "exynos")) ret = exynos_create(fd, out); else diff --git a/meson.build b/meson.build index fa00254b..7298f741 100644 --- a/meson.build +++ b/meson.build @@ -256,9 +256,7 @@ foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_exynos, 'EXYNOS'], [with_vc4, 'VC4'], [with_radeon, 'RADEON']] - if t[0] - config.set10('HAVE_@0@'.format(t[1]), true) - endif + config.set10('HAVE_@0@'.format(t[1]), t[0]) endforeach if with_freedreno_kgsl if not with_freedreno -- cgit v1.2.3-54-g00ecf From ec53f4808c8ccd73cd2dbed8b53a4e961e3a2b76 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 15:19:03 +0000 Subject: always define HAVE_FREEDRENO_KGSL Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 ++ freedreno/freedreno_bo.c | 2 +- freedreno/freedreno_device.c | 2 +- meson.build | 8 +++----- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/configure.ac b/configure.ac index 32ceba69..e19fdc99 100644 --- a/configure.ac +++ b/configure.ac @@ -395,6 +395,8 @@ fi AM_CONDITIONAL(HAVE_FREEDRENO_KGSL, [test "x$FREEDRENO_KGSL" = xyes]) if test "x$FREEDRENO_KGSL" = xyes; then AC_DEFINE(HAVE_FREEDRENO_KGSL, 1, [Have freedreno support for KGSL kernel interface]) +else + AC_DEFINE(HAVE_FREEDRENO_KGSL, 0) fi AM_CONDITIONAL(HAVE_RADEON, [test "x$RADEON" = xyes]) diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index 7f8ea59c..df35c36a 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -326,7 +326,7 @@ void fd_bo_cpu_fini(struct fd_bo *bo) bo->funcs->cpu_fini(bo); } -#ifndef HAVE_FREEDRENO_KGSL +#if !HAVE_FREEDRENO_KGSL struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size) { return NULL; diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c index 12b95fd0..a0334bf4 100644 --- a/freedreno/freedreno_device.c +++ b/freedreno/freedreno_device.c @@ -65,7 +65,7 @@ struct fd_device * fd_device_new(int fd) dev = msm_device_new(fd); dev->version = version->version_minor; -#ifdef HAVE_FREEDRENO_KGSL +#if HAVE_FREEDRENO_KGSL } else if (!strcmp(version->name, "kgsl")) { DEBUG_MSG("kgsl DRM device"); dev = kgsl_device_new(fd); diff --git a/meson.build b/meson.build index 7298f741..c7245dda 100644 --- a/meson.build +++ b/meson.build @@ -255,14 +255,12 @@ foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_nouveau, 'NOUVEAU'], [with_exynos, 'EXYNOS'], [with_vc4, 'VC4'], + [with_freedreno_kgsl, 'FREEDRENO_KGSL'], [with_radeon, 'RADEON']] config.set10('HAVE_@0@'.format(t[1]), t[0]) endforeach -if with_freedreno_kgsl - if not with_freedreno - error('cannot enable freedreno-kgsl without freedreno support') - endif - config.set10('HAVE_FREEDRENO_KGSL', true) +if with_freedreno_kgsl and not with_freedreno + error('cannot enable freedreno-kgsl without freedreno support') endif if dep_cairo.found() config.set10('HAVE_CAIRO', true) -- cgit v1.2.3-54-g00ecf From d2b0a4ec70d93040159af0cbc15717d35812ffc5 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 15:15:29 +0000 Subject: always define HAVE_CAIRO Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 ++ meson.build | 4 +--- tests/util/pattern.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configure.ac b/configure.ac index e19fdc99..993c2a27 100644 --- a/configure.ac +++ b/configure.ac @@ -466,6 +466,8 @@ if test "x$CAIRO" = xyes; then AC_MSG_ERROR([Cairo support required but not present]) fi AC_DEFINE(HAVE_CAIRO, 1, [Have Cairo support]) +else + AC_DEFINE(HAVE_CAIRO, 0) fi AC_MSG_RESULT([$CAIRO]) AM_CONDITIONAL(HAVE_CAIRO, [test "x$CAIRO" = xyes]) diff --git a/meson.build b/meson.build index c7245dda..15a1d405 100644 --- a/meson.build +++ b/meson.build @@ -256,15 +256,13 @@ foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_exynos, 'EXYNOS'], [with_vc4, 'VC4'], [with_freedreno_kgsl, 'FREEDRENO_KGSL'], + [dep_cairo.found(), 'CAIRO'], [with_radeon, 'RADEON']] config.set10('HAVE_@0@'.format(t[1]), t[0]) endforeach if with_freedreno_kgsl and not with_freedreno error('cannot enable freedreno-kgsl without freedreno support') endif -if dep_cairo.found() - config.set10('HAVE_CAIRO', true) -endif if dep_valgrind.found() config.set10('HAVE_VALGRIND', true) endif diff --git a/tests/util/pattern.c b/tests/util/pattern.c index 2366b006..75a458d4 100644 --- a/tests/util/pattern.c +++ b/tests/util/pattern.c @@ -34,7 +34,7 @@ #include -#ifdef HAVE_CAIRO +#if HAVE_CAIRO #include #include #endif @@ -546,7 +546,7 @@ static void fill_smpte(const struct util_format_info *info, void *planes[3], static void make_pwetty(void *data, unsigned int width, unsigned int height, unsigned int stride, uint32_t format) { -#ifdef HAVE_CAIRO +#if HAVE_CAIRO cairo_surface_t *surface; cairo_t *cr; cairo_format_t cairo_format; -- cgit v1.2.3-54-g00ecf From 1d7bbf852094481a8f514ed786b7a7a8af67e5fe Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 15:08:39 +0000 Subject: always define HAVE_VALGRIND Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 ++ freedreno/freedreno_priv.h | 2 +- intel/intel_bufmgr_gem.c | 4 ++-- meson.build | 5 +---- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/configure.ac b/configure.ac index 993c2a27..a0246fe5 100644 --- a/configure.ac +++ b/configure.ac @@ -509,6 +509,8 @@ if test "x$VALGRIND" = "xyes"; then AC_MSG_ERROR([Valgrind support required but not present]) fi AC_DEFINE([HAVE_VALGRIND], 1, [Use valgrind intrinsics to suppress false warnings]) +else + AC_DEFINE([HAVE_VALGRIND], 0) fi AC_MSG_RESULT([$VALGRIND]) diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index 199ccb94..81ad6092 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -200,7 +200,7 @@ offset_bytes(void *end, void *start) return ((char *)end) - ((char *)start); } -#ifdef HAVE_VALGRIND +#if HAVE_VALGRIND # include /* diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 71f140f5..386da30e 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -66,7 +66,7 @@ #include "i915_drm.h" #include "uthash.h" -#ifdef HAVE_VALGRIND +#if HAVE_VALGRIND #include #include #define VG(x) x @@ -1629,7 +1629,7 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; -#ifdef HAVE_VALGRIND +#if HAVE_VALGRIND drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; #endif int ret; diff --git a/meson.build b/meson.build index 15a1d405..76a081a9 100644 --- a/meson.build +++ b/meson.build @@ -257,16 +257,13 @@ foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], [with_vc4, 'VC4'], [with_freedreno_kgsl, 'FREEDRENO_KGSL'], [dep_cairo.found(), 'CAIRO'], + [dep_valgrind.found(), 'VALGRIND'], [with_radeon, 'RADEON']] config.set10('HAVE_@0@'.format(t[1]), t[0]) endforeach if with_freedreno_kgsl and not with_freedreno error('cannot enable freedreno-kgsl without freedreno support') endif -if dep_valgrind.found() - config.set10('HAVE_VALGRIND', true) -endif - config.set10('_GNU_SOURCE', true) config_file = configure_file( configuration : config, -- cgit v1.2.3-54-g00ecf From 5457e0082df2516ee20f2f08370eb063675e4de3 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 16:23:01 +0000 Subject: meson: sort HAVE_* defines Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/meson.build b/meson.build index 76a081a9..65366eee 100644 --- a/meson.build +++ b/meson.build @@ -251,14 +251,17 @@ if cc.compiles('''int foo_hidden(void) __attribute__((visibility(("hidden"))));' config.set10('HAVE_VISIBILITY', true) endif -foreach t : [[with_intel, 'INTEL'], [with_vmwgfx, 'VMWGFX'], - [with_nouveau, 'NOUVEAU'], +foreach t : [ [with_exynos, 'EXYNOS'], - [with_vc4, 'VC4'], [with_freedreno_kgsl, 'FREEDRENO_KGSL'], + [with_intel, 'INTEL'], + [with_nouveau, 'NOUVEAU'], + [with_radeon, 'RADEON'], + [with_vc4, 'VC4'], + [with_vmwgfx, 'VMWGFX'], [dep_cairo.found(), 'CAIRO'], [dep_valgrind.found(), 'VALGRIND'], - [with_radeon, 'RADEON']] + ] config.set10('HAVE_@0@'.format(t[1]), t[0]) endforeach if with_freedreno_kgsl and not with_freedreno -- cgit v1.2.3-54-g00ecf From 2d50a404f6b00117b477766ccd078973933aedc3 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 15:10:46 +0000 Subject: xf86atomic: fix -Wundef warning Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- xf86atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xf86atomic.h b/xf86atomic.h index 922b37da..70e91866 100644 --- a/xf86atomic.h +++ b/xf86atomic.h @@ -101,7 +101,7 @@ typedef struct { LIBDRM_ATOMIC_TYPE atomic; } atomic_t; #endif -#if ! HAS_ATOMIC_OPS +#if !defined(HAS_ATOMIC_OPS) #error libdrm requires atomic operations, please define them for your CPU/compiler. #endif -- cgit v1.2.3-54-g00ecf From 8177d73bdb12eedfa85da35fad6882afb2b01288 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 11:18:30 +0000 Subject: meson: cleanup whitespace Signed-off-by: Eric Engestrom Reviewed-by: Dylan Baker Reviewed-by: Emil Velikov --- meson.build | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/meson.build b/meson.build index 65366eee..e05db1cd 100644 --- a/meson.build +++ b/meson.build @@ -207,8 +207,8 @@ foreach a : ['-Wall', '-Wextra', '-Wsign-compare', '-Werror-implicit-function-declaration', '-Wpointer-arith', '-Wwrite-strings', '-Wstrict-prototypes', '-Wmissing-prototypes', '-Wmissing-declarations', '-Wnested-externs', '-Wpacked', - '-Wswitch-enum', '-Wmissing-format-attribute', - '-Wstrict-aliasing=2', '-Winit-self', '-Winline', '-Wshadow', + '-Wswitch-enum', '-Wmissing-format-attribute', + '-Wstrict-aliasing=2', '-Winit-self', '-Winline', '-Wshadow', '-Wdeclaration-after-statement', '-Wold-style-definition'] if cc.has_argument(a) warn_c_args += a @@ -216,7 +216,7 @@ foreach a : ['-Wall', '-Wextra', '-Wsign-compare', endforeach # GCC will never error for -Wno-*, so check for -W* then add -Wno-* to the list # of options -foreach a : ['unused-parameter', 'attributes', 'long-long', +foreach a : ['unused-parameter', 'attributes', 'long-long', 'missing-field-initializers'] if cc.has_argument('-W@0@'.format(a)) warn_c_args += '-Wno-@0@'.format(a) @@ -320,7 +320,7 @@ pkg.generate( version : meson.project_version(), description : 'Userspace interface to kernel DRM services', ) - + if with_libkms subdir('libkms') endif -- cgit v1.2.3-54-g00ecf From 75758d2ccf608de5774863d3bb7ae36c50197355 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 11:17:33 +0000 Subject: meson,configure: add warning when using undefined preprocessor tokens Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 +- meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index a0246fe5..5396c841 100644 --- a/configure.ac +++ b/configure.ac @@ -197,7 +197,7 @@ dnl skipped and all flags rechecked. So there's no need to do anything dnl else. If for any reason you need to force a recheck, just change dnl MAYBE_WARN in an ignorable way (like adding whitespace) -MAYBE_WARN="-Wall -Wextra \ +MAYBE_WARN="-Wall -Wextra -Wundef \ -Wsign-compare -Werror-implicit-function-declaration \ -Wpointer-arith -Wwrite-strings -Wstrict-prototypes \ -Wmissing-prototypes -Wmissing-declarations -Wnested-externs \ diff --git a/meson.build b/meson.build index e05db1cd..e249ea0f 100644 --- a/meson.build +++ b/meson.build @@ -203,7 +203,7 @@ if cc.has_function('open_memstream') endif warn_c_args = [] -foreach a : ['-Wall', '-Wextra', '-Wsign-compare', +foreach a : ['-Wall', '-Wextra', '-Wsign-compare', '-Wundef', '-Werror-implicit-function-declaration', '-Wpointer-arith', '-Wwrite-strings', '-Wstrict-prototypes', '-Wmissing-prototypes', '-Wmissing-declarations', '-Wnested-externs', '-Wpacked', -- cgit v1.2.3-54-g00ecf From 7797751cf7bbbcffdb1003f3a38479388dc4d7f9 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 5 Jan 2018 14:57:59 +0000 Subject: xf86drmHash: remove always-false #if guards Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- xf86drmHash.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/xf86drmHash.c b/xf86drmHash.c index f287e61f..b2fa414e 100644 --- a/xf86drmHash.c +++ b/xf86drmHash.c @@ -98,9 +98,6 @@ static unsigned long HashHash(unsigned long key) } hash %= HASH_SIZE; -#if DEBUG - printf( "Hash(%lu) = %lu\n", key, hash); -#endif return hash; } @@ -201,9 +198,6 @@ int drmHashInsert(void *t, unsigned long key, void *value) bucket->value = value; bucket->next = table->buckets[hash]; table->buckets[hash] = bucket; -#if DEBUG - printf("Inserted %lu at %lu/%p\n", key, hash, bucket); -#endif return 0; /* Added to table */ } -- cgit v1.2.3-54-g00ecf From 0db36bdec8a1b2caac0046c22eb477ba19c2b43c Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 5 Jan 2018 15:25:31 +0000 Subject: configure: always define HAVE_LIBDRM_ATOMIC_PRIMITIVES and HAVE_LIB_ATOMIC_OPS Fixes #if undefined warnings Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configure.ac b/configure.ac index 5396c841..f7620268 100644 --- a/configure.ac +++ b/configure.ac @@ -259,9 +259,13 @@ AC_CACHE_CHECK([for native atomic primitives], drm_cv_atomic_primitives, [ if test "x$drm_cv_atomic_primitives" = xIntel; then AC_DEFINE(HAVE_LIBDRM_ATOMIC_PRIMITIVES, 1, [Enable if your compiler supports the Intel __sync_* atomic primitives]) +else + AC_DEFINE(HAVE_LIBDRM_ATOMIC_PRIMITIVES, 0) fi if test "x$drm_cv_atomic_primitives" = "xlibatomic-ops"; then AC_DEFINE(HAVE_LIB_ATOMIC_OPS, 1, [Enable if you have libatomic-ops-dev installed]) +else + AC_DEFINE(HAVE_LIB_ATOMIC_OPS, 0) fi dnl Print out the approapriate message considering the value set be the -- cgit v1.2.3-54-g00ecf From 440e6ad0702a912dc61e19aba179e13903767a9a Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 5 Jan 2018 15:27:17 +0000 Subject: exynos/tests: use #ifdef for never-defined token Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- tests/exynos/exynos_fimg2d_test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index 14d304d3..dcb2e35a 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -536,7 +536,7 @@ fail: return ret; } -#if EXYNOS_G2D_USERPTR_TEST +#ifdef EXYNOS_G2D_USERPTR_TEST static int g2d_blend_test(struct exynos_device *dev, struct exynos_bo *src, struct exynos_bo *dst, @@ -880,7 +880,7 @@ int main(int argc, char **argv) * * Disable the test for now, until the kernel code has been sanitized. */ -#if EXYNOS_G2D_USERPTR_TEST +#ifdef EXYNOS_G2D_USERPTR_TEST ret = g2d_blend_test(dev, src, bo, G2D_IMGBUF_USERPTR); if (ret < 0) fprintf(stderr, "failed to test blend operation.\n"); -- cgit v1.2.3-54-g00ecf From ba17673eed0383cc41ed49e8c9841b6b819fdfd3 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 11:18:03 +0000 Subject: meson,configure: turn undefined preprocessor tokens warnings into errors Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 +- meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index f7620268..321ab2c0 100644 --- a/configure.ac +++ b/configure.ac @@ -197,7 +197,7 @@ dnl skipped and all flags rechecked. So there's no need to do anything dnl else. If for any reason you need to force a recheck, just change dnl MAYBE_WARN in an ignorable way (like adding whitespace) -MAYBE_WARN="-Wall -Wextra -Wundef \ +MAYBE_WARN="-Wall -Wextra -Werror=undef \ -Wsign-compare -Werror-implicit-function-declaration \ -Wpointer-arith -Wwrite-strings -Wstrict-prototypes \ -Wmissing-prototypes -Wmissing-declarations -Wnested-externs \ diff --git a/meson.build b/meson.build index e249ea0f..1342a5b3 100644 --- a/meson.build +++ b/meson.build @@ -203,7 +203,7 @@ if cc.has_function('open_memstream') endif warn_c_args = [] -foreach a : ['-Wall', '-Wextra', '-Wsign-compare', '-Wundef', +foreach a : ['-Wall', '-Wextra', '-Wsign-compare', '-Werror=undef', '-Werror-implicit-function-declaration', '-Wpointer-arith', '-Wwrite-strings', '-Wstrict-prototypes', '-Wmissing-prototypes', '-Wmissing-declarations', '-Wnested-externs', '-Wpacked', -- cgit v1.2.3-54-g00ecf From 10e85a8b7f28e80f5184919b2448ade18c19ca21 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Mon, 29 Jan 2018 14:51:31 +0000 Subject: tests/amdgpu: add missing config.h include Otherwise we'll end up without the macros set during configure stage. And effectively error out in sanity tests such as the mmap static assert. To reproduce, do a multilib build - 32bit build on 64bit machine. Cc: Fabio Pedretti Cc: Andrey Grodzovsky Fixes: 33dcc29f7cc ("amdgpu: Add VMID reservation per GPU context test.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104819 Signed-off-by: Emil Velikov Reviewed-by: Eric Engestrom --- tests/amdgpu/vm_tests.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c index 7b6dc5d6..502a9405 100644 --- a/tests/amdgpu/vm_tests.c +++ b/tests/amdgpu/vm_tests.c @@ -21,6 +21,10 @@ * */ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + #include "CUnit/Basic.h" #include "amdgpu_test.h" -- cgit v1.2.3-54-g00ecf From 9e34ad590e0e1003a597b8cc790a3f36830ba993 Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Thu, 25 Jan 2018 15:44:37 -0800 Subject: meson: fix libdrm_nouveau pkgconfig include directories Signed-off-by: Dylan Baker Reviewed-by: Eric Engestrom --- nouveau/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nouveau/meson.build b/nouveau/meson.build index bfecf84b..f031cd63 100644 --- a/nouveau/meson.build +++ b/nouveau/meson.build @@ -45,7 +45,7 @@ install_headers( pkg.generate( name : 'libdrm_nouveau', libraries : libdrm_nouveau, - subdirs : ['.', 'nouveau'], + subdirs : ['.', 'libdrm', 'libdrm/nouveau'], version : meson.project_version(), requires_private : 'libdrm', description : 'Userspace interface to nouveau kernel DRM services', -- cgit v1.2.3-54-g00ecf From b1e63d9ee622f3f08127bab43bf6817101b870a8 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Tue, 6 Feb 2018 11:21:35 +0100 Subject: drm: Fix 32-bit drmSyncobjWait. Otherwise we get an EFAULT, at least on a 64-bit kernel. Fixes: 2048a9e7 "drm: add drmSyncobjWait wrapper" Reviewed-by: Christian König Reviewed-by: Dave Airlie --- xf86drm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xf86drm.c b/xf86drm.c index 74b4e230..1e87610b 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -4271,7 +4271,7 @@ int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, int ret; memclear(args); - args.handles = (intptr_t)handles; + args.handles = (uintptr_t)handles; args.timeout_nsec = timeout_nsec; args.count_handles = num_handles; args.flags = flags; -- cgit v1.2.3-54-g00ecf From bde3b9b689407eadd1cb0d9348a0fd7906c880e2 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Wed, 7 Feb 2018 11:22:32 +0800 Subject: fix return value for syncobj wait otherwise -ETIME is missed. Signed-off-by: Chunming Zhou Reviewed-by: Christian König --- xf86drm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xf86drm.c b/xf86drm.c index 1e87610b..344326db 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -4278,7 +4278,7 @@ int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args); if (ret < 0) - return ret; + return -errno; if (first_signaled) *first_signaled = args.first_signaled; -- cgit v1.2.3-54-g00ecf From d07be74a4afe9d22f987aca7e8e84cccaa210248 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Thu, 8 Feb 2018 14:35:26 +0800 Subject: amdgpu: fix inefficient vamgr algorithm issue: UMD allocates top 4GB, but don't do anything, just reserve top 4GB space, but the performance of VP13 drops from 162fps to 99fps. root cause: our va hole list of vamgr is too long by time going. fix: reusing old hole as much as possible can make the list shortest. result: performance recovers as non-list path, next patch will remove non-list code path. Signed-off-by: Chunming Zhou Reviewed-by: Christian König --- amdgpu/amdgpu_vamgr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index ab425ef7..a2852b55 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -80,9 +80,7 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, return AMDGPU_INVALID_VA_ADDRESS; pthread_mutex_lock(&mgr->bo_va_mutex); - /* TODO: using more appropriate way to track the holes */ - /* first look for a hole */ - LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { + LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) { if (base_required) { if (hole->offset > base_required || (hole->offset + hole->size) < (base_required + size)) -- cgit v1.2.3-54-g00ecf From 41b94a3fb6e87d057fad78568d920d29489e5060 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Thu, 8 Feb 2018 14:52:11 +0800 Subject: amdgpu: clean up non list code path for vamgr Signed-off-by: Chunming Zhou Reviewed-by: Christian König --- amdgpu/amdgpu_internal.h | 2 - amdgpu/amdgpu_vamgr.c | 121 +++++++++++++++++------------------------------ 2 files changed, 43 insertions(+), 80 deletions(-) diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 3e044f11..75276a99 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -53,8 +53,6 @@ struct amdgpu_bo_va_hole { }; struct amdgpu_bo_va_mgr { - /* the start virtual address */ - uint64_t va_offset; uint64_t va_max; struct list_head va_holes; pthread_mutex_t bo_va_mutex; diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index a2852b55..2311e5eb 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -48,12 +48,19 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, uint64_t max, uint64_t alignment) { - mgr->va_offset = start; + struct amdgpu_bo_va_hole *n; + mgr->va_max = max; mgr->va_alignment = alignment; list_inithead(&mgr->va_holes); pthread_mutex_init(&mgr->bo_va_mutex, NULL); + pthread_mutex_lock(&mgr->bo_va_mutex); + n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + n->size = mgr->va_max; + n->offset = start; + list_add(&n->list, &mgr->va_holes); + pthread_mutex_unlock(&mgr->bo_va_mutex); } drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) @@ -122,41 +129,14 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, } } - if (base_required) { - if (base_required < mgr->va_offset) { - pthread_mutex_unlock(&mgr->bo_va_mutex); - return AMDGPU_INVALID_VA_ADDRESS; - } - offset = mgr->va_offset; - waste = base_required - mgr->va_offset; - } else { - offset = mgr->va_offset; - waste = offset % alignment; - waste = waste ? alignment - waste : 0; - } - - if (offset + waste + size > mgr->va_max) { - pthread_mutex_unlock(&mgr->bo_va_mutex); - return AMDGPU_INVALID_VA_ADDRESS; - } - - if (waste) { - n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - n->size = waste; - n->offset = offset; - list_add(&n->list, &mgr->va_holes); - } - - offset += waste; - mgr->va_offset += size + waste; pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; + return AMDGPU_INVALID_VA_ADDRESS; } static drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) { - struct amdgpu_bo_va_hole *hole; + struct amdgpu_bo_va_hole *hole, *next; if (va == AMDGPU_INVALID_VA_ADDRESS) return; @@ -164,61 +144,46 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) size = ALIGN(size, mgr->va_alignment); pthread_mutex_lock(&mgr->bo_va_mutex); - if ((va + size) == mgr->va_offset) { - mgr->va_offset = va; - /* Delete uppermost hole if it reaches the new top */ - if (!LIST_IS_EMPTY(&mgr->va_holes)) { - hole = container_of(mgr->va_holes.next, hole, list); - if ((hole->offset + hole->size) == va) { - mgr->va_offset = hole->offset; + hole = container_of(&mgr->va_holes, hole, list); + LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) { + if (next->offset < va) + break; + hole = next; + } + + if (&hole->list != &mgr->va_holes) { + /* Grow upper hole if it's adjacent */ + if (hole->offset == (va + size)) { + hole->offset = va; + hole->size += size; + /* Merge lower hole if it's adjacent */ + if (next != hole && + &next->list != &mgr->va_holes && + (next->offset + next->size) == va) { + next->size += hole->size; list_del(&hole->list); free(hole); } } - } else { - struct amdgpu_bo_va_hole *next; - - hole = container_of(&mgr->va_holes, hole, list); - LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) { - if (next->offset < va) - break; - hole = next; - } - - if (&hole->list != &mgr->va_holes) { - /* Grow upper hole if it's adjacent */ - if (hole->offset == (va + size)) { - hole->offset = va; - hole->size += size; - /* Merge lower hole if it's adjacent */ - if (next != hole && - &next->list != &mgr->va_holes && - (next->offset + next->size) == va) { - next->size += hole->size; - list_del(&hole->list); - free(hole); - } - goto out; - } - } + } - /* Grow lower hole if it's adjacent */ - if (next != hole && &next->list != &mgr->va_holes && - (next->offset + next->size) == va) { - next->size += size; - goto out; - } + /* Grow lower hole if it's adjacent */ + if (next != hole && &next->list != &mgr->va_holes && + (next->offset + next->size) == va) { + next->size += size; + goto out; + } - /* FIXME on allocation failure we just lose virtual address space - * maybe print a warning - */ - next = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - if (next) { - next->size = size; - next->offset = va; - list_add(&next->list, &hole->list); - } + /* FIXME on allocation failure we just lose virtual address space + * maybe print a warning + */ + next = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + if (next) { + next->size = size; + next->offset = va; + list_add(&next->list, &hole->list); } + out: pthread_mutex_unlock(&mgr->bo_va_mutex); } -- cgit v1.2.3-54-g00ecf From 09642c073e8af71127cf98b48fe1b2a376c606cf Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Thu, 8 Feb 2018 15:03:01 +0800 Subject: tests/amdgpu: add bo eviction test for(( i=1; i < 100; i++)) do echo "Hello, Welcome $i times " sudo ./amdgpu_test -s 1 -t 5 done with above stricpt, run in two terminals, will reproduce Felix's swap leeking issue. Signed-off-by: Chunming Zhou Acked-by: Christian König --- tests/amdgpu/amdgpu_test.h | 23 +++++++ tests/amdgpu/basic_tests.c | 160 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 182 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 1db803c6..7397dea0 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -251,6 +251,29 @@ static inline int gpu_mem_free(amdgpu_bo_handle bo, return 0; } +static inline int +amdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size, + unsigned alignment, unsigned heap, uint64_t flags, + amdgpu_bo_handle *bo) +{ + struct amdgpu_bo_alloc_request request = {}; + amdgpu_bo_handle buf_handle; + int r; + + request.alloc_size = size; + request.phys_alignment = alignment; + request.preferred_heap = heap; + request.flags = flags; + + r = amdgpu_bo_alloc(dev, &request, &buf_handle); + if (r) + return r; + + *bo = buf_handle; + + return 0; +} + static inline int amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size, unsigned alignment, unsigned heap, uint64_t flags, diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 354b0157..0ea010a8 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -51,14 +51,22 @@ static void amdgpu_command_submission_sdma(void); static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); static void amdgpu_sync_dependency_test(void); +static void amdgpu_bo_eviction_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type); - +static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, + unsigned ip_type, + int instance, int pm4_dw, uint32_t *pm4_src, + int res_cnt, amdgpu_bo_handle *resources, + struct amdgpu_cs_ib_info *ib_info, + struct amdgpu_cs_request *ibs_request); + CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, { "Userptr Test", amdgpu_userptr_test }, + { "bo eviction Test", amdgpu_bo_eviction_test }, { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, { "Command submission Test (Compute)", amdgpu_command_submission_compute }, { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, @@ -516,6 +524,156 @@ static void amdgpu_command_submission_gfx_cp_copy_data(void) amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX); } +static void amdgpu_bo_eviction_test(void) +{ + const int sdma_write_length = 1024; + const int pm4_dw = 256; + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo1, bo2, vram_max[2], gtt_max[2]; + amdgpu_bo_handle *resources; + uint32_t *pm4; + struct amdgpu_cs_ib_info *ib_info; + struct amdgpu_cs_request *ibs_request; + uint64_t bo1_mc, bo2_mc; + volatile unsigned char *bo1_cpu, *bo2_cpu; + int i, j, r, loop1, loop2; + uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; + amdgpu_va_handle bo1_va_handle, bo2_va_handle; + struct amdgpu_heap_info vram_info, gtt_info; + + pm4 = calloc(pm4_dw, sizeof(*pm4)); + CU_ASSERT_NOT_EQUAL(pm4, NULL); + + ib_info = calloc(1, sizeof(*ib_info)); + CU_ASSERT_NOT_EQUAL(ib_info, NULL); + + ibs_request = calloc(1, sizeof(*ibs_request)); + CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + /* prepare resource */ + resources = calloc(4, sizeof(amdgpu_bo_handle)); + CU_ASSERT_NOT_EQUAL(resources, NULL); + + r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, + 0, &vram_info); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, + 0, >t_info); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[0]); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[1]); + CU_ASSERT_EQUAL(r, 0); + + + + loop1 = loop2 = 0; + /* run 9 circle to test all mapping combination */ + while(loop1 < 2) { + while(loop2 < 2) { + /* allocate UC bo1for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop1], &bo1, + (void**)&bo1_cpu, &bo1_mc, + &bo1_va_handle); + CU_ASSERT_EQUAL(r, 0); + + /* set bo1 */ + memset((void*)bo1_cpu, 0xaa, sdma_write_length); + + /* allocate UC bo2 for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop2], &bo2, + (void**)&bo2_cpu, &bo2_mc, + &bo2_va_handle); + CU_ASSERT_EQUAL(r, 0); + + /* clear bo2 */ + memset((void*)bo2_cpu, 0, sdma_write_length); + + resources[0] = bo1; + resources[1] = bo2; + resources[2] = vram_max[loop2]; + resources[3] = gtt_max[loop2]; + + /* fulfill PM4: test DMA copy linear */ + i = j = 0; + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, + sdma_write_length); + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + } else { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; + pm4[i++] = 0; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + } + + amdgpu_test_exec_cs_helper(context_handle, + AMDGPU_HW_IP_DMA, 0, + i, pm4, + 4, resources, + ib_info, ibs_request); + + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); + } + r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + loop2++; + } + loop2 = 0; + loop1++; + } + amdgpu_bo_free(vram_max[0]); + amdgpu_bo_free(vram_max[1]); + amdgpu_bo_free(gtt_max[0]); + amdgpu_bo_free(gtt_max[1]); + /* clean resources */ + free(resources); + free(ibs_request); + free(ib_info); + free(pm4); + + /* end of test */ + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} + + static void amdgpu_command_submission_gfx(void) { /* write data using the CP */ -- cgit v1.2.3-54-g00ecf From fa35b51f6366bd44185177f0a66e02191905d774 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 8 Feb 2018 09:50:53 +0100 Subject: Revert "amdgpu: clean up non list code path for vamgr" This reverts commit 41b94a3fb6e87d057fad78568d920d29489e5060. It caused crashes with radeonsi in at least glxgears and Xorg. --- amdgpu/amdgpu_internal.h | 2 + amdgpu/amdgpu_vamgr.c | 121 ++++++++++++++++++++++++++++++----------------- 2 files changed, 80 insertions(+), 43 deletions(-) diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 75276a99..3e044f11 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -53,6 +53,8 @@ struct amdgpu_bo_va_hole { }; struct amdgpu_bo_va_mgr { + /* the start virtual address */ + uint64_t va_offset; uint64_t va_max; struct list_head va_holes; pthread_mutex_t bo_va_mutex; diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 2311e5eb..a2852b55 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -48,19 +48,12 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, uint64_t max, uint64_t alignment) { - struct amdgpu_bo_va_hole *n; - + mgr->va_offset = start; mgr->va_max = max; mgr->va_alignment = alignment; list_inithead(&mgr->va_holes); pthread_mutex_init(&mgr->bo_va_mutex, NULL); - pthread_mutex_lock(&mgr->bo_va_mutex); - n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - n->size = mgr->va_max; - n->offset = start; - list_add(&n->list, &mgr->va_holes); - pthread_mutex_unlock(&mgr->bo_va_mutex); } drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) @@ -129,14 +122,41 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, } } + if (base_required) { + if (base_required < mgr->va_offset) { + pthread_mutex_unlock(&mgr->bo_va_mutex); + return AMDGPU_INVALID_VA_ADDRESS; + } + offset = mgr->va_offset; + waste = base_required - mgr->va_offset; + } else { + offset = mgr->va_offset; + waste = offset % alignment; + waste = waste ? alignment - waste : 0; + } + + if (offset + waste + size > mgr->va_max) { + pthread_mutex_unlock(&mgr->bo_va_mutex); + return AMDGPU_INVALID_VA_ADDRESS; + } + + if (waste) { + n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + n->size = waste; + n->offset = offset; + list_add(&n->list, &mgr->va_holes); + } + + offset += waste; + mgr->va_offset += size + waste; pthread_mutex_unlock(&mgr->bo_va_mutex); - return AMDGPU_INVALID_VA_ADDRESS; + return offset; } static drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) { - struct amdgpu_bo_va_hole *hole, *next; + struct amdgpu_bo_va_hole *hole; if (va == AMDGPU_INVALID_VA_ADDRESS) return; @@ -144,46 +164,61 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) size = ALIGN(size, mgr->va_alignment); pthread_mutex_lock(&mgr->bo_va_mutex); - hole = container_of(&mgr->va_holes, hole, list); - LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) { - if (next->offset < va) - break; - hole = next; - } - - if (&hole->list != &mgr->va_holes) { - /* Grow upper hole if it's adjacent */ - if (hole->offset == (va + size)) { - hole->offset = va; - hole->size += size; - /* Merge lower hole if it's adjacent */ - if (next != hole && - &next->list != &mgr->va_holes && - (next->offset + next->size) == va) { - next->size += hole->size; + if ((va + size) == mgr->va_offset) { + mgr->va_offset = va; + /* Delete uppermost hole if it reaches the new top */ + if (!LIST_IS_EMPTY(&mgr->va_holes)) { + hole = container_of(mgr->va_holes.next, hole, list); + if ((hole->offset + hole->size) == va) { + mgr->va_offset = hole->offset; list_del(&hole->list); free(hole); } } - } + } else { + struct amdgpu_bo_va_hole *next; - /* Grow lower hole if it's adjacent */ - if (next != hole && &next->list != &mgr->va_holes && - (next->offset + next->size) == va) { - next->size += size; - goto out; - } + hole = container_of(&mgr->va_holes, hole, list); + LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) { + if (next->offset < va) + break; + hole = next; + } - /* FIXME on allocation failure we just lose virtual address space - * maybe print a warning - */ - next = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - if (next) { - next->size = size; - next->offset = va; - list_add(&next->list, &hole->list); - } + if (&hole->list != &mgr->va_holes) { + /* Grow upper hole if it's adjacent */ + if (hole->offset == (va + size)) { + hole->offset = va; + hole->size += size; + /* Merge lower hole if it's adjacent */ + if (next != hole && + &next->list != &mgr->va_holes && + (next->offset + next->size) == va) { + next->size += hole->size; + list_del(&hole->list); + free(hole); + } + goto out; + } + } + + /* Grow lower hole if it's adjacent */ + if (next != hole && &next->list != &mgr->va_holes && + (next->offset + next->size) == va) { + next->size += size; + goto out; + } + /* FIXME on allocation failure we just lose virtual address space + * maybe print a warning + */ + next = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + if (next) { + next->size = size; + next->offset = va; + list_add(&next->list, &hole->list); + } + } out: pthread_mutex_unlock(&mgr->bo_va_mutex); } -- cgit v1.2.3-54-g00ecf From 69f9faeee6c10d07a9f9f35e175a75f6e7eeecd1 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Thu, 8 Feb 2018 14:52:11 +0800 Subject: amdgpu: clean up non list code path for vamgr v2 v2: Add missing "goto out" Signed-off-by: Chunming Zhou Reviewed-by: Christian König Tested-by: Michel Dänzer --- amdgpu/amdgpu_internal.h | 2 - amdgpu/amdgpu_vamgr.c | 122 +++++++++++++++++------------------------------ 2 files changed, 44 insertions(+), 80 deletions(-) diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 3e044f11..75276a99 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -53,8 +53,6 @@ struct amdgpu_bo_va_hole { }; struct amdgpu_bo_va_mgr { - /* the start virtual address */ - uint64_t va_offset; uint64_t va_max; struct list_head va_holes; pthread_mutex_t bo_va_mutex; diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index a2852b55..722067f3 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -48,12 +48,19 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, uint64_t max, uint64_t alignment) { - mgr->va_offset = start; + struct amdgpu_bo_va_hole *n; + mgr->va_max = max; mgr->va_alignment = alignment; list_inithead(&mgr->va_holes); pthread_mutex_init(&mgr->bo_va_mutex, NULL); + pthread_mutex_lock(&mgr->bo_va_mutex); + n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + n->size = mgr->va_max; + n->offset = start; + list_add(&n->list, &mgr->va_holes); + pthread_mutex_unlock(&mgr->bo_va_mutex); } drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) @@ -122,41 +129,14 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, } } - if (base_required) { - if (base_required < mgr->va_offset) { - pthread_mutex_unlock(&mgr->bo_va_mutex); - return AMDGPU_INVALID_VA_ADDRESS; - } - offset = mgr->va_offset; - waste = base_required - mgr->va_offset; - } else { - offset = mgr->va_offset; - waste = offset % alignment; - waste = waste ? alignment - waste : 0; - } - - if (offset + waste + size > mgr->va_max) { - pthread_mutex_unlock(&mgr->bo_va_mutex); - return AMDGPU_INVALID_VA_ADDRESS; - } - - if (waste) { - n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - n->size = waste; - n->offset = offset; - list_add(&n->list, &mgr->va_holes); - } - - offset += waste; - mgr->va_offset += size + waste; pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; + return AMDGPU_INVALID_VA_ADDRESS; } static drm_private void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) { - struct amdgpu_bo_va_hole *hole; + struct amdgpu_bo_va_hole *hole, *next; if (va == AMDGPU_INVALID_VA_ADDRESS) return; @@ -164,61 +144,47 @@ amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) size = ALIGN(size, mgr->va_alignment); pthread_mutex_lock(&mgr->bo_va_mutex); - if ((va + size) == mgr->va_offset) { - mgr->va_offset = va; - /* Delete uppermost hole if it reaches the new top */ - if (!LIST_IS_EMPTY(&mgr->va_holes)) { - hole = container_of(mgr->va_holes.next, hole, list); - if ((hole->offset + hole->size) == va) { - mgr->va_offset = hole->offset; + hole = container_of(&mgr->va_holes, hole, list); + LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) { + if (next->offset < va) + break; + hole = next; + } + + if (&hole->list != &mgr->va_holes) { + /* Grow upper hole if it's adjacent */ + if (hole->offset == (va + size)) { + hole->offset = va; + hole->size += size; + /* Merge lower hole if it's adjacent */ + if (next != hole && + &next->list != &mgr->va_holes && + (next->offset + next->size) == va) { + next->size += hole->size; list_del(&hole->list); free(hole); } - } - } else { - struct amdgpu_bo_va_hole *next; - - hole = container_of(&mgr->va_holes, hole, list); - LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) { - if (next->offset < va) - break; - hole = next; - } - - if (&hole->list != &mgr->va_holes) { - /* Grow upper hole if it's adjacent */ - if (hole->offset == (va + size)) { - hole->offset = va; - hole->size += size; - /* Merge lower hole if it's adjacent */ - if (next != hole && - &next->list != &mgr->va_holes && - (next->offset + next->size) == va) { - next->size += hole->size; - list_del(&hole->list); - free(hole); - } - goto out; - } - } - - /* Grow lower hole if it's adjacent */ - if (next != hole && &next->list != &mgr->va_holes && - (next->offset + next->size) == va) { - next->size += size; goto out; } + } - /* FIXME on allocation failure we just lose virtual address space - * maybe print a warning - */ - next = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - if (next) { - next->size = size; - next->offset = va; - list_add(&next->list, &hole->list); - } + /* Grow lower hole if it's adjacent */ + if (next != hole && &next->list != &mgr->va_holes && + (next->offset + next->size) == va) { + next->size += size; + goto out; } + + /* FIXME on allocation failure we just lose virtual address space + * maybe print a warning + */ + next = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + if (next) { + next->size = size; + next->offset = va; + list_add(&next->list, &hole->list); + } + out: pthread_mutex_unlock(&mgr->bo_va_mutex); } -- cgit v1.2.3-54-g00ecf From deb59781fcc1183e19cca67e2db35c2e21f40ed5 Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Wed, 7 Feb 2018 15:35:24 -0800 Subject: meson: include headers in root directory in ext_libdrm Which is used in wraps. Signed-off-by: Dylan Baker Reviewed-by: Eric Anholt --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 1342a5b3..4aaeb7e1 100644 --- a/meson.build +++ b/meson.build @@ -294,7 +294,7 @@ libdrm = shared_library( ext_libdrm = declare_dependency( link_with : libdrm, - include_directories : inc_drm, + include_directories : [inc_root, inc_drm], ) install_headers('libsync.h', 'xf86drm.h', 'xf86drmMode.h') -- cgit v1.2.3-54-g00ecf From ad5b702fec3f9cb54feeb403e7b31c10ebc0ca7c Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Fri, 2 Feb 2018 18:15:00 +0100 Subject: amdgpu: add amdgpu_query_sw_info for querying high bits of 32-bit address space Reviewed-by: Christian König --- amdgpu/amdgpu.h | 21 +++++++++++++++++++++ amdgpu/amdgpu_device.c | 14 ++++++++++++++ amdgpu/amdgpu_internal.h | 1 + 3 files changed, 36 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 2eb03bf1..928b2a68 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -94,6 +94,10 @@ enum amdgpu_gpu_va_range amdgpu_gpu_va_range_general = 0 }; +enum amdgpu_sw_info { + amdgpu_sw_info_address32_hi = 0, +}; + /*--------------------------------------------------------------------------*/ /* -------------------------- Datatypes ----------------------------------- */ /*--------------------------------------------------------------------------*/ @@ -1085,6 +1089,23 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev, int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, unsigned size, void *value); +/** + * Query hardware or driver information. + * + * The return size is query-specific and depends on the "info_id" parameter. + * No more than "size" bytes is returned. + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param info - \c [in] amdgpu_sw_info_* + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX error code + * +*/ +int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, + void *value); + /** * Query information about GDS * diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index f34e27a9..6ee25a9e 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -275,6 +275,7 @@ int amdgpu_device_initialize(int fd, max = MIN2(max, (start & ~0xffffffffULL) + 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); + dev->address32_hi = start >> 32; start = max; if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) @@ -312,3 +313,16 @@ const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) { return dev->marketing_name; } + +int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, + void *value) +{ + uint32_t *val32 = (uint32_t*)value; + + switch (info) { + case amdgpu_sw_info_address32_hi: + *val32 = dev->address32_hi; + return 0; + } + return -EINVAL; +} diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 75276a99..dd0c3a61 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -73,6 +73,7 @@ struct amdgpu_device { int flink_fd; unsigned major_version; unsigned minor_version; + uint32_t address32_hi; char *marketing_name; /** List of buffer handles. Protected by bo_table_mutex. */ -- cgit v1.2.3-54-g00ecf From 03f80b9f6a6f28e4942b1685a205a9484b2a0d63 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Mon, 12 Feb 2018 15:47:55 +0100 Subject: amdgpu: Add amdgpu_query_sw_info to amdgpu-symbol-check Fixes make check. Trivial. --- amdgpu/amdgpu-symbol-check | 1 + 1 file changed, 1 insertion(+) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 3f298d13..17de0c3b 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -40,6 +40,7 @@ amdgpu_cs_fence_to_handle amdgpu_cs_import_syncobj amdgpu_cs_query_fence_status amdgpu_cs_query_reset_state +amdgpu_query_sw_info amdgpu_cs_signal_semaphore amdgpu_cs_submit amdgpu_cs_submit_raw -- cgit v1.2.3-54-g00ecf From a4b6fd651f1b34f13eb3a3bc101a34adfa3b54a5 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Wed, 6 Dec 2017 19:28:13 +0100 Subject: android: Move gralloc handle struct to libdrm This struct is used in mesa and drm_hwcomposer. Versions of if have been implemented in several grallocs: drm_gralloc, gbm_gralloc, minigbm and intel-minigbm. Other than the 1:1 move of the struct a new generic name has been chosen and variables have had comments added to them. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- Android.mk | 8 +++- Makefile.sources | 3 ++ android/gralloc_handle.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+), 2 deletions(-) create mode 100644 android/gralloc_handle.h diff --git a/Android.mk b/Android.mk index 292be236..8611c5e3 100644 --- a/Android.mk +++ b/Android.mk @@ -28,7 +28,7 @@ LIBDRM_TOP := $(LOCAL_PATH) include $(CLEAR_VARS) -# Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES +# Import variables LIBDRM_{,H,INCLUDE_H,INCLUDE_ANDROID_H,INCLUDE_VMWGFX_H}_FILES include $(LOCAL_PATH)/Makefile.sources #static library for the device (recovery) @@ -38,7 +38,8 @@ LOCAL_MODULE := libdrm LOCAL_SRC_FILES := $(LIBDRM_FILES) LOCAL_EXPORT_C_INCLUDE_DIRS := \ $(LOCAL_PATH) \ - $(LOCAL_PATH)/include/drm + $(LOCAL_PATH)/include/drm \ + $(LOCAL_PATH)/android LOCAL_C_INCLUDES := \ $(LOCAL_PATH)/include/drm @@ -54,6 +55,9 @@ LOCAL_SRC_FILES := $(LIBDRM_FILES) LOCAL_EXPORT_C_INCLUDE_DIRS := \ $(LOCAL_PATH)/include/drm +LOCAL_SHARED_LIBRARIES := \ + libcutils + LOCAL_C_INCLUDES := \ $(LOCAL_PATH)/include/drm diff --git a/Makefile.sources b/Makefile.sources index 10aa1d0f..1f8372bc 100644 --- a/Makefile.sources +++ b/Makefile.sources @@ -37,5 +37,8 @@ LIBDRM_INCLUDE_H_FILES := \ include/drm/via_drm.h \ include/drm/virtgpu_drm.h +LIBDRM_INCLUDE_ANDROID_H_FILES := \ + android/gralloc_handle.h + LIBDRM_INCLUDE_VMWGFX_H_FILES := \ include/drm/vmwgfx_drm.h diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h new file mode 100644 index 00000000..45b9f2e9 --- /dev/null +++ b/android/gralloc_handle.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2011 Chia-I Wu + * Copyright (C) 2010-2011 LunarG Inc. + * Copyright (C) 2016 Linaro, Ltd., Rob Herring + * Copyright (C) 2018 Collabora, Robert Foss + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ANDROID_GRALLOC_HANDLE_H__ +#define __ANDROID_GRALLOC_HANDLE_H__ + +#include + +/* support users of drm_gralloc/gbm_gralloc */ +#define gralloc_gbm_handle_t gralloc_handle_t +#define gralloc_drm_handle_t gralloc_handle_t + +struct gralloc_handle_t { + native_handle_t base; + + /* dma-buf file descriptor + * Must be located first since, native_handle_t is allocated + * using native_handle_create(), which allocates space for + * sizeof(native_handle_t) + sizeof(int) * (numFds + numInts) + * numFds = GRALLOC_HANDLE_NUM_FDS + * numInts = GRALLOC_HANDLE_NUM_INTS + * Where numFds represents the number of FDs and + * numInts represents the space needed for the + * remainder of this struct. + * And the FDs are expected to be found first following + * native_handle_t. + */ + int prime_fd; + + int magic; /* differentiate between allocator impls */ + + int width; /* width of buffer in pixels */ + int height; /* height of buffer in pixels */ + int format; /* pixel format (Android) */ + int usage; /* android libhardware usage flags */ + + int name; /* the name of the bo */ + int stride; /* the stride in bytes */ + uint64_t modifier; /* buffer modifiers */ + + int data_owner; /* owner of data (for validation) */ + union { + void *data; /* pointer to struct gralloc_gbm_bo_t */ + uint64_t reserved; + } __attribute__((aligned(8))); +}; + +#define GRALLOC_HANDLE_MAGIC 0x60585350 +#define GRALLOC_HANDLE_NUM_FDS 1 +#define GRALLOC_HANDLE_NUM_INTS ( \ + ((sizeof(struct alloc_handle_t) - sizeof(native_handle_t))/sizeof(int)) \ + - GRALLOC_HANDLE_NUM_FDS) + +/** + * Create a buffer handle. + */ +static struct gralloc_handle_t gralloc_handle_create(int width, int height, + int format, int usage) +{ + struct gralloc_handle_t handle = { .magic = GRALLOC_HANDLE_MAGIC }; + + native_handle_t *nhandle = native_handle_create(GRALLOC_HANDLE_NUM_FDS, + GRALLOC_HANDLE_NUM_INTS); + handle.base = *nhandle; + native_handle_delete(nhandle); + + handle.width = width; + handle.height = height; + handle.format = format; + handle.usage = usage; + handle.prime_fd = -1; + + handle->data_owner = getpid(); + handle->data = bo; + + return handle; +} + +#endif -- cgit v1.2.3-54-g00ecf From 76cd0af39960d0c36e7aacd4fe8d6a08f4af8ecc Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 16 Jan 2018 14:36:13 +0100 Subject: android: Add version variable to gralloc_handle_t The version variable will be used for versioning of this struct and the corresponding accessor functions. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- android/gralloc_handle.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index 45b9f2e9..7cbc8ee7 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -27,6 +27,7 @@ #define __ANDROID_GRALLOC_HANDLE_H__ #include +#include /* support users of drm_gralloc/gbm_gralloc */ #define gralloc_gbm_handle_t gralloc_handle_t @@ -49,7 +50,9 @@ struct gralloc_handle_t { */ int prime_fd; + /* api variables */ int magic; /* differentiate between allocator impls */ + const uint32_t version; /* api version */ int width; /* width of buffer in pixels */ int height; /* height of buffer in pixels */ @@ -67,6 +70,7 @@ struct gralloc_handle_t { } __attribute__((aligned(8))); }; +#define GRALLOC_HANDLE_VERSION 1 #define GRALLOC_HANDLE_MAGIC 0x60585350 #define GRALLOC_HANDLE_NUM_FDS 1 #define GRALLOC_HANDLE_NUM_INTS ( \ @@ -79,7 +83,9 @@ struct gralloc_handle_t { static struct gralloc_handle_t gralloc_handle_create(int width, int height, int format, int usage) { - struct gralloc_handle_t handle = { .magic = GRALLOC_HANDLE_MAGIC }; + struct alloc_handle_t handle = { + .magic = GRALLOC_HANDLE_MAGIC, + .version = GRALLOC_HANDLE_VERSION }; native_handle_t *nhandle = native_handle_create(GRALLOC_HANDLE_NUM_FDS, GRALLOC_HANDLE_NUM_INTS); -- cgit v1.2.3-54-g00ecf From ed0ed55f3e6c2e1a460d72fed270f6243dcf92a5 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 16 Jan 2018 15:19:15 +0100 Subject: android: Mark gralloc_handle_t magic variable as const Mark magic member of gralloc_handle_t as const. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- android/gralloc_handle.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index 7cbc8ee7..5d8a19ea 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -51,7 +51,7 @@ struct gralloc_handle_t { int prime_fd; /* api variables */ - int magic; /* differentiate between allocator impls */ + const int magic; /* differentiate between allocator impls */ const uint32_t version; /* api version */ int width; /* width of buffer in pixels */ -- cgit v1.2.3-54-g00ecf From 8e00d5ffbda7ae7ef6e33aa51aa71a0bf347f488 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 16 Jan 2018 14:38:41 +0100 Subject: android: Remove member name from gralloc_handle_t The name member of gralloc_handle_t is no longer needed and has been removed. The version field has also been bumped. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- android/gralloc_handle.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index 5d8a19ea..9648b006 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -59,7 +59,6 @@ struct gralloc_handle_t { int format; /* pixel format (Android) */ int usage; /* android libhardware usage flags */ - int name; /* the name of the bo */ int stride; /* the stride in bytes */ uint64_t modifier; /* buffer modifiers */ @@ -70,7 +69,7 @@ struct gralloc_handle_t { } __attribute__((aligned(8))); }; -#define GRALLOC_HANDLE_VERSION 1 +#define GRALLOC_HANDLE_VERSION 2 #define GRALLOC_HANDLE_MAGIC 0x60585350 #define GRALLOC_HANDLE_NUM_FDS 1 #define GRALLOC_HANDLE_NUM_INTS ( \ -- cgit v1.2.3-54-g00ecf From e75e0ea2e3e29aa65dff868b1088bd41d9405781 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 16 Jan 2018 18:07:15 +0100 Subject: android: Change gralloc_handle_t members to be fixed width In order to lessen future alignment issues, lets switch to fixed width integers where possible. This excludes the data_owner since it is a pid_t which in theory could be larger than 32 bits. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- android/gralloc_handle.h | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index 9648b006..b47bee19 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -51,15 +51,15 @@ struct gralloc_handle_t { int prime_fd; /* api variables */ - const int magic; /* differentiate between allocator impls */ + const uint32_t magic; /* differentiate between allocator impls */ const uint32_t version; /* api version */ - int width; /* width of buffer in pixels */ - int height; /* height of buffer in pixels */ - int format; /* pixel format (Android) */ - int usage; /* android libhardware usage flags */ + uint32_t width; /* width of buffer in pixels */ + uint32_t height; /* height of buffer in pixels */ + uint32_t format; /* pixel format (Android) */ + uint32_t usage; /* android libhardware usage flags */ - int stride; /* the stride in bytes */ + uint32_t stride; /* the stride in bytes */ uint64_t modifier; /* buffer modifiers */ int data_owner; /* owner of data (for validation) */ @@ -69,7 +69,7 @@ struct gralloc_handle_t { } __attribute__((aligned(8))); }; -#define GRALLOC_HANDLE_VERSION 2 +#define GRALLOC_HANDLE_VERSION 3 #define GRALLOC_HANDLE_MAGIC 0x60585350 #define GRALLOC_HANDLE_NUM_FDS 1 #define GRALLOC_HANDLE_NUM_INTS ( \ @@ -79,8 +79,10 @@ struct gralloc_handle_t { /** * Create a buffer handle. */ -static struct gralloc_handle_t gralloc_handle_create(int width, int height, - int format, int usage) +static struct gralloc_handle_t gralloc_handle_create(int32_t width, + int32_t height, + int32_t format, + int32_t usage) { struct alloc_handle_t handle = { .magic = GRALLOC_HANDLE_MAGIC, -- cgit v1.2.3-54-g00ecf From 36c816fbee30fd4f31ea5233fe97126deaacd625 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 17 Feb 2018 04:28:42 +0100 Subject: configure.ac: bump version to 2.4.90 --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 321ab2c0..c9c4754c 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.89], + [2.4.90], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) -- cgit v1.2.3-54-g00ecf From a05f5ac3023fd9a16b0dfffe30786e83c7513197 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 17 Feb 2018 20:20:33 +0100 Subject: meson: bump the version number --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 4aaeb7e1..166559e8 100644 --- a/meson.build +++ b/meson.build @@ -21,7 +21,7 @@ project( 'libdrm', ['c'], - version : '2.4.89', + version : '2.4.90', license : 'MIT', meson_version : '>= 0.43', default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], -- cgit v1.2.3-54-g00ecf From e87a87925ea23e84ed6f67de73a5ef2713ca2c49 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 17 Feb 2018 20:25:02 +0100 Subject: RELEASING: mention meson --- RELEASING | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/RELEASING b/RELEASING index 262ca08d..7e03e3b9 100644 --- a/RELEASING +++ b/RELEASING @@ -9,9 +9,9 @@ However, this is up to whoever is driving the feature in question. Follow these steps to release a new version of libdrm: - 1) Bump the version number in configure.ac. We seem to have settled - for 2.4.x as the versioning scheme for libdrm, so just bump the - micro version. + 1) Bump the version number in configure.ac and meson.build. We seem + to have settled for 2.4.x as the versioning scheme for libdrm, so + just bump the micro version. 2) Run autoconf and then re-run ./configure so the build system picks up the new version number. -- cgit v1.2.3-54-g00ecf From b3c4c79e16f13a72e8124f69453a37135329f968 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Nov 2017 18:51:26 +0100 Subject: drm/fourcc: Fix fourcc_mod_code() definition Avoid compiler warnings when the val parameter is an expression. This is based on commit 5843f4e02fbe86a59981e35adc6cabebee46fdc0 from Linux v4.16-rc1. Acked-by: Emil Velikov Signed-off-by: Thierry Reding --- include/drm/drm_fourcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index 3ad838d3..a76ed8f9 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -188,7 +188,7 @@ extern "C" { #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) #define fourcc_mod_code(vendor, val) \ - ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) + ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) /* * Format Modifier tokens: -- cgit v1.2.3-54-g00ecf From ab5aaf6c8eb93462c15007e9b54f4447c1ea8148 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Nov 2017 18:50:30 +0100 Subject: drm/tegra: Sanitize format modifiers The existing format modifier definitions were merged prematurely, and recent work has unveiled that the definitions are suboptimal in several ways: - The format specifiers, except for one, are not Tegra specific, but the names don't reflect that. - The number space is split into two, reserving 32 bits for some "parameter" which most of the modifiers are not going to have. - Symbolic names for the modifiers are not using the standard DRM_FORMAT_MOD_* prefix, which makes them awkward to use. - The vendor prefix NV is somewhat ambiguous. Fortunately, nobody's started using these modifiers, so we can still fix the above issues. Do so by using the standard prefix. Also, remove TEGRA from the name of those modifiers that exist on NVIDIA GPUs as well. In case of the block linear modifiers, make the "parameter" smaller (4 bits, though only 6 values are valid) and don't let that leak into any of the other modifiers. Finally, also use the more canonical NVIDIA instead of the ambiguous NV prefix. This is based on commit 5843f4e02fbe86a59981e35adc6cabebee46fdc0 from Linux v4.16-rc1 and also updates modetest to use the new defines. Acked-by: Emil Velikov Signed-off-by: Thierry Reding --- include/drm/drm_fourcc.h | 36 +++++++++++++++++++----------------- tests/modetest/modetest.c | 28 ++++++++++++++-------------- 2 files changed, 33 insertions(+), 31 deletions(-) diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index a76ed8f9..e04613d3 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -178,7 +178,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_NONE 0 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 -#define DRM_FORMAT_MOD_VENDOR_NV 0x03 +#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 @@ -338,29 +338,17 @@ extern "C" { */ #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) -/* NVIDIA Tegra frame buffer modifiers */ - -/* - * Some modifiers take parameters, for example the number of vertical GOBs in - * a block. Reserve the lower 32 bits for parameters - */ -#define __fourcc_mod_tegra_mode_shift 32 -#define fourcc_mod_tegra_code(val, params) \ - fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) -#define fourcc_mod_tegra_mod(m) \ - (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -#define fourcc_mod_tegra_param(m) \ - (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) +/* NVIDIA frame buffer modifiers */ /* * Tegra Tiled Layout, used by Tegra 2, 3 and 4. * * Pixels are arranged in simple tiles of 16 x 16 bytes. */ -#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) +#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) /* - * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 + * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later * * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked * vertically by a power of 2 (1 to 32 GOBs) to form a block. @@ -380,7 +368,21 @@ extern "C" { * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format * in full detail. */ -#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ + fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) + +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ + fourcc_mod_code(NVIDIA, 0x10) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ + fourcc_mod_code(NVIDIA, 0x11) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ + fourcc_mod_code(NVIDIA, 0x12) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ + fourcc_mod_code(NVIDIA, 0x13) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ + fourcc_mod_code(NVIDIA, 0x14) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ + fourcc_mod_code(NVIDIA, 0x15) /* * Broadcom VC4 "T" format diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index 0773bd02..fb9f15fc 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -278,20 +278,20 @@ static const char *modifier_to_string(uint64_t modifier) return "VIVANTE_SPLIT_TILED"; case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED: return "VIVANTE_SPLIT_SUPER_TILED"; - case NV_FORMAT_MOD_TEGRA_TILED: - return "MOD_TEGRA_TILED"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): - return "MOD_TEGRA_16BX2_BLOCK(0)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(1): - return "MOD_TEGRA_16BX2_BLOCK(1)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(2): - return "MOD_TEGRA_16BX2_BLOCK(2)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(3): - return "MOD_TEGRA_16BX2_BLOCK(3)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(4): - return "MOD_TEGRA_16BX2_BLOCK(4)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(5): - return "MOD_TEGRA_16BX2_BLOCK(5)"; + case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED: + return "NVIDIA_TEGRA_TILED"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0): + return "NVIDIA_16BX2_BLOCK(0)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1): + return "NVIDIA_16BX2_BLOCK(1)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2): + return "NVIDIA_16BX2_BLOCK(2)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3): + return "NVIDIA_16BX2_BLOCK(3)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4): + return "NVIDIA_16BX2_BLOCK(4)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5): + return "NVIDIA_16BX2_BLOCK(5)"; case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: return "MOD_BROADCOM_VC4_T_TILED"; default: -- cgit v1.2.3-54-g00ecf From 33a2851ab9bc3cd8a68bedf4cf0fdc549b0f3596 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 19 Feb 2018 02:18:36 -0500 Subject: amdgpu: Fix mistake in initial hole size calculation. Signed-off-by: Andrey Grodzovsky Acked-by: Christian König --- amdgpu/amdgpu_vamgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 722067f3..58400428 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -57,7 +57,7 @@ drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, pthread_mutex_init(&mgr->bo_va_mutex, NULL); pthread_mutex_lock(&mgr->bo_va_mutex); n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - n->size = mgr->va_max; + n->size = mgr->va_max - start; n->offset = start; list_add(&n->list, &mgr->va_holes); pthread_mutex_unlock(&mgr->bo_va_mutex); @@ -80,6 +80,7 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, struct amdgpu_bo_va_hole *hole, *n; uint64_t offset = 0, waste = 0; + alignment = MAX2(alignment, mgr->va_alignment); size = ALIGN(size, mgr->va_alignment); -- cgit v1.2.3-54-g00ecf From 9411f8ea03a4c019a0069845545cae45136596fc Mon Sep 17 00:00:00 2001 From: Igor Gnatenko Date: Mon, 19 Feb 2018 13:55:27 +0100 Subject: meson: do not use cairo/valgrind if disabled -Dcairo-tests=false currently results into enabling cairo support if it was found. Same for valgrind. v2: * Use underscore-prefixed variables to not change type of variable * Use empty array for "fake" dependency instead of real empty object v3: * Fix typo Reviewed-by: Eric Engestrom Signed-off-by: Igor Gnatenko --- meson.build | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/meson.build b/meson.build index 166559e8..7f786a8c 100644 --- a/meson.build +++ b/meson.build @@ -32,8 +32,6 @@ pkg = import('pkgconfig') with_udev = get_option('udev') with_freedreno_kgsl = get_option('freedreno-kgsl') with_install_tests = get_option('install-test-programs') -with_cairo_tests = get_option('cairo-tests') -with_valgrind = get_option('valgrind') config = configuration_data() @@ -226,8 +224,22 @@ endforeach dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : with_intel) dep_cunit = dependency('cunit', version : '>= 2.1', required : false) -dep_cairo = dependency('cairo', required : with_cairo_tests == 'true') -dep_valgrind = dependency('valgrind', required : with_valgrind == 'true') +_cairo_tests = get_option('cairo-tests') +if _cairo_tests != 'false' + dep_cairo = dependency('cairo', required : _cairo_tests == 'true') + with_cairo_tests = dep_cairo.found() +else + dep_cairo = [] + with_cairo_tests = false +endif +_valgrind = get_option('valgrind') +if _valgrind != 'false' + dep_valgrind = dependency('valgrind', required : _valgrind == 'true') + with_valgrind = dep_valgrind.found() +else + dep_valgrind = [] + with_valgrind = false +endif with_man_pages = get_option('man-pages') prog_xslt = find_program('xsltproc', required : with_man_pages == 'true') @@ -259,8 +271,8 @@ foreach t : [ [with_radeon, 'RADEON'], [with_vc4, 'VC4'], [with_vmwgfx, 'VMWGFX'], - [dep_cairo.found(), 'CAIRO'], - [dep_valgrind.found(), 'VALGRIND'], + [with_cairo_tests, 'CAIRO'], + [with_valgrind, 'VALGRIND'], ] config.set10('HAVE_@0@'.format(t[1]), t[0]) endforeach -- cgit v1.2.3-54-g00ecf From 9eb6c8a6b1aad741ddd23f8fd85925d795edbee3 Mon Sep 17 00:00:00 2001 From: Jonathan Gray Date: Tue, 20 Feb 2018 17:09:14 +1100 Subject: meson/configure.ac: pthread-stubs not present on OpenBSD pthread-stubs is no longer required on OpenBSD and has been removed. libpthread parts involved moved to libc. Signed-off-by: Jonathan Gray Reviewed-by: Eric Engestrom [Eric: add meson equivalent] Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- configure.ac | 4 ++-- meson.build | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index c9c4754c..68270004 100644 --- a/configure.ac +++ b/configure.ac @@ -65,10 +65,10 @@ AC_CHECK_HEADERS([sys/sysctl.h sys/select.h]) LT_PREREQ([2.2]) LT_INIT([disable-static]) -dnl pthread-stubs is mandatory on BSD platforms, due to the nature of the +dnl pthread-stubs is mandatory on some BSD platforms, due to the nature of the dnl project. Even then there's a notable issue as described in the project README case "$host_os" in -linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu*) +linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu* | openbsd*) pthread_stubs_possible="no" ;; * ) diff --git a/meson.build b/meson.build index 7f786a8c..f6b1a432 100644 --- a/meson.build +++ b/meson.build @@ -35,8 +35,7 @@ with_install_tests = get_option('install-test-programs') config = configuration_data() -# TODO: openbsd is guess, the others are correct -if ['freebsd', 'dragonfly', 'netbsd', 'openbsd'].contains(host_machine.system()) +if ['freebsd', 'dragonfly', 'netbsd'].contains(host_machine.system()) dep_pthread_stubs = dependency('pthread-stubs', version : '>= 0.4') else dep_pthread_stubs = [] -- cgit v1.2.3-54-g00ecf From 5db7bf41b27d7445f2920a938c780920b6c27851 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 14 Feb 2018 17:10:25 -0600 Subject: android: revert making handle magic and version members const Const members are problematic for dynamically allocating struct gralloc_handle_t, so just drop the const modifier. Reviewed-by: Robert Foss Signed-off-by: Rob Herring --- android/gralloc_handle.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index b47bee19..b035e035 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -51,8 +51,8 @@ struct gralloc_handle_t { int prime_fd; /* api variables */ - const uint32_t magic; /* differentiate between allocator impls */ - const uint32_t version; /* api version */ + uint32_t magic; /* differentiate between allocator impls */ + uint32_t version; /* api version */ uint32_t width; /* width of buffer in pixels */ uint32_t height; /* height of buffer in pixels */ -- cgit v1.2.3-54-g00ecf From 652bcea5a609ab6de1f54d2143968c954a37e959 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 14 Feb 2018 17:06:46 -0600 Subject: android: fix mis-named alloc_handle_t Fix a typo where alloc_handle_t should be gralloc_handle_t. One still remains in gralloc_handle_create, but a subsequent commit will fix that along with other problems in gralloc_handle_create. Reviewed-by: Robert Foss Signed-off-by: Rob Herring --- android/gralloc_handle.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index b035e035..b0f5048c 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -73,7 +73,7 @@ struct gralloc_handle_t { #define GRALLOC_HANDLE_MAGIC 0x60585350 #define GRALLOC_HANDLE_NUM_FDS 1 #define GRALLOC_HANDLE_NUM_INTS ( \ - ((sizeof(struct alloc_handle_t) - sizeof(native_handle_t))/sizeof(int)) \ + ((sizeof(struct gralloc_handle_t) - sizeof(native_handle_t))/sizeof(int)) \ - GRALLOC_HANDLE_NUM_FDS) /** -- cgit v1.2.3-54-g00ecf From 86c62e49c81eb56200ec72936462a9a8629d7d1d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 14 Feb 2018 17:05:42 -0600 Subject: android: add helper to convert buffer_handle_t to gralloc_handle_t ptr Clients frequently need to convert a buffer_handle_t (aka native_handle_t *) to a gralloc_handle_t ptr. This is a simple cast, but add an inline function to do the conversion. Reviewed-by: Robert Foss Signed-off-by: Rob Herring --- android/gralloc_handle.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index b0f5048c..43255ba5 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -76,6 +76,11 @@ struct gralloc_handle_t { ((sizeof(struct gralloc_handle_t) - sizeof(native_handle_t))/sizeof(int)) \ - GRALLOC_HANDLE_NUM_FDS) +static inline struct gralloc_handle_t *gralloc_handle(buffer_handle_t handle) +{ + return (struct gralloc_handle_t *)handle; +} + /** * Create a buffer handle. */ -- cgit v1.2.3-54-g00ecf From 009634e493097afae95d190fc26cb04a1664648a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 14 Feb 2018 17:03:56 -0600 Subject: android: fix gralloc_handle_create() problems There's a number of problems with gralloc_handle_create starting with it doesn't even compile. More importantly, it doesn't really create (i.e. allocate) a handle. It allocates a native_handle_t, copies it to a struct gralloc_handle_t on the stack and returns the struct (not a ptr). So the caller still has to allocate a struct gralloc_handle_t to hold the returned struct. Rework gralloc_handle_create() to allocate a new handle and return the pointer to the allocated handle. Callers should free the handle with native_handle_close() and native_handle_delete(). In the interest of making gralloc_handle_t opaque, return a native_handle_t ptr instead. Reviewed-by: Robert Foss Signed-off-by: Rob Herring --- android/gralloc_handle.h | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index 43255ba5..9cb5a5d7 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -84,28 +84,26 @@ static inline struct gralloc_handle_t *gralloc_handle(buffer_handle_t handle) /** * Create a buffer handle. */ -static struct gralloc_handle_t gralloc_handle_create(int32_t width, +static inline native_handle_t *gralloc_handle_create(int32_t width, int32_t height, - int32_t format, + int32_t hal_format, int32_t usage) { - struct alloc_handle_t handle = { - .magic = GRALLOC_HANDLE_MAGIC, - .version = GRALLOC_HANDLE_VERSION }; - + struct gralloc_handle_t *handle; native_handle_t *nhandle = native_handle_create(GRALLOC_HANDLE_NUM_FDS, - GRALLOC_HANDLE_NUM_INTS); - handle.base = *nhandle; - native_handle_delete(nhandle); - - handle.width = width; - handle.height = height; - handle.format = format; - handle.usage = usage; - handle.prime_fd = -1; - - handle->data_owner = getpid(); - handle->data = bo; + GRALLOC_HANDLE_NUM_INTS); + + if (!nhandle) + return NULL; + + handle = gralloc_handle(nhandle); + handle->magic = GRALLOC_HANDLE_MAGIC; + handle->version = GRALLOC_HANDLE_VERSION; + handle->width = width; + handle->height = height; + handle->format = hal_format; + handle->usage = usage; + handle->prime_fd = -1; return handle; } -- cgit v1.2.3-54-g00ecf From 4f08bfe96da1542f336589edf310d06ebce3cf20 Mon Sep 17 00:00:00 2001 From: Heiko Becker Date: Mon, 19 Feb 2018 15:13:15 +0000 Subject: *-symbol-check: Don't hard-code nm executable Helpful if your nm executable has a prefix based on the architecture, for example. Signed-off-by: Heiko Becker Cc: Timo Gurr [Eric: v2: rebase and add Meson support] Signed-off-by: Eric Engestrom Reviewed-by: Eric Anholt Reviewed-by: Emil Velikov --- amdgpu/amdgpu-symbol-check | 2 +- amdgpu/meson.build | 1 + configure.ac | 1 + exynos/exynos-symbol-check | 2 +- exynos/meson.build | 1 + freedreno/freedreno-symbol-check | 2 +- freedreno/meson.build | 1 + intel/intel-symbol-check | 2 +- intel/meson.build | 1 + libkms/kms-symbol-check | 2 +- libkms/meson.build | 1 + meson.build | 3 +++ nouveau/meson.build | 1 + nouveau/nouveau-symbol-check | 2 +- omap/meson.build | 1 + omap/omap-symbol-check | 2 +- radeon/meson.build | 1 + radeon/radeon-symbol-check | 2 +- tegra/meson.build | 1 + tegra/tegra-symbol-check | 2 +- 20 files changed, 22 insertions(+), 9 deletions(-) diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 17de0c3b..90b7a1d6 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -3,7 +3,7 @@ # The following symbols (past the first five) are taken from the public headers. # A list of the latter should be available Makefile.am/libdrm_amdgpuinclude_HEADERS -FUNCS=$(nm -D --format=bsd --defined-only ${1-.libs/libdrm_amdgpu.so} | awk '{print $3}' | while read func; do +FUNCS=$($NM -D --format=bsd --defined-only ${1-.libs/libdrm_amdgpu.so} | awk '{print $3}' | while read func; do ( grep -q "^$func$" || echo $func ) < --- freedreno/freedreno_bo.c | 10 ++++++++++ freedreno/freedreno_drmif.h | 3 +++ freedreno/freedreno_priv.h | 1 + freedreno/msm/msm_bo.c | 13 +++++++++++++ 4 files changed, 27 insertions(+) diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index df35c36a..331b8227 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -195,6 +195,16 @@ out_unlock: return bo; } +uint64_t fd_bo_get_iova(struct fd_bo *bo) +{ + return bo->funcs->iova(bo); +} + +void fd_bo_put_iova(struct fd_bo *bo) +{ + /* currently a no-op */ +} + struct fd_bo * fd_bo_ref(struct fd_bo *bo) { atomic_inc(&bo->refcnt); diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h index c3b0d02a..2711518b 100644 --- a/freedreno/freedreno_drmif.h +++ b/freedreno/freedreno_drmif.h @@ -95,6 +95,7 @@ enum fd_version { FD_VERSION_UNLIMITED_CMDS = 1, /* submits w/ >4 cmd buffers (growable ringbuffer) */ FD_VERSION_FENCE_FD = 2, /* submit command supports in/out fences */ FD_VERSION_SUBMIT_QUEUES = 3, /* submit queues and multiple priority levels */ + FD_VERSION_BO_IOVA = 3, /* supports fd_bo_get/put_iova() */ }; enum fd_version fd_device_version(struct fd_device *dev); @@ -123,6 +124,8 @@ struct fd_bo *fd_bo_from_handle(struct fd_device *dev, uint32_t handle, uint32_t size); struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name); struct fd_bo * fd_bo_from_dmabuf(struct fd_device *dev, int fd); +uint64_t fd_bo_get_iova(struct fd_bo *bo); +void fd_bo_put_iova(struct fd_bo *bo); struct fd_bo * fd_bo_ref(struct fd_bo *bo); void fd_bo_del(struct fd_bo *bo); int fd_bo_get_name(struct fd_bo *bo, uint32_t *name); diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index 81ad6092..a0957fad 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -157,6 +157,7 @@ struct fd_bo_funcs { int (*cpu_prep)(struct fd_bo *bo, struct fd_pipe *pipe, uint32_t op); void (*cpu_fini)(struct fd_bo *bo); int (*madvise)(struct fd_bo *bo, int willneed); + uint64_t (*iova)(struct fd_bo *bo); void (*destroy)(struct fd_bo *bo); }; diff --git a/freedreno/msm/msm_bo.c b/freedreno/msm/msm_bo.c index 72471df6..281c5aa7 100644 --- a/freedreno/msm/msm_bo.c +++ b/freedreno/msm/msm_bo.c @@ -108,6 +108,18 @@ static int msm_bo_madvise(struct fd_bo *bo, int willneed) return req.retained; } +static uint64_t msm_bo_iova(struct fd_bo *bo) +{ + struct drm_msm_gem_info req = { + .handle = bo->handle, + .flags = MSM_INFO_IOVA, + }; + + drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req)); + + return req.offset; +} + static void msm_bo_destroy(struct fd_bo *bo) { struct msm_bo *msm_bo = to_msm_bo(bo); @@ -120,6 +132,7 @@ static const struct fd_bo_funcs funcs = { .cpu_prep = msm_bo_cpu_prep, .cpu_fini = msm_bo_cpu_fini, .madvise = msm_bo_madvise, + .iova = msm_bo_iova, .destroy = msm_bo_destroy, }; -- cgit v1.2.3-54-g00ecf From cd8a80493beea4fbdd0a2e0b68ef0adbdaac1133 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 26 Feb 2018 12:30:36 +0100 Subject: amdgpu: mostly revert "use the high VA range if possible v2" This reverts commit 07ea20d5beb24315b721adf83bbfa72ce016e146. Unfortunately it turned out that this change broke some corner cases in Mesa. Revert it for now, but keep the high range in separate VA managers. Signed-off-by: Christian König Reviewed-by: Marek Olšák --- amdgpu/amdgpu_device.c | 28 +++++++++++++++------------- amdgpu/amdgpu_internal.h | 6 +++++- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 6ee25a9e..ca0c7987 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -264,27 +264,29 @@ int amdgpu_device_initialize(int fd, goto cleanup; } - if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) { - start = dev->dev_info.high_va_offset; - max = dev->dev_info.high_va_max; - } else { - start = dev->dev_info.virtual_address_offset; - max = dev->dev_info.virtual_address_max; - } - - max = MIN2(max, (start & ~0xffffffffULL) + 0x100000000ULL); + start = dev->dev_info.virtual_address_offset; + max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); dev->address32_hi = start >> 32; start = max; - if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) - max = dev->dev_info.high_va_max; - else - max = dev->dev_info.virtual_address_max; + max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr, start, max, dev->dev_info.virtual_address_alignment); + start = dev->dev_info.high_va_offset; + max = MIN2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) + + 0x100000000ULL); + amdgpu_vamgr_init(&dev->vamgr_high_32, start, max, + dev->dev_info.virtual_address_alignment); + + start = max; + max = MAX2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) + + 0x100000000ULL); + amdgpu_vamgr_init(&dev->vamgr_high, start, max, + dev->dev_info.virtual_address_alignment); + amdgpu_parse_asic_ids(dev); *major_version = dev->major_version; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index dd0c3a61..423880ed 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -84,10 +84,14 @@ struct amdgpu_device { pthread_mutex_t bo_table_mutex; struct drm_amdgpu_info_device dev_info; struct amdgpu_gpu_info info; - /** The global VA manager for the whole virtual address space */ + /** The VA manager for the lower virtual address space */ struct amdgpu_bo_va_mgr vamgr; /** The VA manager for the 32bit address space */ struct amdgpu_bo_va_mgr vamgr_32; + /** The VA manager for the high virtual address space */ + struct amdgpu_bo_va_mgr vamgr_high; + /** The VA manager for the 32bit high address space */ + struct amdgpu_bo_va_mgr vamgr_high_32; }; struct amdgpu_bo { -- cgit v1.2.3-54-g00ecf From ff0da7b32369a08c8a2f69cd4dcd046ad7a15bec Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 26 Feb 2018 14:11:52 +0100 Subject: amdgpu: add AMDGPU_VA_RANGE_HIGH Return high addresses if requested and available. Signed-off-by: Christian König Reviewed-by: Marek Olšák --- amdgpu/amdgpu.h | 1 + amdgpu/amdgpu_device.c | 6 ++++-- amdgpu/amdgpu_internal.h | 1 - amdgpu/amdgpu_vamgr.c | 24 +++++++++++++++++++----- 4 files changed, 24 insertions(+), 8 deletions(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 928b2a68..36f91058 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1162,6 +1162,7 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, * Flag to request VA address range in the 32bit address space */ #define AMDGPU_VA_RANGE_32_BIT 0x1 +#define AMDGPU_VA_RANGE_HIGH 0x2 /** * Allocate virtual address range diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index ca0c7987..9ff6ad16 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -268,7 +268,6 @@ int amdgpu_device_initialize(int fd, max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL); amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); - dev->address32_hi = start >> 32; start = max; max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); @@ -323,7 +322,10 @@ int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, switch (info) { case amdgpu_sw_info_address32_hi: - *val32 = dev->address32_hi; + if (dev->vamgr_high_32.va_max) + *val32 = dev->vamgr_high_32.va_max >> 32; + else + *val32 = dev->vamgr_32.va_max >> 32; return 0; } return -EINVAL; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 423880ed..aeb5d651 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -73,7 +73,6 @@ struct amdgpu_device { int flink_fd; unsigned major_version; unsigned minor_version; - uint32_t address32_hi; char *marketing_name; /** List of buffer handles. Protected by bo_table_mutex. */ diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 58400428..ac1202de 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -201,10 +201,21 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, { struct amdgpu_bo_va_mgr *vamgr; - if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = &dev->vamgr_32; - else - vamgr = &dev->vamgr; + /* Clear the flag when the high VA manager is not initialized */ + if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) + flags &= ~AMDGPU_VA_RANGE_HIGH; + + if (flags & AMDGPU_VA_RANGE_HIGH) { + if (flags & AMDGPU_VA_RANGE_32_BIT) + vamgr = &dev->vamgr_high_32; + else + vamgr = &dev->vamgr_high; + } else { + if (flags & AMDGPU_VA_RANGE_32_BIT) + vamgr = &dev->vamgr_32; + else + vamgr = &dev->vamgr; + } va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); size = ALIGN(size, vamgr->va_alignment); @@ -215,7 +226,10 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, if (!(flags & AMDGPU_VA_RANGE_32_BIT) && (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { /* fallback to 32bit address */ - vamgr = &dev->vamgr_32; + if (flags & AMDGPU_VA_RANGE_HIGH) + vamgr = &dev->vamgr_high_32; + else + vamgr = &dev->vamgr_32; *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, va_base_alignment, va_base_required); } -- cgit v1.2.3-54-g00ecf From bca585b02f09e27d7adef8375630515711bd4802 Mon Sep 17 00:00:00 2001 From: Christian König Date: Wed, 28 Feb 2018 15:39:46 +0100 Subject: amdgpu: fix "add AMDGPU_VA_RANGE_HIGH" The range is stored as exclusive, not inclusive. Subtracts one to get the inclusive interval for the calculation. This fixes crashes when 32bit addresses are in use. Signed-off-by: Christian König Reviewed-and-Tested-by: Michel Dänzer --- amdgpu/amdgpu_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 9ff6ad16..fb2cfb57 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -323,9 +323,9 @@ int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, switch (info) { case amdgpu_sw_info_address32_hi: if (dev->vamgr_high_32.va_max) - *val32 = dev->vamgr_high_32.va_max >> 32; + *val32 = (dev->vamgr_high_32.va_max - 1) >> 32; else - *val32 = dev->vamgr_32.va_max >> 32; + *val32 = (dev->vamgr_32.va_max - 1) >> 32; return 0; } return -EINVAL; -- cgit v1.2.3-54-g00ecf From 1f6a85cc3773025940005e443f9bddcbf1795c27 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Thu, 1 Mar 2018 18:04:07 +0800 Subject: test/amdgpu: disable bo eviction test by default if some system has no swap space and memory is less, than the test could fail. And bo eviction test takes much more time in some system, which effects automation test result and efficiency. So disable it by default now, only be used by developer manually. Signed-off-by: Chunming Zhou Acked-by: Christian König --- tests/amdgpu/amdgpu_test.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 4f766aaf..35cb37a4 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -432,6 +432,8 @@ static void amdgpu_disable_suits() if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); /* This test was ran on GFX8 and GFX9 only */ if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV) -- cgit v1.2.3-54-g00ecf From a1a13d2002666922dbc7530c6f16aad600c3c3f3 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 1 Mar 2018 11:15:42 +0100 Subject: tests/amdgpu: Fix misspellings of "suite" Acked-by: Christian König --- tests/amdgpu/amdgpu_test.c | 12 ++++++------ tests/amdgpu/amdgpu_test.h | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 35cb37a4..e49f4a6c 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -51,7 +51,7 @@ #include "amdgpu_test.h" #include "amdgpu_internal.h" -/* Test suit names */ +/* Test suite names */ #define BASIC_TESTS_STR "Basic Tests" #define BO_TESTS_STR "BO Tests" #define CS_TESTS_STR "CS Tests" @@ -399,7 +399,7 @@ static int amdgpu_find_device(uint8_t bus, uint16_t dev) return -1; } -static void amdgpu_disable_suits() +static void amdgpu_disable_suites() { amdgpu_device_handle device_handle; uint32_t major_version, minor_version, family_id; @@ -415,11 +415,11 @@ static void amdgpu_disable_suits() if (amdgpu_device_deinitialize(device_handle)) return; - /* Set active status for suits based on their policies */ + /* Set active status for suites based on their policies */ for (i = 0; i < size; ++i) if (amdgpu_set_suite_active(suites_active_stat[i].pName, suites_active_stat[i].pActive())) - fprintf(stderr, "suit deactivation failed - %s\n", CU_get_error_msg()); + fprintf(stderr, "suite deactivation failed - %s\n", CU_get_error_msg()); /* Explicitly disable specific tests due to known bugs or preferences */ /* @@ -557,8 +557,8 @@ int main(int argc, char **argv) /* Run tests using the CUnit Basic interface */ CU_basic_set_mode(CU_BRM_VERBOSE); - /* Disable suits and individual tests based on misc. conditions */ - amdgpu_disable_suits(); + /* Disable suites and individual tests based on misc. conditions */ + amdgpu_disable_suites(); if (display_list) { display_test_suites(); diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 7397dea0..62875736 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -350,26 +350,26 @@ amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1, } -static inline CU_ErrorCode amdgpu_set_suite_active(const char *suit_name, +static inline CU_ErrorCode amdgpu_set_suite_active(const char *suite_name, CU_BOOL active) { - CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suit_name), active); + CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suite_name), active); if (r != CUE_SUCCESS) - fprintf(stderr, "Failed to obtain suite %s\n", suit_name); + fprintf(stderr, "Failed to obtain suite %s\n", suite_name); return r; } -static inline CU_ErrorCode amdgpu_set_test_active(const char *suit_name, +static inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name, const char *test_name, CU_BOOL active) { CU_ErrorCode r; - CU_pSuite pSuite = CU_get_suite(suit_name); + CU_pSuite pSuite = CU_get_suite(suite_name); if (!pSuite) { fprintf(stderr, "Failed to obtain suite %s\n", - suit_name); + suite_name); return CUE_NOSUITE; } -- cgit v1.2.3-54-g00ecf From 7a58c21f3ef3fd9f47d9f73cc9d725996ad691a0 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Mon, 26 Feb 2018 15:42:18 +0000 Subject: meson: add configuration summary The message block printed is the same as the one in configure.ac Signed-off-by: Eric Engestrom --- meson.build | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/meson.build b/meson.build index 15a2b084..7bf26819 100644 --- a/meson.build +++ b/meson.build @@ -373,3 +373,20 @@ if with_man_pages endif subdir('data') subdir('tests') + +message('') +message('@0@ will be compiled with:'.format(meson.project_name())) +message('') +message(' libkms @0@'.format(with_libkms)) +message(' Intel API @0@'.format(with_intel)) +message(' vmwgfx API @0@'.format(with_vmwgfx)) +message(' Radeon API @0@'.format(with_radeon)) +message(' AMDGPU API @0@'.format(with_amdgpu)) +message(' Nouveau API @0@'.format(with_nouveau)) +message(' OMAP API @0@'.format(with_omap)) +message(' EXYNOS API @0@'.format(with_exynos)) +message(' Freedreno API @0@ (kgsl: @1@)'.format(with_freedreno, with_freedreno_kgsl)) +message(' Tegra API @0@'.format(with_tegra)) +message(' VC4 API @0@'.format(with_vc4)) +message(' Etnaviv API @0@'.format(with_etnaviv)) +message('') -- cgit v1.2.3-54-g00ecf From 85ae22af0f209e73c954d8867d9189ab2cfeb3e1 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 5 Mar 2018 15:55:51 -0500 Subject: bump version for release Signed-off-by: Rob Clark --- configure.ac | 2 +- meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index 02644a66..ec5003f6 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.90], + [2.4.91], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) diff --git a/meson.build b/meson.build index 7bf26819..c803f709 100644 --- a/meson.build +++ b/meson.build @@ -21,7 +21,7 @@ project( 'libdrm', ['c'], - version : '2.4.90', + version : '2.4.91', license : 'MIT', meson_version : '>= 0.43', default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], -- cgit v1.2.3-54-g00ecf From 7b12381723021fd5fbcf761e6832dd16a14f52d4 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Wed, 7 Feb 2018 22:46:43 -0800 Subject: intel/intel_chipset.h: Sync Cannonlake IDs. Let's sync CNL ids with Spec and kernel. Sync with kernel commit '3f43031b1693 ("drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.")' and commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")' Cc: James Ausmus Cc: Lucas De Marchi Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Rafael Antognolli --- intel/intel_chipset.h | 52 +++++++++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3818e71e..01d250e8 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -241,16 +241,20 @@ #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 -#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 -#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A -#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 -#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A -#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 -#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 -#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 -#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 -#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 -#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 +#define PCI_CHIP_CANNONLAKE_0 0x5A51 +#define PCI_CHIP_CANNONLAKE_1 0x5A59 +#define PCI_CHIP_CANNONLAKE_2 0x5A41 +#define PCI_CHIP_CANNONLAKE_3 0x5A49 +#define PCI_CHIP_CANNONLAKE_4 0x5A52 +#define PCI_CHIP_CANNONLAKE_5 0x5A5A +#define PCI_CHIP_CANNONLAKE_6 0x5A42 +#define PCI_CHIP_CANNONLAKE_7 0x5A4A +#define PCI_CHIP_CANNONLAKE_8 0x5A50 +#define PCI_CHIP_CANNONLAKE_9 0x5A40 +#define PCI_CHIP_CANNONLAKE_10 0x5A54 +#define PCI_CHIP_CANNONLAKE_11 0x5A5C +#define PCI_CHIP_CANNONLAKE_12 0x5A44 +#define PCI_CHIP_CANNONLAKE_13 0x5A4C #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -515,20 +519,20 @@ IS_GEMINILAKE(devid) || \ IS_COFFEELAKE(devid)) -#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) - -#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) - -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ - IS_CNL_Y(devid)) +#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ + (devid) == PCI_CHIP_CANNONLAKE_1 || \ + (devid) == PCI_CHIP_CANNONLAKE_2 || \ + (devid) == PCI_CHIP_CANNONLAKE_3 || \ + (devid) == PCI_CHIP_CANNONLAKE_4 || \ + (devid) == PCI_CHIP_CANNONLAKE_5 || \ + (devid) == PCI_CHIP_CANNONLAKE_6 || \ + (devid) == PCI_CHIP_CANNONLAKE_7 || \ + (devid) == PCI_CHIP_CANNONLAKE_8 || \ + (devid) == PCI_CHIP_CANNONLAKE_9 || \ + (devid) == PCI_CHIP_CANNONLAKE_10 || \ + (devid) == PCI_CHIP_CANNONLAKE_11 || \ + (devid) == PCI_CHIP_CANNONLAKE_12 || \ + (devid) == PCI_CHIP_CANNONLAKE_13) #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) -- cgit v1.2.3-54-g00ecf From 45eee3fd44f4fa253cd4d5c03f48d4a6899f899f Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Wed, 7 Mar 2018 12:41:12 +0000 Subject: drm/atomic: Refuse to add invalid objects to requests Object and property IDs cannot be zero. Prevent them from being added to the request stream at all, rather than breaking at commit time. Signed-off-by: Daniel Stone Reviewed-by: Daniel Vetter --- xf86drmMode.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xf86drmMode.c b/xf86drmMode.c index 15957ffc..bd59ef25 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -1313,6 +1313,9 @@ int drmModeAtomicAddProperty(drmModeAtomicReqPtr req, if (!req) return -EINVAL; + if (object_id == 0 || property_id == 0) + return -EINVAL; + if (req->cursor >= req->size_items) { drmModeAtomicReqItemPtr new; -- cgit v1.2.3-54-g00ecf From 28370370afb2b291a2cfe6a5478a29d9a1b1c28f Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 6 Mar 2018 15:37:55 +0000 Subject: freedreno: add missing symbols to symbol-check Fixes: 1384c081233751569473 "freedreno: add interface to get buffer address" Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Christian Gmeiner --- freedreno/freedreno-symbol-check | 2 ++ 1 file changed, 2 insertions(+) diff --git a/freedreno/freedreno-symbol-check b/freedreno/freedreno-symbol-check index 56e3d3ee..3b119528 100755 --- a/freedreno/freedreno-symbol-check +++ b/freedreno/freedreno-symbol-check @@ -18,10 +18,12 @@ fd_bo_from_dmabuf fd_bo_from_fbdev fd_bo_from_handle fd_bo_from_name +fd_bo_get_iova fd_bo_get_name fd_bo_handle fd_bo_map fd_bo_new +fd_bo_put_iova fd_bo_ref fd_bo_size fd_device_del -- cgit v1.2.3-54-g00ecf From 924f856a9047b87e8bfdc2867f7fe484e3f71343 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 7 Mar 2017 15:00:34 +0800 Subject: amdgpu:support 16 ibs per submit for PAL/SRIOV to support SRIOV and MCBP, need 16 IBs per submit Signed-off-by: Qiang Yu Reviewed-by: Junwei Zhang Acked-by: Christian König Reviewed-by: Alex Deucher --- amdgpu/amdgpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 36f91058..4c17247e 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -53,7 +53,7 @@ struct drm_amdgpu_info_hw_ip; * * \sa amdgpu_cs_ib_info */ -#define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 +#define AMDGPU_CS_MAX_IBS_PER_SUBMIT 16 /** * Special timeout value meaning that the timeout is infinite. -- cgit v1.2.3-54-g00ecf From 666d59d86b548dc553f295bf2db7513848536768 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 8 Mar 2018 20:04:01 -0500 Subject: Revert "amdgpu:support 16 ibs per submit for PAL/SRIOV" This reverts commit 924f856a9047b87e8bfdc2867f7fe484e3f71343. Wrong patch. --- amdgpu/amdgpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 4c17247e..36f91058 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -53,7 +53,7 @@ struct drm_amdgpu_info_hw_ip; * * \sa amdgpu_cs_ib_info */ -#define AMDGPU_CS_MAX_IBS_PER_SUBMIT 16 +#define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 /** * Special timeout value meaning that the timeout is infinite. -- cgit v1.2.3-54-g00ecf From a5329cd990cd1b85e2755f708fd9e48ac06b99a7 Mon Sep 17 00:00:00 2001 From: Sabre Shao Date: Fri, 8 Sep 2017 17:43:51 +0800 Subject: drm/amdgpu: Remove IB count checking Signed-off-by: Sabre Shao Reviewed-by: Marek Olšák --- amdgpu/amdgpu_cs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 46dffe1d..4ac9bac7 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -195,8 +195,6 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, return -EINVAL; if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; - if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT) - return -EINVAL; if (ibs_request->number_of_ibs == 0) { ibs_request->seq_no = AMDGPU_NULL_SUBMIT_SEQ; return 0; -- cgit v1.2.3-54-g00ecf From 5236de6cc1ee3759567e0fd8cd6260386b8d5b7e Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Wed, 7 Feb 2018 14:20:52 +0000 Subject: meson: use pkg-config to detect libatomic_ops Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- amdgpu/meson.build | 2 +- etnaviv/meson.build | 2 +- freedreno/meson.build | 2 +- intel/meson.build | 2 +- meson.build | 4 +++- nouveau/meson.build | 2 +- omap/meson.build | 2 +- radeon/meson.build | 2 +- tegra/meson.build | 2 +- 9 files changed, 11 insertions(+), 9 deletions(-) diff --git a/amdgpu/meson.build b/amdgpu/meson.build index 518b8504..f39d7bf6 100644 --- a/amdgpu/meson.build +++ b/amdgpu/meson.build @@ -37,7 +37,7 @@ libdrm_amdgpu = shared_library( ], include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : dep_pthread_stubs, + dependencies : [dep_pthread_stubs, dep_atomic_ops], version : '1.0.0', install : true, ) diff --git a/etnaviv/meson.build b/etnaviv/meson.build index 1767733b..ca2aa544 100644 --- a/etnaviv/meson.build +++ b/etnaviv/meson.build @@ -31,7 +31,7 @@ libdrm_etnaviv = shared_library( include_directories : [inc_root, inc_drm], link_with : libdrm, c_args : warn_c_args, - dependencies : [dep_pthread_stubs, dep_rt], + dependencies : [dep_pthread_stubs, dep_rt, dep_atomic_ops], version : '1.0.0', install : true, ) diff --git a/freedreno/meson.build b/freedreno/meson.build index 741b3b6a..015b7fb1 100644 --- a/freedreno/meson.build +++ b/freedreno/meson.build @@ -44,7 +44,7 @@ libdrm_freedreno = shared_library( [files_freedreno, config_file], c_args : warn_c_args, include_directories : [inc_root, inc_drm], - dependencies : [dep_valgrind, dep_pthread_stubs, dep_rt], + dependencies : [dep_valgrind, dep_pthread_stubs, dep_rt, dep_atomic_ops], link_with : libdrm, version : '1.0.0', install : true, diff --git a/intel/meson.build b/intel/meson.build index aa5a1349..53c7fce4 100644 --- a/intel/meson.build +++ b/intel/meson.build @@ -29,7 +29,7 @@ libdrm_intel = shared_library( ], include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : [dep_pciaccess, dep_pthread_stubs, dep_rt, dep_valgrind], + dependencies : [dep_pciaccess, dep_pthread_stubs, dep_rt, dep_valgrind, dep_atomic_ops], c_args : warn_c_args, version : '1.0.0', install : true, diff --git a/meson.build b/meson.build index c803f709..df6f2bd2 100644 --- a/meson.build +++ b/meson.build @@ -48,6 +48,7 @@ cc = meson.get_compiler('c') intel_atomics = false lib_atomics = false +dep_atomic_ops = dependency('atomic_ops', required : false) if cc.compiles(''' int atomic_add(int *i) { return __sync_add_and_fetch (i, 1); } int atomic_cmpxchg(int *i, int j, int k) { return __sync_val_compare_and_swap (i, j, k); } @@ -55,7 +56,8 @@ if cc.compiles(''' name : 'Intel Atomics') intel_atomics = true with_atomics = true -elif cc.has_header('atomic_ops.h') + dep_atomic_ops = [] +elif dep_atomic_ops.found() lib_atomics = true with_atomics = true elif cc.has_function('atomic_cas_uint') diff --git a/nouveau/meson.build b/nouveau/meson.build index 80a8678c..51c9a712 100644 --- a/nouveau/meson.build +++ b/nouveau/meson.build @@ -25,7 +25,7 @@ libdrm_nouveau = shared_library( c_args : warn_c_args, include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : dep_threads, + dependencies : [dep_threads, dep_atomic_ops], version : '2.0.0', install : true, ) diff --git a/omap/meson.build b/omap/meson.build index 8adb2213..e57b8f5d 100644 --- a/omap/meson.build +++ b/omap/meson.build @@ -24,7 +24,7 @@ libdrm_omap = shared_library( include_directories : [inc_root, inc_drm], c_args : warn_c_args, link_with : libdrm, - dependencies : [dep_pthread_stubs], + dependencies : [dep_pthread_stubs, dep_atomic_ops], version : '1.0.0', install : true, ) diff --git a/radeon/meson.build b/radeon/meson.build index a4171b41..b08c7442 100644 --- a/radeon/meson.build +++ b/radeon/meson.build @@ -31,7 +31,7 @@ libdrm_radeon = shared_library( c_args : warn_c_args, include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : [dep_pthread_stubs], + dependencies : [dep_pthread_stubs, dep_atomic_ops], version : '1.0.1', install : true, ) diff --git a/tegra/meson.build b/tegra/meson.build index 7c671cd5..1f5c74b3 100644 --- a/tegra/meson.build +++ b/tegra/meson.build @@ -23,7 +23,7 @@ libdrm_tegra = shared_library( [files('tegra.c'), config_file], include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : [dep_pthread_stubs], + dependencies : [dep_pthread_stubs, dep_atomic_ops], c_args : warn_c_args, version : '0.0.0', install : true, -- cgit v1.2.3-54-g00ecf From 0663dbd3efc7e6d644662c903722d1fc4a199cfa Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Mon, 12 Mar 2018 10:10:51 -0700 Subject: meson: don't use compiler.has_header Meson's compiler.has_header is completely useless, it only checks that a header exists, not whether it's usable. This creates problems if a header contains a conditional #error declaration, like so: > #if __x86_64__ > # error "Doesn't work with x86_64!" > #endif Compiler.has_header will return true in this case, even when compiling for x86_64. This is useless. Instead, we'll do a compile check so that any #error declarations will be treated as errors, and compilation will work. Fixes compilation on x32 architecture. Gentoo Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=649746 meson bug: https://github.com/mesonbuild/meson/issues/2246 CC: Matt Turner Signed-off-by: Dylan Baker Reviewed-by: Eric Engestrom --- meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index df6f2bd2..a0c79e30 100644 --- a/meson.build +++ b/meson.build @@ -186,10 +186,10 @@ else dep_rt = [] endif dep_m = cc.find_library('m', required : false) -if cc.has_header('sys/sysctl.h') +if cc.compiles('#include ', name : 'sys/sysctl.h works') config.set10('HAVE_SYS_SYSCTL_H', true) endif -if cc.has_header('sys/select.h') +if cc.compiles('#include ', name : 'sys/select.h works') config.set10('HAVE_SYS_SELECT_H', true) endif if cc.has_header_symbol('sys/sysmacros.h', 'major') -- cgit v1.2.3-54-g00ecf From 2bd461e32a5fd50169704786ba975324ddc11cb2 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Mon, 12 Mar 2018 16:17:55 +0000 Subject: meson: make it easy to add headers to check Signed-off-by: Eric Engestrom Reviewed-by: Dylan Baker --- meson.build | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/meson.build b/meson.build index a0c79e30..b85f1d7a 100644 --- a/meson.build +++ b/meson.build @@ -186,12 +186,11 @@ else dep_rt = [] endif dep_m = cc.find_library('m', required : false) -if cc.compiles('#include ', name : 'sys/sysctl.h works') - config.set10('HAVE_SYS_SYSCTL_H', true) -endif -if cc.compiles('#include ', name : 'sys/select.h works') - config.set10('HAVE_SYS_SELECT_H', true) -endif +foreach header : ['sys/sysctl.h', 'sys/select.h'] + if cc.compiles('#include <@0@>'.format(header), name : '@0@ works'.format(header)) + config.set10('HAVE_' + header.underscorify().to_upper(), true) + endif +endforeach if cc.has_header_symbol('sys/sysmacros.h', 'major') config.set10('MAJOR_IN_SYSMACROS', true) elif cc.has_header_symbol('sys/mkdev.h', 'major') -- cgit v1.2.3-54-g00ecf From a58490de0d8ae5c290d2db6e59fc44edc829d9c6 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 13 Mar 2018 14:31:29 +0000 Subject: meson: detect alloca.h amdgpu makes use of it Signed-off-by: Eric Engestrom Reviewed-by: Dylan Baker --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index b85f1d7a..2a6c4680 100644 --- a/meson.build +++ b/meson.build @@ -186,7 +186,7 @@ else dep_rt = [] endif dep_m = cc.find_library('m', required : false) -foreach header : ['sys/sysctl.h', 'sys/select.h'] +foreach header : ['sys/sysctl.h', 'sys/select.h', 'alloca.h'] if cc.compiles('#include <@0@>'.format(header), name : '@0@ works'.format(header)) config.set10('HAVE_' + header.underscorify().to_upper(), true) endif -- cgit v1.2.3-54-g00ecf From dff690ac3128300577d7cd7e4f086004c4114ab6 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Wed, 14 Mar 2018 14:48:37 +0900 Subject: tests/exynos: remove dead condition There is already condition checking input values between 2 and 4096 so condition checking 0 is always false. Remove the dead condition. Signed-off-by: Seung-Woo Kim Reviewed-by: Eric Engestrom --- tests/exynos/exynos_fimg2d_perf.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/tests/exynos/exynos_fimg2d_perf.c b/tests/exynos/exynos_fimg2d_perf.c index a2d5c192..97691a71 100644 --- a/tests/exynos/exynos_fimg2d_perf.c +++ b/tests/exynos/exynos_fimg2d_perf.c @@ -274,13 +274,6 @@ int main(int argc, char **argv) goto out; } - if (bufw == 0 || bufh == 0) { - fprintf(stderr, "error: buffer width/height should be non-zero.\n"); - ret = -1; - - goto out; - } - fd = drmOpen("exynos", NULL); if (fd < 0) { fprintf(stderr, "error: failed to open drm\n"); -- cgit v1.2.3-54-g00ecf From ed07718ae7bab596297abf210bb0c37c6dba58ed Mon Sep 17 00:00:00 2001 From: John Stultz Date: Wed, 14 Mar 2018 09:47:36 -0700 Subject: libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64 When building AOSP after updating libdrm project to the freedesktop/master branch, I've seen the following build errors: external/libdrm/intel/Android.mk: error: libdrm_intel (SHARED_LIBRARIES android-arm64) missing libpciaccess (SHARED_LIBRARIES android-arm64) You can set ALLOW_MISSING_DEPENDENCIES=true in your environment if this is intentional, but that may defer real problems until later in the build. Using ALLOW_MISSING_DEPENDENCIES=true when building allows things to function properly, but is not ideal. So basically, while I'm not including the libdrm_intel package into the build, just the fact that the Android.mk file references libpciaccess which isn't a repo included in AOSP causes the build failure. So it seems we need some sort of conditional filter in the Android.mk to skip over it if we're not building for intel. Cc: Chad Versace Cc: Marissa Wall Cc: Sean Paul Cc: Dan Willemsen Cc: Tomasz Figa Cc: Robert Foss Reviewed-by: Emil Velikov Signed-off-by: John Stultz Signed-off-by: Rob Herring --- intel/Android.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/intel/Android.mk b/intel/Android.mk index 5407ff3e..3f9db785 100644 --- a/intel/Android.mk +++ b/intel/Android.mk @@ -21,6 +21,7 @@ # IN THE SOFTWARE. # +ifeq ($(TARGET_ARCH),$(filter $(TARGET_ARCH),x86 x86_64)) LOCAL_PATH := $(call my-dir) include $(CLEAR_VARS) @@ -37,3 +38,4 @@ LOCAL_SHARED_LIBRARIES := \ include $(LIBDRM_COMMON_MK) include $(BUILD_SHARED_LIBRARY) +endif -- cgit v1.2.3-54-g00ecf From 32e0370e36e8263b1e7dfb75f76934dbfce53e9c Mon Sep 17 00:00:00 2001 From: Inki Dae Date: Tue, 20 Mar 2018 12:47:33 +0900 Subject: tests: fix memory leak issue Fixed memory leak issue to drmModeRes and drmModePlaneRes objects. These objects were allocated by drmModeGetResources and drmModeGetPlaneResources functions but not freed properly. So this patch frees them by calling drmModeFreeResources drmModeFreePlaneResources functions at failure case. Signed-off-by: Inki Dae Reviewed-by: Eric Engestrom --- tests/kms/libkms-test-device.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tests/kms/libkms-test-device.c b/tests/kms/libkms-test-device.c index 53c7349b..042ae05d 100644 --- a/tests/kms/libkms-test-device.c +++ b/tests/kms/libkms-test-device.c @@ -67,7 +67,7 @@ static void kms_device_probe_screens(struct kms_device *device) device->screens = calloc(res->count_connectors, sizeof(screen)); if (!device->screens) - return; + goto err_free_resources; for (i = 0; i < res->count_connectors; i++) { unsigned int *count; @@ -97,6 +97,7 @@ static void kms_device_probe_screens(struct kms_device *device) device->num_screens++; } +err_free_resources: drmModeFreeResources(res); } @@ -112,7 +113,7 @@ static void kms_device_probe_crtcs(struct kms_device *device) device->crtcs = calloc(res->count_crtcs, sizeof(crtc)); if (!device->crtcs) - return; + goto err_free_resources; for (i = 0; i < res->count_crtcs; i++) { crtc = kms_crtc_create(device, res->crtcs[i]); @@ -123,6 +124,7 @@ static void kms_device_probe_crtcs(struct kms_device *device) device->num_crtcs++; } +err_free_resources: drmModeFreeResources(res); } @@ -138,7 +140,7 @@ static void kms_device_probe_planes(struct kms_device *device) device->planes = calloc(res->count_planes, sizeof(plane)); if (!device->planes) - return; + goto err_free_resources; for (i = 0; i < res->count_planes; i++) { plane = kms_plane_create(device, res->planes[i]); @@ -149,6 +151,7 @@ static void kms_device_probe_planes(struct kms_device *device) device->num_planes++; } +err_free_resources: drmModeFreePlaneResources(res); } -- cgit v1.2.3-54-g00ecf From 1a44bbae734fa6aa227d2ac621ff7884af1ae8ef Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 26 Jan 2018 17:04:28 +0000 Subject: meson,configure: always define HAVE_OPEN_MEMSTREAM Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 4 +++- intel/test_decode.c | 4 ++-- meson.build | 4 +--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configure.ac b/configure.ac index ec5003f6..762ca9f9 100644 --- a/configure.ac +++ b/configure.ac @@ -189,7 +189,9 @@ AC_CHECK_FUNCS([clock_gettime], [CLOCK_LIB=], [AC_MSG_ERROR([Couldn't find clock_gettime])])]) AC_SUBST([CLOCK_LIB]) -AC_CHECK_FUNCS([open_memstream], [HAVE_OPEN_MEMSTREAM=yes]) +AC_CHECK_FUNCS([open_memstream], + [AC_DEFINE([HAVE_OPEN_MEMSTREAM], 1, [Have open_memstream()])], + [AC_DEFINE([HAVE_OPEN_MEMSTREAM], 0)]) dnl Use lots of warning flags with with gcc and compatible compilers diff --git a/intel/test_decode.c b/intel/test_decode.c index b4eddcd1..68f777b0 100644 --- a/intel/test_decode.c +++ b/intel/test_decode.c @@ -91,7 +91,7 @@ compare_batch(struct drm_intel_decode *ctx, const char *batch_filename) { FILE *out = NULL; void *ptr, *ref_ptr, *batch_ptr; -#ifdef HAVE_OPEN_MEMSTREAM +#if HAVE_OPEN_MEMSTREAM size_t size; #endif size_t ref_size, batch_size; @@ -109,7 +109,7 @@ compare_batch(struct drm_intel_decode *ctx, const char *batch_filename) * figure out how to output to a file in a safe and sane way * inside of an automake project's test infrastructure. */ -#ifdef HAVE_OPEN_MEMSTREAM +#if HAVE_OPEN_MEMSTREAM out = open_memstream((char **)&ptr, &size); #else fprintf(stderr, "platform lacks open_memstream, skipping.\n"); diff --git a/meson.build b/meson.build index 2a6c4680..50daa1d0 100644 --- a/meson.build +++ b/meson.build @@ -196,9 +196,7 @@ if cc.has_header_symbol('sys/sysmacros.h', 'major') elif cc.has_header_symbol('sys/mkdev.h', 'major') config.set10('MAJOR_IN_MKDEV', true) endif -if cc.has_function('open_memstream') - config.set10('HAVE_OPEN_MEMSTREAM', true) -endif +config.set10('HAVE_OPEN_MEMSTREAM', cc.has_function('open_memstream')) warn_c_args = [] foreach a : ['-Wall', '-Wextra', '-Wsign-compare', '-Werror=undef', -- cgit v1.2.3-54-g00ecf From e8d3d885b1362caba4f1e1dfa42d45bac7163124 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 16 Mar 2018 17:07:08 +0000 Subject: meson,configure: always define HAVE_VISIBILITY Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 ++ libdrm_macros.h | 2 +- meson.build | 7 +++---- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/configure.ac b/configure.ac index 762ca9f9..607d8597 100644 --- a/configure.ac +++ b/configure.ac @@ -535,6 +535,8 @@ AC_LINK_IFELSE([AC_LANG_PROGRAM([ if test "x$HAVE_ATTRIBUTE_VISIBILITY" = xyes; then AC_DEFINE(HAVE_VISIBILITY, 1, [Compiler supports __attribute__(("hidden"))]) +else + AC_DEFINE(HAVE_VISIBILITY, 0) fi AC_SUBST(WARN_CFLAGS) diff --git a/libdrm_macros.h b/libdrm_macros.h index 639d0904..211fab21 100644 --- a/libdrm_macros.h +++ b/libdrm_macros.h @@ -23,7 +23,7 @@ #ifndef LIBDRM_LIBDRM_H #define LIBDRM_LIBDRM_H -#if defined(HAVE_VISIBILITY) +#if HAVE_VISIBILITY # define drm_private __attribute__((visibility("hidden"))) #else # define drm_private diff --git a/meson.build b/meson.build index 50daa1d0..826cd915 100644 --- a/meson.build +++ b/meson.build @@ -256,10 +256,9 @@ with_man_pages = with_man_pages != 'false' and prog_xslt.found() and prog_sed.fo # Used for tets prog_bash = find_program('bash') -if cc.compiles('''int foo_hidden(void) __attribute__((visibility(("hidden"))));''', - name : 'compiler supports __attribute__(("hidden"))') - config.set10('HAVE_VISIBILITY', true) -endif +config.set10('HAVE_VISIBILITY', + cc.compiles('''int foo_hidden(void) __attribute__((visibility(("hidden"))));''', + name : 'compiler supports __attribute__(("hidden"))')) foreach t : [ [with_exynos, 'EXYNOS'], -- cgit v1.2.3-54-g00ecf From 07585200e937a528bd9fad3d5850de68823f27fa Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 16 Mar 2018 17:04:50 +0000 Subject: meson,configure: always define UDEV Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- configure.ac | 2 ++ meson.build | 2 +- xf86drm.c | 8 ++++---- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/configure.ac b/configure.ac index 607d8597..0e36336c 100644 --- a/configure.ac +++ b/configure.ac @@ -347,6 +347,8 @@ AC_SUBST(PCIACCESS_LIBS) if test "x$UDEV" = xyes; then AC_DEFINE(UDEV, 1, [Have UDEV support]) +else + AC_DEFINE(UDEV, 0) fi AC_CANONICAL_HOST diff --git a/meson.build b/meson.build index 826cd915..b90127aa 100644 --- a/meson.build +++ b/meson.build @@ -165,9 +165,9 @@ if _libkms != 'false' with_libkms = _libkms == 'true' or ['linux', 'freebsd', 'dragonfly'].contains(host_machine.system()) endif +config.set10('UDEV', with_udev) if with_udev dep_udev = dependency('udev') - config.set10('UDEV', true) else dep_udev = [] endif diff --git a/xf86drm.c b/xf86drm.c index 344326db..9328bf5a 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -293,7 +293,7 @@ static int drmMatchBusID(const char *id1, const char *id2, int pci_domain_ok) * If any other failure happened then it will output error mesage using * drmMsg() call. */ -#if !defined(UDEV) +#if !UDEV static int chown_check_return(const char *path, uid_t owner, gid_t group) { int rv; @@ -332,7 +332,7 @@ static int drmOpenDevice(dev_t dev, int minor, int type) int fd; mode_t devmode = DRM_DEV_MODE, serv_mode; gid_t serv_group; -#if !defined(UDEV) +#if !UDEV int isroot = !geteuid(); uid_t user = DRM_DEV_UID; gid_t group = DRM_DEV_GID; @@ -361,7 +361,7 @@ static int drmOpenDevice(dev_t dev, int minor, int type) devmode &= ~(S_IXUSR|S_IXGRP|S_IXOTH); } -#if !defined(UDEV) +#if !UDEV if (stat(DRM_DIR_NAME, &st)) { if (!isroot) return DRM_ERR_NOT_ROOT; @@ -414,7 +414,7 @@ wait_for_udev: if (fd >= 0) return fd; -#if !defined(UDEV) +#if !UDEV /* Check if the device node is not what we expect it to be, and recreate it * and try again if so. */ -- cgit v1.2.3-54-g00ecf From 431f1a147e33b3fae7ea78a47d40a6014b682ebd Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Fri, 16 Mar 2018 17:10:26 +0000 Subject: meson: replace `if(compiles) have=true` with `have=compiles` Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov Reviewed-by: Dylan Baker --- meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index b90127aa..100a59fa 100644 --- a/meson.build +++ b/meson.build @@ -187,9 +187,8 @@ else endif dep_m = cc.find_library('m', required : false) foreach header : ['sys/sysctl.h', 'sys/select.h', 'alloca.h'] - if cc.compiles('#include <@0@>'.format(header), name : '@0@ works'.format(header)) - config.set10('HAVE_' + header.underscorify().to_upper(), true) - endif + config.set('HAVE_' + header.underscorify().to_upper(), + cc.compiles('#include <@0@>'.format(header), name : '@0@ works'.format(header))) endforeach if cc.has_header_symbol('sys/sysmacros.h', 'major') config.set10('MAJOR_IN_SYSMACROS', true) -- cgit v1.2.3-54-g00ecf From 0926f0af54d654b1a95826066edcae30b8052581 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Thu, 1 Feb 2018 11:12:05 +0000 Subject: meson,configure: include config.h automatically This will prevent any more missing `#include "config.h"` bug, at the cost of having to recompile some files that didn't need to be when changing build options. Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- amdgpu/amdgpu_asic_id.c | 4 ---- amdgpu/amdgpu_bo.c | 4 ---- amdgpu/amdgpu_cs.c | 4 ---- amdgpu/amdgpu_device.c | 4 ---- amdgpu/amdgpu_gpu_info.c | 4 ---- amdgpu/amdgpu_internal.h | 4 ---- amdgpu/amdgpu_vamgr.c | 4 ---- amdgpu/amdgpu_vm.c | 4 ---- amdgpu/util_hash.c | 4 ---- amdgpu/util_hash.h | 4 ---- amdgpu/util_hash_table.c | 4 ---- amdgpu/util_hash_table.h | 4 ---- configure.ac | 2 ++ etnaviv/etnaviv_bo.c | 4 ---- etnaviv/etnaviv_bo_cache.c | 4 ---- etnaviv/etnaviv_cmd_stream.c | 4 ---- etnaviv/etnaviv_device.c | 4 ---- etnaviv/etnaviv_gpu.c | 4 ---- etnaviv/etnaviv_perfmon.c | 4 ---- etnaviv/etnaviv_pipe.c | 4 ---- exynos/exynos_drm.c | 4 ---- exynos/exynos_fimg2d.c | 4 ---- freedreno/freedreno_bo.c | 4 ---- freedreno/freedreno_bo_cache.c | 4 ---- freedreno/freedreno_device.c | 4 ---- freedreno/freedreno_pipe.c | 4 ---- freedreno/freedreno_priv.h | 4 ---- freedreno/freedreno_ringbuffer.c | 4 ---- freedreno/kgsl/kgsl_bo.c | 4 ---- freedreno/kgsl/kgsl_device.c | 4 ---- freedreno/kgsl/kgsl_pipe.c | 4 ---- freedreno/kgsl/kgsl_ringbuffer.c | 4 ---- freedreno/msm/msm_bo.c | 4 ---- freedreno/msm/msm_device.c | 4 ---- freedreno/msm/msm_pipe.c | 4 ---- freedreno/msm/msm_ringbuffer.c | 4 ---- intel/intel_bufmgr.c | 4 ---- intel/intel_bufmgr_fake.c | 4 ---- intel/intel_bufmgr_gem.c | 4 ---- intel/intel_decode.c | 4 ---- intel/mm.c | 4 ---- intel/mm.h | 4 ---- intel/test_decode.c | 4 ---- libkms/api.c | 4 ---- libkms/dumb.c | 4 ---- libkms/exynos.c | 4 ---- libkms/intel.c | 4 ---- libkms/internal.h | 4 ---- libkms/linux.c | 4 ---- libkms/nouveau.c | 4 ---- libkms/radeon.c | 4 ---- libkms/vmwgfx.c | 4 ---- meson.build | 2 +- nouveau/abi16.c | 4 ---- nouveau/bufctx.c | 4 ---- nouveau/nouveau.c | 4 ---- nouveau/pushbuf.c | 4 ---- omap/omap_drm.c | 4 ---- radeon/radeon_bo.c | 3 --- radeon/radeon_bo_gem.c | 3 --- radeon/radeon_cs.c | 3 --- radeon/radeon_cs_gem.c | 3 --- radeon/radeon_cs_space.c | 3 --- radeon/radeon_surface.c | 3 --- tegra/tegra.c | 4 ---- tests/amdgpu/amdgpu_test.c | 4 ---- tests/amdgpu/basic_tests.c | 4 ---- tests/amdgpu/bo_tests.c | 4 ---- tests/amdgpu/cs_tests.c | 4 ---- tests/amdgpu/deadlock_tests.c | 4 ---- tests/amdgpu/uvd_enc_tests.c | 4 ---- tests/amdgpu/vce_tests.c | 4 ---- tests/amdgpu/vcn_tests.c | 4 ---- tests/amdgpu/vm_tests.c | 4 ---- tests/etnaviv/etnaviv_2d_test.c | 4 ---- tests/etnaviv/etnaviv_bo_cache_test.c | 4 ---- tests/exynos/exynos_fimg2d_test.c | 4 ---- tests/kms/kms-steal-crtc.c | 4 ---- tests/kms/kms-universal-planes.c | 4 ---- tests/kms/libkms-test-crtc.c | 4 ---- tests/kms/libkms-test-device.c | 4 ---- tests/kms/libkms-test-framebuffer.c | 4 ---- tests/kms/libkms-test-plane.c | 4 ---- tests/kms/libkms-test-screen.c | 4 ---- tests/modetest/buffers.c | 4 ---- tests/modetest/cursor.c | 4 ---- tests/modetest/modetest.c | 4 ---- tests/nouveau/threaded.c | 4 ---- tests/tegra/openclose.c | 4 ---- tests/util/format.c | 4 ---- tests/util/kms.c | 4 ---- tests/util/pattern.c | 4 ---- tests/vbltest/vbltest.c | 4 ---- xf86atomic.h | 4 ---- xf86drm.c | 3 --- xf86drmMode.c | 4 ---- 96 files changed, 3 insertions(+), 370 deletions(-) diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c index 62459c09..a5007ffc 100644 --- a/amdgpu/amdgpu_asic_id.c +++ b/amdgpu/amdgpu_asic_id.c @@ -22,10 +22,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 3853fd03..cb255cb0 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -22,10 +22,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 4ac9bac7..3c9be6c2 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index fb2cfb57..d81efcf8 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -28,10 +28,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index 1efffc6f..b68e1c4f 100644 --- a/amdgpu/amdgpu_gpu_info.c +++ b/amdgpu/amdgpu_gpu_info.c @@ -22,10 +22,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index aeb5d651..99b8ce0b 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -25,10 +25,6 @@ #ifndef _AMDGPU_INTERNAL_H_ #define _AMDGPU_INTERNAL_H_ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index ac1202de..1de9f952 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/amdgpu/amdgpu_vm.c b/amdgpu/amdgpu_vm.c index 5ba7c082..da9d07f8 100644 --- a/amdgpu/amdgpu_vm.c +++ b/amdgpu/amdgpu_vm.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "amdgpu.h" #include "amdgpu_drm.h" #include "xf86drm.h" diff --git a/amdgpu/util_hash.c b/amdgpu/util_hash.c index 87cb671b..7e590419 100644 --- a/amdgpu/util_hash.c +++ b/amdgpu/util_hash.c @@ -30,10 +30,6 @@ * Zack Rusin */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "util_hash.h" #include diff --git a/amdgpu/util_hash.h b/amdgpu/util_hash.h index 01a4779b..6eed1569 100644 --- a/amdgpu/util_hash.h +++ b/amdgpu/util_hash.h @@ -44,10 +44,6 @@ #ifndef UTIL_HASH_H #define UTIL_HASH_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include "libdrm_macros.h" diff --git a/amdgpu/util_hash_table.c b/amdgpu/util_hash_table.c index fa7f6eab..89a8bf9b 100644 --- a/amdgpu/util_hash_table.c +++ b/amdgpu/util_hash_table.c @@ -38,10 +38,6 @@ */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "util_hash_table.h" #include "util_hash.h" diff --git a/amdgpu/util_hash_table.h b/amdgpu/util_hash_table.h index e0001289..5e295a81 100644 --- a/amdgpu/util_hash_table.h +++ b/amdgpu/util_hash_table.h @@ -34,10 +34,6 @@ #ifndef U_HASH_TABLE_H_ #define U_HASH_TABLE_H_ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "libdrm_macros.h" /** diff --git a/configure.ac b/configure.ac index 0e36336c..619af497 100644 --- a/configure.ac +++ b/configure.ac @@ -541,6 +541,8 @@ else AC_DEFINE(HAVE_VISIBILITY, 0) fi +CFLAGS="$CFLAGS -include config.h" + AC_SUBST(WARN_CFLAGS) AC_CONFIG_FILES([ Makefile diff --git a/etnaviv/etnaviv_bo.c b/etnaviv/etnaviv_bo.c index 78b9cd27..32f7b348 100644 --- a/etnaviv/etnaviv_bo.c +++ b/etnaviv/etnaviv_bo.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "etnaviv_priv.h" #include "etnaviv_drmif.h" diff --git a/etnaviv/etnaviv_bo_cache.c b/etnaviv/etnaviv_bo_cache.c index 6208230d..c81de262 100644 --- a/etnaviv/etnaviv_bo_cache.c +++ b/etnaviv/etnaviv_bo_cache.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "etnaviv_priv.h" #include "etnaviv_drmif.h" diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c index e8c58cd5..13730168 100644 --- a/etnaviv/etnaviv_cmd_stream.c +++ b/etnaviv/etnaviv_cmd_stream.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include "etnaviv_drmif.h" diff --git a/etnaviv/etnaviv_device.c b/etnaviv/etnaviv_device.c index 3ce92030..d83e8d3e 100644 --- a/etnaviv/etnaviv_device.c +++ b/etnaviv/etnaviv_device.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/etnaviv/etnaviv_gpu.c b/etnaviv/etnaviv_gpu.c index bc355e8f..f7efa028 100644 --- a/etnaviv/etnaviv_gpu.c +++ b/etnaviv/etnaviv_gpu.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "etnaviv_priv.h" #include "etnaviv_drmif.h" diff --git a/etnaviv/etnaviv_perfmon.c b/etnaviv/etnaviv_perfmon.c index aa5130a6..5f408a7b 100644 --- a/etnaviv/etnaviv_perfmon.c +++ b/etnaviv/etnaviv_perfmon.c @@ -25,10 +25,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "etnaviv_priv.h" static int etna_perfmon_query_signals(struct etna_perfmon *pm, struct etna_perfmon_domain *dom) diff --git a/etnaviv/etnaviv_pipe.c b/etnaviv/etnaviv_pipe.c index 94c5d377..53954aa3 100644 --- a/etnaviv/etnaviv_pipe.c +++ b/etnaviv/etnaviv_pipe.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "etnaviv_priv.h" int etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms) diff --git a/exynos/exynos_drm.c b/exynos/exynos_drm.c index f6204f1c..e1afef65 100644 --- a/exynos/exynos_drm.c +++ b/exynos/exynos_drm.c @@ -24,10 +24,6 @@ * Inki Dae */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c index 5658a48e..bca884b9 100644 --- a/exynos/exynos_fimg2d.c +++ b/exynos/exynos_fimg2d.c @@ -23,10 +23,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index 331b8227..34c285fb 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "freedreno_drmif.h" #include "freedreno_priv.h" diff --git a/freedreno/freedreno_bo_cache.c b/freedreno/freedreno_bo_cache.c index d922f3a9..3b737159 100644 --- a/freedreno/freedreno_bo_cache.c +++ b/freedreno/freedreno_bo_cache.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "freedreno_drmif.h" #include "freedreno_priv.h" diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c index a0334bf4..0b42561a 100644 --- a/freedreno/freedreno_device.c +++ b/freedreno/freedreno_device.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include #include diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c index 1540474b..77b160e7 100644 --- a/freedreno/freedreno_pipe.c +++ b/freedreno/freedreno_pipe.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "freedreno_drmif.h" #include "freedreno_priv.h" diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index a0957fad..6c9e509f 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -29,10 +29,6 @@ #ifndef FREEDRENO_PRIV_H_ #define FREEDRENO_PRIV_H_ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/freedreno/freedreno_ringbuffer.c b/freedreno/freedreno_ringbuffer.c index 7310f1fd..3834b51b 100644 --- a/freedreno/freedreno_ringbuffer.c +++ b/freedreno/freedreno_ringbuffer.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include "freedreno_drmif.h" diff --git a/freedreno/kgsl/kgsl_bo.c b/freedreno/kgsl/kgsl_bo.c index ab3485e3..c6d2d499 100644 --- a/freedreno/kgsl/kgsl_bo.c +++ b/freedreno/kgsl/kgsl_bo.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "kgsl_priv.h" #include diff --git a/freedreno/kgsl/kgsl_device.c b/freedreno/kgsl/kgsl_device.c index 958e8a72..914f3412 100644 --- a/freedreno/kgsl/kgsl_device.c +++ b/freedreno/kgsl/kgsl_device.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include #include diff --git a/freedreno/kgsl/kgsl_pipe.c b/freedreno/kgsl/kgsl_pipe.c index 80bd1313..0a8b6586 100644 --- a/freedreno/kgsl/kgsl_pipe.c +++ b/freedreno/kgsl/kgsl_pipe.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "kgsl_priv.h" diff --git a/freedreno/kgsl/kgsl_ringbuffer.c b/freedreno/kgsl/kgsl_ringbuffer.c index f09c433b..a756deda 100644 --- a/freedreno/kgsl/kgsl_ringbuffer.c +++ b/freedreno/kgsl/kgsl_ringbuffer.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include "freedreno_ringbuffer.h" diff --git a/freedreno/msm/msm_bo.c b/freedreno/msm/msm_bo.c index 281c5aa7..8b3d0bcb 100644 --- a/freedreno/msm/msm_bo.c +++ b/freedreno/msm/msm_bo.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "msm_priv.h" static int bo_allocate(struct msm_bo *msm_bo) diff --git a/freedreno/msm/msm_device.c b/freedreno/msm/msm_device.c index c454938d..7bb57677 100644 --- a/freedreno/msm/msm_device.c +++ b/freedreno/msm/msm_device.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include #include diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c index 12e4be59..f28778ef 100644 --- a/freedreno/msm/msm_pipe.c +++ b/freedreno/msm/msm_pipe.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include "msm_priv.h" static int query_param(struct fd_pipe *pipe, uint32_t param, diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index c75bb169..a87e1b9a 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include diff --git a/intel/intel_bufmgr.c b/intel/intel_bufmgr.c index a2853400..bede0a21 100644 --- a/intel/intel_bufmgr.c +++ b/intel/intel_bufmgr.c @@ -25,10 +25,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c index 641df6a1..3b24b81b 100644 --- a/intel/intel_bufmgr_fake.c +++ b/intel/intel_bufmgr_fake.c @@ -34,10 +34,6 @@ * the bugs in the old texture manager. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 386da30e..5c47a46f 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -34,10 +34,6 @@ * Dave Airlie */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 3a81500f..bc7b04b8 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/intel/mm.c b/intel/mm.c index 954e9dcb..79d8719d 100644 --- a/intel/mm.c +++ b/intel/mm.c @@ -22,10 +22,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/intel/mm.h b/intel/mm.h index 8d83743f..1b0f84fc 100644 --- a/intel/mm.h +++ b/intel/mm.h @@ -29,10 +29,6 @@ #ifndef MM_H #define MM_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "libdrm_macros.h" struct mem_block { diff --git a/intel/test_decode.c b/intel/test_decode.c index 68f777b0..b9f5b927 100644 --- a/intel/test_decode.c +++ b/intel/test_decode.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/libkms/api.c b/libkms/api.c index 354d8a2e..22dd32d7 100644 --- a/libkms/api.c +++ b/libkms/api.c @@ -26,10 +26,6 @@ **************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/libkms/dumb.c b/libkms/dumb.c index b95a072c..17efc10a 100644 --- a/libkms/dumb.c +++ b/libkms/dumb.c @@ -26,10 +26,6 @@ **************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/libkms/exynos.c b/libkms/exynos.c index c20b6b05..ef64a668 100644 --- a/libkms/exynos.c +++ b/libkms/exynos.c @@ -25,10 +25,6 @@ * SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/libkms/intel.c b/libkms/intel.c index 3d8ca055..859e7a0f 100644 --- a/libkms/intel.c +++ b/libkms/intel.c @@ -26,10 +26,6 @@ **************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/libkms/internal.h b/libkms/internal.h index 905f5b17..8b386db6 100644 --- a/libkms/internal.h +++ b/libkms/internal.h @@ -29,10 +29,6 @@ #ifndef INTERNAL_H_ #define INTERNAL_H_ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "libdrm_macros.h" #include "libkms.h" diff --git a/libkms/linux.c b/libkms/linux.c index 1431eb10..56205054 100644 --- a/libkms/linux.c +++ b/libkms/linux.c @@ -29,10 +29,6 @@ * going from fd to pci id via fstat and udev. */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif #include #include #include diff --git a/libkms/nouveau.c b/libkms/nouveau.c index d10e0fdb..7fe23db3 100644 --- a/libkms/nouveau.c +++ b/libkms/nouveau.c @@ -26,10 +26,6 @@ **************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/libkms/radeon.c b/libkms/radeon.c index aaeeaf31..2cb2b11f 100644 --- a/libkms/radeon.c +++ b/libkms/radeon.c @@ -26,10 +26,6 @@ **************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/libkms/vmwgfx.c b/libkms/vmwgfx.c index 6a24fd4d..f0e40be7 100644 --- a/libkms/vmwgfx.c +++ b/libkms/vmwgfx.c @@ -26,10 +26,6 @@ **************************************************************************/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/meson.build b/meson.build index 100a59fa..74a541e8 100644 --- a/meson.build +++ b/meson.build @@ -280,7 +280,7 @@ config_file = configure_file( configuration : config, output : 'config.h', ) -add_project_arguments('-DHAVE_CONFIG_H', language : 'c') +add_project_arguments('-include', 'config.h', language : 'c') inc_root = include_directories('.') inc_drm = include_directories('include/drm') diff --git a/nouveau/abi16.c b/nouveau/abi16.c index ee38c0cb..ba2501ea 100644 --- a/nouveau/abi16.c +++ b/nouveau/abi16.c @@ -22,10 +22,6 @@ * Authors: Ben Skeggs */ -#ifdef HAVE_CONFIG_H -# include -#endif - #include #include #include diff --git a/nouveau/bufctx.c b/nouveau/bufctx.c index 4f76e5df..67b7570e 100644 --- a/nouveau/bufctx.c +++ b/nouveau/bufctx.c @@ -22,10 +22,6 @@ * Authors: Ben Skeggs */ -#ifdef HAVE_CONFIG_H -#include -#endif - #include #include #include diff --git a/nouveau/nouveau.c b/nouveau/nouveau.c index e113a8fe..55593517 100644 --- a/nouveau/nouveau.c +++ b/nouveau/nouveau.c @@ -22,10 +22,6 @@ * Authors: Ben Skeggs */ -#ifdef HAVE_CONFIG_H -#include -#endif - #include #include #include diff --git a/nouveau/pushbuf.c b/nouveau/pushbuf.c index 035e3019..445c966e 100644 --- a/nouveau/pushbuf.c +++ b/nouveau/pushbuf.c @@ -22,10 +22,6 @@ * Authors: Ben Skeggs */ -#ifdef HAVE_CONFIG_H -#include -#endif - #include #include #include diff --git a/omap/omap_drm.c b/omap/omap_drm.c index 08ba64eb..417d522c 100644 --- a/omap/omap_drm.c +++ b/omap/omap_drm.c @@ -26,10 +26,6 @@ * Rob Clark */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/radeon/radeon_bo.c b/radeon/radeon_bo.c index 447f9280..821807bc 100644 --- a/radeon/radeon_bo.c +++ b/radeon/radeon_bo.c @@ -29,9 +29,6 @@ * Dave Airlie * Jérôme Glisse */ -#ifdef HAVE_CONFIG_H -#include -#endif #include #include #include diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c index fbd453d9..774b26e4 100644 --- a/radeon/radeon_bo_gem.c +++ b/radeon/radeon_bo_gem.c @@ -29,9 +29,6 @@ * Dave Airlie * Jérôme Glisse */ -#ifdef HAVE_CONFIG_H -#include -#endif #include #include #include diff --git a/radeon/radeon_cs.c b/radeon/radeon_cs.c index dffb869f..eb7859e5 100644 --- a/radeon/radeon_cs.c +++ b/radeon/radeon_cs.c @@ -1,6 +1,3 @@ -#ifdef HAVE_CONFIG_H -#include -#endif #include "libdrm_macros.h" #include #include "radeon_cs.h" diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c index f3dccb6c..4d5fc13a 100644 --- a/radeon/radeon_cs_gem.c +++ b/radeon/radeon_cs_gem.c @@ -29,9 +29,6 @@ * Nicolai Haehnle * Jérôme Glisse */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif #include #include #include diff --git a/radeon/radeon_cs_space.c b/radeon/radeon_cs_space.c index 69287be5..8531c345 100644 --- a/radeon/radeon_cs_space.c +++ b/radeon/radeon_cs_space.c @@ -25,9 +25,6 @@ */ /* */ -#ifdef HAVE_CONFIG_H -#include -#endif #include #include #include diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 04df77d6..3cafcfcb 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -26,9 +26,6 @@ * Authors: * Jérôme Glisse */ -#ifdef HAVE_CONFIG_H -#include -#endif #include #include #include diff --git a/tegra/tegra.c b/tegra/tegra.c index f7dc89ad..1d7268e5 100644 --- a/tegra/tegra.c +++ b/tegra/tegra.c @@ -22,10 +22,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -# include "config.h" -#endif - #include #include #include diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index e49f4a6c..96fcd687 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 0ea010a8..1adbddd9 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c index 24698bcb..9d4da4af 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include "CUnit/Basic.h" diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c index a5361cd5..7ad0f0dc 100644 --- a/tests/amdgpu/cs_tests.c +++ b/tests/amdgpu/cs_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include "CUnit/Basic.h" diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index 96c99c96..1eb5761a 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c index 0377c1a5..b4251bcf 100644 --- a/tests/amdgpu/uvd_enc_tests.c +++ b/tests/amdgpu/uvd_enc_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c index 75821bbb..25c0b1fb 100644 --- a/tests/amdgpu/vce_tests.c +++ b/tests/amdgpu/vce_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c index 2eb8c434..d9f05af8 100644 --- a/tests/amdgpu/vcn_tests.c +++ b/tests/amdgpu/vcn_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c index 502a9405..7b6dc5d6 100644 --- a/tests/amdgpu/vm_tests.c +++ b/tests/amdgpu/vm_tests.c @@ -21,10 +21,6 @@ * */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "CUnit/Basic.h" #include "amdgpu_test.h" diff --git a/tests/etnaviv/etnaviv_2d_test.c b/tests/etnaviv/etnaviv_2d_test.c index 10751c73..8dd77b66 100644 --- a/tests/etnaviv/etnaviv_2d_test.c +++ b/tests/etnaviv/etnaviv_2d_test.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include "config.h" -#endif - #include #include #include diff --git a/tests/etnaviv/etnaviv_bo_cache_test.c b/tests/etnaviv/etnaviv_bo_cache_test.c index fb01f8d3..7fb06293 100644 --- a/tests/etnaviv/etnaviv_bo_cache_test.c +++ b/tests/etnaviv/etnaviv_bo_cache_test.c @@ -24,10 +24,6 @@ * Christian Gmeiner */ -#ifdef HAVE_CONFIG_H -# include "config.h" -#endif - #undef NDEBUG #include diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index dcb2e35a..99bb9233 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -23,10 +23,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/kms/kms-steal-crtc.c b/tests/kms/kms-steal-crtc.c index 4b830d27..cd40758d 100644 --- a/tests/kms/kms-steal-crtc.c +++ b/tests/kms/kms-steal-crtc.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/kms/kms-universal-planes.c b/tests/kms/kms-universal-planes.c index 89057bb5..2163c987 100644 --- a/tests/kms/kms-universal-planes.c +++ b/tests/kms/kms-universal-planes.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/kms/libkms-test-crtc.c b/tests/kms/libkms-test-crtc.c index 3adb4903..2c28face 100644 --- a/tests/kms/libkms-test-crtc.c +++ b/tests/kms/libkms-test-crtc.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include "libkms-test.h" struct kms_crtc *kms_crtc_create(struct kms_device *device, uint32_t id) diff --git a/tests/kms/libkms-test-device.c b/tests/kms/libkms-test-device.c index 042ae05d..d3bb11ce 100644 --- a/tests/kms/libkms-test-device.c +++ b/tests/kms/libkms-test-device.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/kms/libkms-test-framebuffer.c b/tests/kms/libkms-test-framebuffer.c index c9e5ad3c..9bb2d95b 100644 --- a/tests/kms/libkms-test-framebuffer.c +++ b/tests/kms/libkms-test-framebuffer.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/tests/kms/libkms-test-plane.c b/tests/kms/libkms-test-plane.c index 8eb78af1..6c40a3c9 100644 --- a/tests/kms/libkms-test-plane.c +++ b/tests/kms/libkms-test-plane.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/tests/kms/libkms-test-screen.c b/tests/kms/libkms-test-screen.c index 33690222..bbe972a0 100644 --- a/tests/kms/libkms-test-screen.c +++ b/tests/kms/libkms-test-screen.c @@ -21,10 +21,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c index 4fd310b9..9b635c0c 100644 --- a/tests/modetest/buffers.c +++ b/tests/modetest/buffers.c @@ -24,10 +24,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/modetest/cursor.c b/tests/modetest/cursor.c index 6de82a4a..829bced1 100644 --- a/tests/modetest/cursor.c +++ b/tests/modetest/cursor.c @@ -22,10 +22,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index fb9f15fc..62957d84 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -38,10 +38,6 @@ * the mode has been programmed, along with possible test patterns. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/nouveau/threaded.c b/tests/nouveau/threaded.c index 281af460..3669bcd3 100644 --- a/tests/nouveau/threaded.c +++ b/tests/nouveau/threaded.c @@ -20,10 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -# include "config.h" -#endif - #include #include #include diff --git a/tests/tegra/openclose.c b/tests/tegra/openclose.c index 881d8aa4..f80f52d4 100644 --- a/tests/tegra/openclose.c +++ b/tests/tegra/openclose.c @@ -20,10 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -# include "config.h" -#endif - #include #include #include diff --git a/tests/util/format.c b/tests/util/format.c index 043cfe7f..15ac5e1e 100644 --- a/tests/util/format.c +++ b/tests/util/format.c @@ -23,10 +23,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/util/kms.c b/tests/util/kms.c index 028cc8d9..8b3e7878 100644 --- a/tests/util/kms.c +++ b/tests/util/kms.c @@ -37,10 +37,6 @@ * the mode has been programmed, along with possible test patterns. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/util/pattern.c b/tests/util/pattern.c index 75a458d4..9fa0a417 100644 --- a/tests/util/pattern.c +++ b/tests/util/pattern.c @@ -23,10 +23,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c index 3f6b803a..48708d20 100644 --- a/tests/vbltest/vbltest.c +++ b/tests/vbltest/vbltest.c @@ -24,10 +24,6 @@ * IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include diff --git a/xf86atomic.h b/xf86atomic.h index 70e91866..2d733bd5 100644 --- a/xf86atomic.h +++ b/xf86atomic.h @@ -34,10 +34,6 @@ #ifndef LIBDRM_ATOMICS_H #define LIBDRM_ATOMICS_H -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #if HAVE_LIBDRM_ATOMIC_PRIMITIVES #define HAS_ATOMIC_OPS 1 diff --git a/xf86drm.c b/xf86drm.c index 9328bf5a..689e8fe9 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -31,9 +31,6 @@ * DEALINGS IN THE SOFTWARE. */ -#ifdef HAVE_CONFIG_H -# include -#endif #include #include #include diff --git a/xf86drmMode.c b/xf86drmMode.c index bd59ef25..cf8e1eac 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -38,10 +38,6 @@ * platforms find which headers to include to get uint32_t */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - #include #include #include -- cgit v1.2.3-54-g00ecf From 56f6d3d48d405024802fa1e52a80f8918fba7fc5 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 20 Mar 2018 14:55:50 +0000 Subject: meson: drop unneeded dependency to libudev libdrm only needed libudev for a few days 3 years ago, between fde4969176822fe54197 and its revert 5b0e76f143887c4ec7db. Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- meson.build | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/meson.build b/meson.build index 74a541e8..ade90be1 100644 --- a/meson.build +++ b/meson.build @@ -166,12 +166,6 @@ if _libkms != 'false' endif config.set10('UDEV', with_udev) -if with_udev - dep_udev = dependency('udev') -else - dep_udev = [] -endif - # Among others FreeBSD does not have a separate dl library. if not cc.has_function('dlsym') dep_dl = cc.find_library('dl', required : with_nouveau) @@ -294,7 +288,7 @@ libdrm = shared_library( config_file, ], c_args : warn_c_args, - dependencies : [dep_udev, dep_valgrind, dep_rt, dep_m], + dependencies : [dep_valgrind, dep_rt, dep_m], include_directories : inc_drm, version : '2.4.0', install : true, -- cgit v1.2.3-54-g00ecf From edaca475e8b21da95ffee11b7287bc976ad31d49 Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 20 Mar 2018 14:54:45 +0000 Subject: meson: move line to allow using `config` earlier Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index ade90be1..ddcd25ff 100644 --- a/meson.build +++ b/meson.build @@ -29,12 +29,12 @@ project( pkg = import('pkgconfig') +config = configuration_data() + with_udev = get_option('udev') with_freedreno_kgsl = get_option('freedreno-kgsl') with_install_tests = get_option('install-test-programs') -config = configuration_data() - if ['freebsd', 'dragonfly', 'netbsd'].contains(host_machine.system()) dep_pthread_stubs = dependency('pthread-stubs', version : '>= 0.4') else -- cgit v1.2.3-54-g00ecf From 361d4bffd322f2743f8b5ce4a81ed0482105afac Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Tue, 20 Mar 2018 14:59:40 +0000 Subject: meson: drop unnecessary variable Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- meson.build | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/meson.build b/meson.build index ddcd25ff..961ee59c 100644 --- a/meson.build +++ b/meson.build @@ -31,7 +31,7 @@ pkg = import('pkgconfig') config = configuration_data() -with_udev = get_option('udev') +config.set10('UDEV', get_option('udev')) with_freedreno_kgsl = get_option('freedreno-kgsl') with_install_tests = get_option('install-test-programs') @@ -165,7 +165,6 @@ if _libkms != 'false' with_libkms = _libkms == 'true' or ['linux', 'freebsd', 'dragonfly'].contains(host_machine.system()) endif -config.set10('UDEV', with_udev) # Among others FreeBSD does not have a separate dl library. if not cc.has_function('dlsym') dep_dl = cc.find_library('dl', required : with_nouveau) -- cgit v1.2.3-54-g00ecf From b81d44d587d1706d5c7568e539340632a748782b Mon Sep 17 00:00:00 2001 From: Satyajit Date: Mon, 26 Feb 2018 18:07:03 +0530 Subject: libdrm: amdgpu: Adding DRM_RDWR flag in amdgpu_bo_export Currently while exporting prime handle to fd read write access is not granted. mmap fails because of this. mmap was not supported on prime initially. Here is link to related discussion https://lists.freedesktop.org/archives/dri-devel/2017-February/131840.html Adding the DRM_RDWR flag in amdgpu_bo_export to support mmap. Signed-off-by: Satyajit Acked-by: Christian König --- amdgpu/amdgpu_bo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index cb255cb0..9e37b149 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -246,8 +246,9 @@ int amdgpu_bo_export(amdgpu_bo_handle bo, case amdgpu_bo_handle_type_dma_buf_fd: amdgpu_add_handle_to_table(bo); - return drmPrimeHandleToFD(bo->dev->fd, bo->handle, DRM_CLOEXEC, - (int*)shared_handle); + return drmPrimeHandleToFD(bo->dev->fd, bo->handle, + DRM_CLOEXEC | DRM_RDWR, + (int*)shared_handle); } return -EINVAL; } -- cgit v1.2.3-54-g00ecf From d930ef82b2fe32d793e78ce536567ead7cc973d7 Mon Sep 17 00:00:00 2001 From: Gowtham Tammana Date: Wed, 28 Feb 2018 12:54:51 -0600 Subject: omap: add Android build support Add Android.mk file to build libdrm_omap library. Signed-off-by: Gowtham Tammana Signed-off-by: Andrew F. Davis --- omap/Android.mk | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 omap/Android.mk diff --git a/omap/Android.mk b/omap/Android.mk new file mode 100644 index 00000000..b25cca13 --- /dev/null +++ b/omap/Android.mk @@ -0,0 +1,13 @@ +LOCAL_PATH := $(call my-dir) +include $(CLEAR_VARS) + +LOCAL_MODULE := libdrm_omap +LOCAL_VENDOR_MODULE := true + +LOCAL_SRC_FILES := omap_drm.c + +LOCAL_SHARED_LIBRARIES := libdrm + +include $(LIBDRM_COMMON_MK) + +include $(BUILD_SHARED_LIBRARY) -- cgit v1.2.3-54-g00ecf From 32ee9c0e0566ee6642c3df02315a2595105c0c87 Mon Sep 17 00:00:00 2001 From: Stefan Schake Date: Sun, 18 Mar 2018 02:26:59 +0100 Subject: android: Add missing include exports They were set for the static library but not the shared variant. Signed-off-by: Stefan Schake Acked-by: John Stultz Reviewed-by: Emil Velikov --- Android.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Android.mk b/Android.mk index 8611c5e3..1b77c538 100644 --- a/Android.mk +++ b/Android.mk @@ -53,7 +53,9 @@ LOCAL_MODULE := libdrm LOCAL_SRC_FILES := $(LIBDRM_FILES) LOCAL_EXPORT_C_INCLUDE_DIRS := \ - $(LOCAL_PATH)/include/drm + $(LOCAL_PATH) \ + $(LOCAL_PATH)/include/drm \ + $(LOCAL_PATH)/android LOCAL_SHARED_LIBRARIES := \ libcutils -- cgit v1.2.3-54-g00ecf From bb45ce4e3ac751315bfd7fbfd9e1425bf515ec0d Mon Sep 17 00:00:00 2001 From: John Stultz Date: Tue, 20 Mar 2018 17:48:23 +0000 Subject: libdrm: Use readdir instead of readdir_r to avoid build warnings Building libdrm under AOSP, we see the following build warning: external/libdrm/xf86drm.c:2861:12: warning: 'readdir_r' is deprecated: readdir_r is deprecated; use readdir instead [-Wdeprecated-declarations] while (readdir_r(sysdir, pent, &ent) == 0 && ent != NULL) { ^ Building on Linux with glibc produces the same warning. Thus, this patch replaces readdir_r with readdir. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102031 Cc: Robert Foss Cc: Rob Herring Cc: Stefan Schake Cc: John Stultz Signed-off-by: John Stultz Reviewed-by: Emil Velikov [Emil Velikov: remove unused variables, Eric] Signed-off-by: Emil Velikov Reviewed-by: Eric Engestrom --- xf86drm.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) diff --git a/xf86drm.c b/xf86drm.c index 689e8fe9..3a9d0ed2 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -2819,12 +2819,11 @@ static char *drmGetMinorNameForFD(int fd, int type) { #ifdef __linux__ DIR *sysdir; - struct dirent *pent, *ent; + struct dirent *ent; struct stat sbuf; const char *name = drmGetMinorName(type); int len; char dev_name[64], buf[64]; - long name_max; int maj, min; if (!name) @@ -2847,30 +2846,16 @@ static char *drmGetMinorNameForFD(int fd, int type) if (!sysdir) return NULL; - name_max = fpathconf(dirfd(sysdir), _PC_NAME_MAX); - if (name_max == -1) - goto out_close_dir; - - pent = malloc(offsetof(struct dirent, d_name) + name_max + 1); - if (pent == NULL) - goto out_close_dir; - - while (readdir_r(sysdir, pent, &ent) == 0 && ent != NULL) { + while ((ent = readdir(sysdir))) { if (strncmp(ent->d_name, name, len) == 0) { snprintf(dev_name, sizeof(dev_name), DRM_DIR_NAME "/%s", ent->d_name); - free(pent); closedir(sysdir); - return strdup(dev_name); } } - - free(pent); - -out_close_dir: - closedir(sysdir); + return NULL; #else struct stat sbuf; char buf[PATH_MAX + 1]; @@ -2911,7 +2896,6 @@ out_close_dir: return strdup(buf); #endif - return NULL; } char *drmGetPrimaryDeviceNameFromFd(int fd) -- cgit v1.2.3-54-g00ecf From 00aa37443f32ff22e439093bc4039c21c74d0d2e Mon Sep 17 00:00:00 2001 From: Eric Engestrom Date: Thu, 22 Mar 2018 17:08:37 +0000 Subject: xf86drmMode: merge successive mutually-exclusive #ifs Signed-off-by: Eric Engestrom Reviewed-by: Frank Binns Reviewed-by: Emil Velikov --- xf86drmMode.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xf86drmMode.c b/xf86drmMode.c index cf8e1eac..9a15b5e7 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -827,8 +827,7 @@ int drmCheckModesettingSupported(const char *busid) } #elif defined(__DragonFly__) return 0; -#endif -#ifdef __OpenBSD__ +#elif defined(__OpenBSD__) int fd; struct drm_mode_card_res res; drmModeResPtr r = 0; -- cgit v1.2.3-54-g00ecf From bb0fd5f3b30141e2049a31f9ccd3f806645b21e0 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 14 Dec 2015 19:46:34 +0900 Subject: intel: Do not use libpciaccess on Android This patch makes the code not rely anymore on libpciaccess when compiled for Android to eliminate ioperm() and iopl() syscalls required by that library. As a side effect, the mappable aperture size is hardcoded to 64 MiB on Android, however nothing seems to rely on this value anyway, as checked be grepping relevant code in drm_gralloc and Mesa. Cc: Rob Herring Signed-off-by: Tomasz Figa [Emil Velikov: rebase against master. add missing __func__, Eric] Signed-off-by: Emil Velikov Acked-by: John Stultz --- intel/Android.mk | 3 +-- intel/intel_bufmgr.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/intel/Android.mk b/intel/Android.mk index 3f9db785..dd881688 100644 --- a/intel/Android.mk +++ b/intel/Android.mk @@ -33,8 +33,7 @@ LOCAL_MODULE := libdrm_intel LOCAL_SRC_FILES := $(LIBDRM_INTEL_FILES) LOCAL_SHARED_LIBRARIES := \ - libdrm \ - libpciaccess + libdrm include $(LIBDRM_COMMON_MK) include $(BUILD_SHARED_LIBRARY) diff --git a/intel/intel_bufmgr.c b/intel/intel_bufmgr.c index bede0a21..192de093 100644 --- a/intel/intel_bufmgr.c +++ b/intel/intel_bufmgr.c @@ -32,7 +32,9 @@ #include #include #include +#ifndef __ANDROID__ #include +#endif #include "libdrm_macros.h" #include "intel_bufmgr.h" #include "intel_bufmgr_priv.h" @@ -322,6 +324,7 @@ drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id) return -1; } +#ifndef __ANDROID__ static size_t drm_intel_probe_agp_aperture_size(int fd) { @@ -347,6 +350,15 @@ err: pci_system_cleanup (); return size; } +#else +static size_t +drm_intel_probe_agp_aperture_size(int fd) +{ + /* Nothing seems to rely on this value on Android anyway... */ + fprintf(stderr, "%s: Mappable aperture size hardcoded to 64MiB\n", __func__); + return 64 * 1024 * 1024; +} +#endif int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total) -- cgit v1.2.3-54-g00ecf From 4dfa458979c345ea5eb46749f545d78c09e3f244 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Tue, 20 Mar 2018 17:32:37 +0000 Subject: Revert "libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64" This reverts commit ed07718ae7bab596297abf210bb0c37c6dba58ed. The commit added a guard since libpciaccess may be missing on some setups. As of last commit there are no traces of the project, from Android POV. Hence, we can revert this workaround - which caused similar breakage to the one it's trying to fix. This time in Mesa. Cc: Rob Herring Acked-by: John Stultz --- intel/Android.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/intel/Android.mk b/intel/Android.mk index dd881688..f45312dd 100644 --- a/intel/Android.mk +++ b/intel/Android.mk @@ -21,7 +21,6 @@ # IN THE SOFTWARE. # -ifeq ($(TARGET_ARCH),$(filter $(TARGET_ARCH),x86 x86_64)) LOCAL_PATH := $(call my-dir) include $(CLEAR_VARS) @@ -37,4 +36,3 @@ LOCAL_SHARED_LIBRARIES := \ include $(LIBDRM_COMMON_MK) include $(BUILD_SHARED_LIBRARY) -endif -- cgit v1.2.3-54-g00ecf From 2fa58c77fb9e563219f8ec647b9ddf52f3390ed2 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Tue, 20 Mar 2018 14:08:09 +0800 Subject: headers: sync up amdgpu_drm.h with drm-next Add sensor_info type AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK Reviewed-by: Evan Quan Signed-off-by: Rex Zhu --- include/drm/amdgpu_drm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index a023b476..f784f248 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -656,6 +656,10 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_SENSOR_VDDNB 0x6 /* Subquery id: Query graphics voltage */ #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 + /* Subquery id: Query GPU stable pstate shader clock */ + #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 + /* Subquery id: Query GPU stable pstate memory clock */ + #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 /* Number of VRAM page faults on CPU access. */ #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F -- cgit v1.2.3-54-g00ecf From 8e535dd2142433b24aebc6eddeaee04663489aa2 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 30 Mar 2018 13:04:30 +0100 Subject: headers: Sync with drm-next Taken from the drm-next pull for 4.17-rc1 (694f54f680f7), and manually reconciled: core: - Dropped DRM_MODE_TYPE_ALL and DRM_MODE_FLAG_ALL; these are purely internal details of the bits accepted by the currently running kernel, and can not be generally relied on by userspace - Add HDCP flags - Note CTM entry representation is sign-magnitude format, not two's-complement amdgpu: - Add QUERY_STATE2 context op - Add VCN firmware version query etnaviv: - Add more GPU feature flags i915: - Add caps, params and ioctls for PMU / perf-stream - Add support for explicit fencing nouveau: - Add TILE_COMP layout vc4: - Add perfmon ioctls virtgpu: - Add capset-fix param vmware: - Add handle-close ioctl and explicit-fencing support Signed-off-by: Daniel Stone Reviewed-by: Alex Deucher --- etnaviv/etnaviv_drm.h | 7 + include/drm/amdgpu_drm.h | 11 ++ include/drm/drm_mode.h | 25 ++-- include/drm/i915_drm.h | 321 ++++++++++++++++++++++++++++++++++++++++++++-- include/drm/nouveau_drm.h | 1 + include/drm/vc4_drm.h | 76 +++++++++++ include/drm/virtgpu_drm.h | 1 + include/drm/vmwgfx_drm.h | 35 ++++- 8 files changed, 451 insertions(+), 26 deletions(-) diff --git a/etnaviv/etnaviv_drm.h b/etnaviv/etnaviv_drm.h index 110cc73b..0d5c49dc 100644 --- a/etnaviv/etnaviv_drm.h +++ b/etnaviv/etnaviv_drm.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright (C) 2015 Etnaviv Project * @@ -54,6 +55,12 @@ struct drm_etnaviv_timespec { #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 #define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 #define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 +#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a +#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b +#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c +#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d +#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e +#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index f784f248..c363b67f 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -160,6 +160,7 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_OP_ALLOC_CTX 1 #define AMDGPU_CTX_OP_FREE_CTX 2 #define AMDGPU_CTX_OP_QUERY_STATE 3 +#define AMDGPU_CTX_OP_QUERY_STATE2 4 /* GPU reset status */ #define AMDGPU_CTX_NO_RESET 0 @@ -170,6 +171,13 @@ union drm_amdgpu_bo_list { /* unknown cause */ #define AMDGPU_CTX_UNKNOWN_RESET 3 +/* indicate gpu reset occured after ctx created */ +#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) +/* indicate vram lost occured after ctx created */ +#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) +/* indicate some job from this context once cause gpu hang */ +#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) + /* Context priority level */ #define AMDGPU_CTX_PRIORITY_UNSET -2048 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 @@ -610,6 +618,8 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_FW_SOS 0x0c /* Subquery id: Query PSP ASD firmware version */ #define AMDGPU_INFO_FW_ASD 0x0d + /* Subquery id: Query VCN firmware version */ + #define AMDGPU_INFO_FW_VCN 0x0e /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f /* the used VRAM size */ @@ -798,6 +808,7 @@ struct drm_amdgpu_info_firmware { #define AMDGPU_VRAM_TYPE_GDDR5 5 #define AMDGPU_VRAM_TYPE_HBM 6 #define AMDGPU_VRAM_TYPE_DDR3 7 +#define AMDGPU_VRAM_TYPE_DDR4 8 struct drm_amdgpu_info_device { /** PCI Device ID */ diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index 5597a871..5f9fadbd 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -38,11 +38,11 @@ extern "C" { #define DRM_DISPLAY_MODE_LEN 32 #define DRM_PROP_NAME_LEN 32 -#define DRM_MODE_TYPE_BUILTIN (1<<0) -#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_BUILTIN (1<<0) /* deprecated */ +#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ +#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ #define DRM_MODE_TYPE_PREFERRED (1<<3) -#define DRM_MODE_TYPE_DEFAULT (1<<4) +#define DRM_MODE_TYPE_DEFAULT (1<<4) /* deprecated */ #define DRM_MODE_TYPE_USERDEF (1<<5) #define DRM_MODE_TYPE_DRIVER (1<<6) @@ -66,8 +66,8 @@ extern "C" { #define DRM_MODE_FLAG_PCSYNC (1<<7) #define DRM_MODE_FLAG_NCSYNC (1<<8) #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) -#define DRM_MODE_FLAG_PIXMUX (1<<11) +#define DRM_MODE_FLAG_BCAST (1<<10) /* deprecated */ +#define DRM_MODE_FLAG_PIXMUX (1<<11) /* deprecated */ #define DRM_MODE_FLAG_DBLCLK (1<<12) #define DRM_MODE_FLAG_CLKDIV2 (1<<13) /* @@ -173,6 +173,10 @@ extern "C" { DRM_MODE_REFLECT_X | \ DRM_MODE_REFLECT_Y) +/* Content Protection Flags */ +#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0 +#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1 +#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2 struct drm_mode_modeinfo { __u32 clock; @@ -341,7 +345,7 @@ struct drm_mode_get_connector { __u32 pad; }; -#define DRM_MODE_PROP_PENDING (1<<0) +#define DRM_MODE_PROP_PENDING (1<<0) /* deprecated, do not use */ #define DRM_MODE_PROP_RANGE (1<<1) #define DRM_MODE_PROP_IMMUTABLE (1<<2) #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ @@ -576,8 +580,11 @@ struct drm_mode_crtc_lut { }; struct drm_color_ctm { - /* Conversion matrix in S31.32 format. */ - __s64 matrix[9]; + /* + * Conversion matrix in S31.32 sign-magnitude + * (not two's complement!) format. + */ + __u64 matrix[9]; }; struct drm_color_lut { diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 5ebe0462..16e452aa 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -86,6 +86,62 @@ enum i915_mocs_table_index { I915_MOCS_CACHED, }; +/* + * Different engines serve different roles, and there may be more than one + * engine serving each role. enum drm_i915_gem_engine_class provides a + * classification of the role of the engine, which may be used when requesting + * operations to be performed on a certain subset of engines, or for providing + * information about that group. + */ +enum drm_i915_gem_engine_class { + I915_ENGINE_CLASS_RENDER = 0, + I915_ENGINE_CLASS_COPY = 1, + I915_ENGINE_CLASS_VIDEO = 2, + I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, + + I915_ENGINE_CLASS_INVALID = -1 +}; + +/** + * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 + * + */ + +enum drm_i915_pmu_engine_sample { + I915_SAMPLE_BUSY = 0, + I915_SAMPLE_WAIT = 1, + I915_SAMPLE_SEMA = 2 +}; + +#define I915_PMU_SAMPLE_BITS (4) +#define I915_PMU_SAMPLE_MASK (0xf) +#define I915_PMU_SAMPLE_INSTANCE_BITS (8) +#define I915_PMU_CLASS_SHIFT \ + (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) + +#define __I915_PMU_ENGINE(class, instance, sample) \ + ((class) << I915_PMU_CLASS_SHIFT | \ + (instance) << I915_PMU_SAMPLE_BITS | \ + (sample)) + +#define I915_PMU_ENGINE_BUSY(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) + +#define I915_PMU_ENGINE_WAIT(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) + +#define I915_PMU_ENGINE_SEMA(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) + +#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) + +#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) +#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) +#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) +#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) + +#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY + /* Each region is a minimum of 16k, and there are at most 255 of them. */ #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use @@ -260,6 +316,9 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 #define DRM_I915_PERF_OPEN 0x36 +#define DRM_I915_PERF_ADD_CONFIG 0x37 +#define DRM_I915_PERF_REMOVE_CONFIG 0x38 +#define DRM_I915_QUERY 0x39 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -315,6 +374,9 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) +#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) +#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) +#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -393,10 +455,20 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_MIN_EU_IN_POOL 39 #define I915_PARAM_MMAP_GTT_VERSION 40 -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution +/* + * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution * priorities and the driver will attempt to execute batches in priority order. + * The param returns a capability bitmask, nonzero implies that the scheduler + * is enabled, with different features present according to the mask. + * + * The initial priority for each batch is supplied by the context and is + * controlled via I915_CONTEXT_PARAM_PRIORITY. */ #define I915_PARAM_HAS_SCHEDULER 41 +#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) +#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) +#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) + #define I915_PARAM_HUC_STATUS 42 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of @@ -412,6 +484,51 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_HAS_EXEC_FENCE 44 +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture + * user specified bufffers for post-mortem debugging of GPU hangs. See + * EXEC_OBJECT_CAPTURE. + */ +#define I915_PARAM_HAS_EXEC_CAPTURE 45 + +#define I915_PARAM_SLICE_MASK 46 + +/* Assuming it's uniform for each slice, this queries the mask of subslices + * per-slice for this system. + */ +#define I915_PARAM_SUBSLICE_MASK 47 + +/* + * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer + * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. + */ +#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 + +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of + * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. + */ +#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 + +/* + * Query whether every context (both per-file default and user created) is + * isolated (insofar as HW supports). If this parameter is not true, then + * freshly created contexts may inherit values from an existing context, + * rather than default HW values. If true, it also ensures (insofar as HW + * supports) that all state set by this context will not leak to any other + * context. + * + * As not every engine across every gen support contexts, the returned + * value reports the support of context isolation for individual engines by + * returning a bitmask of each engine class set to true if that class supports + * isolation. + */ +#define I915_PARAM_HAS_CONTEXT_ISOLATION 50 + +/* Frequency of the command streamer timestamps given by the *_TIMESTAMP + * registers. This used to be fixed per platform but from CNL onwards, this + * might vary depending on the parts. + */ +#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 + typedef struct drm_i915_getparam { __s32 param; /* @@ -666,6 +783,8 @@ struct drm_i915_gem_relocation_entry { #define I915_GEM_DOMAIN_VERTEX 0x00000020 /** GTT domain - aperture and scanout */ #define I915_GEM_DOMAIN_GTT 0x00000040 +/** WC domain - uncached access */ +#define I915_GEM_DOMAIN_WC 0x00000080 /** @} */ struct drm_i915_gem_exec_object { @@ -773,8 +892,15 @@ struct drm_i915_gem_exec_object2 { * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. */ #define EXEC_OBJECT_ASYNC (1<<6) +/* Request that the contents of this execobject be copied into the error + * state upon a GPU hang involving this batch for post-mortem debugging. + * These buffers are recorded in no particular order as "user" in + * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see + * if the kernel supports this flag. + */ +#define EXEC_OBJECT_CAPTURE (1<<7) /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ -#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1) +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) __u64 flags; union { @@ -784,6 +910,18 @@ struct drm_i915_gem_exec_object2 { __u64 rsvd2; }; +struct drm_i915_gem_exec_fence { + /** + * User's handle for a drm_syncobj to wait on or signal. + */ + __u32 handle; + +#define I915_EXEC_FENCE_WAIT (1<<0) +#define I915_EXEC_FENCE_SIGNAL (1<<1) +#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) + __u32 flags; +}; + struct drm_i915_gem_execbuffer2 { /** * List of gem_exec_object2 structs @@ -798,7 +936,11 @@ struct drm_i915_gem_execbuffer2 { __u32 DR1; __u32 DR4; __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ + /** + * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY + * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a + * struct drm_i915_gem_exec_fence *fences. + */ __u64 cliprects_ptr; #define I915_EXEC_RING_MASK (7<<0) #define I915_EXEC_DEFAULT (0<<0) @@ -889,7 +1031,24 @@ struct drm_i915_gem_execbuffer2 { */ #define I915_EXEC_FENCE_OUT (1<<17) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1)) +/* + * Traditionally the execbuf ioctl has only considered the final element in + * the execobject[] to be the executable batch. Often though, the client + * will known the batch object prior to construction and being able to place + * it into the execobject[] array first can simplify the relocation tracking. + * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the + * execobject[] as the * batch instead (the default is to use the last + * element). + */ +#define I915_EXEC_BATCH_FIRST (1<<18) + +/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr + * define an array of i915_gem_exec_fence structures which specify a set of + * dma fences to wait upon or signal. + */ +#define I915_EXEC_FENCE_ARRAY (1<<19) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ @@ -1201,7 +1360,9 @@ struct drm_intel_overlay_attrs { * active on a given plane. */ -#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ +#define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set + * flags==0 to disable colorkeying. + */ #define I915_SET_COLORKEY_DESTINATION (1<<1) #define I915_SET_COLORKEY_SOURCE (1<<2) struct drm_intel_sprite_colorkey { @@ -1239,14 +1400,16 @@ struct drm_i915_reg_read { * be specified */ __u64 offset; +#define I915_REG_READ_8B_WA (1ul << 0) + __u64 val; /* Return value */ }; /* Known registers: * * Render engine timestamp - 0x2358 + 64bit - gen7+ * - Note this register returns an invalid value if using the default - * single instruction 8byte read, in order to workaround that use - * offset (0x2538 | 1) instead. + * single instruction 8byte read, in order to workaround that pass + * flag I915_REG_READ_8B_WA in offset field. * */ @@ -1289,17 +1452,26 @@ struct drm_i915_gem_context_param { #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 #define I915_CONTEXT_PARAM_BANNABLE 0x5 +#define I915_CONTEXT_PARAM_PRIORITY 0x6 +#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ +#define I915_CONTEXT_DEFAULT_PRIORITY 0 +#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ __u64 value; }; enum drm_i915_oa_format { - I915_OA_FORMAT_A13 = 1, - I915_OA_FORMAT_A29, - I915_OA_FORMAT_A13_B8_C8, - I915_OA_FORMAT_B4_C8, - I915_OA_FORMAT_A45_B8_C8, - I915_OA_FORMAT_B4_C8_A16, - I915_OA_FORMAT_C4_B8, + I915_OA_FORMAT_A13 = 1, /* HSW only */ + I915_OA_FORMAT_A29, /* HSW only */ + I915_OA_FORMAT_A13_B8_C8, /* HSW only */ + I915_OA_FORMAT_B4_C8, /* HSW only */ + I915_OA_FORMAT_A45_B8_C8, /* HSW only */ + I915_OA_FORMAT_B4_C8_A16, /* HSW only */ + I915_OA_FORMAT_C4_B8, /* HSW+ */ + + /* Gen8+ */ + I915_OA_FORMAT_A12, + I915_OA_FORMAT_A12_B8_C8, + I915_OA_FORMAT_A32u40_A4u32_B8_C8, I915_OA_FORMAT_MAX /* non-ABI */ }; @@ -1424,6 +1596,127 @@ enum drm_i915_perf_record_type { DRM_I915_PERF_RECORD_MAX /* non-ABI */ }; +/** + * Structure to upload perf dynamic configuration into the kernel. + */ +struct drm_i915_perf_oa_config { + /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ + char uuid[36]; + + __u32 n_mux_regs; + __u32 n_boolean_regs; + __u32 n_flex_regs; + + /* + * These fields are pointers to tuples of u32 values (register address, + * value). For example the expected length of the buffer pointed by + * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). + */ + __u64 mux_regs_ptr; + __u64 boolean_regs_ptr; + __u64 flex_regs_ptr; +}; + +struct drm_i915_query_item { + __u64 query_id; +#define DRM_I915_QUERY_TOPOLOGY_INFO 1 + + /* + * When set to zero by userspace, this is filled with the size of the + * data to be written at the data_ptr pointer. The kernel sets this + * value to a negative value to signal an error on a particular query + * item. + */ + __s32 length; + + /* + * Unused for now. Must be cleared to zero. + */ + __u32 flags; + + /* + * Data will be written at the location pointed by data_ptr when the + * value of length matches the length of the data to be written by the + * kernel. + */ + __u64 data_ptr; +}; + +struct drm_i915_query { + __u32 num_items; + + /* + * Unused for now. Must be cleared to zero. + */ + __u32 flags; + + /* + * This points to an array of num_items drm_i915_query_item structures. + */ + __u64 items_ptr; +}; + +/* + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : + * + * data: contains the 3 pieces of information : + * + * - the slice mask with one bit per slice telling whether a slice is + * available. The availability of slice X can be queried with the following + * formula : + * + * (data[X / 8] >> (X % 8)) & 1 + * + * - the subslice mask for each slice with one bit per subslice telling + * whether a subslice is available. The availability of subslice Y in slice + * X can be queried with the following formula : + * + * (data[subslice_offset + + * X * subslice_stride + + * Y / 8] >> (Y % 8)) & 1 + * + * - the EU mask for each subslice in each slice with one bit per EU telling + * whether an EU is available. The availability of EU Z in subslice Y in + * slice X can be queried with the following formula : + * + * (data[eu_offset + + * (X * max_subslices + Y) * eu_stride + + * Z / 8] >> (Z % 8)) & 1 + */ +struct drm_i915_query_topology_info { + /* + * Unused for now. Must be cleared to zero. + */ + __u16 flags; + + __u16 max_slices; + __u16 max_subslices; + __u16 max_eus_per_subslice; + + /* + * Offset in data[] at which the subslice masks are stored. + */ + __u16 subslice_offset; + + /* + * Stride at which each of the subslice masks for each slice are + * stored. + */ + __u16 subslice_stride; + + /* + * Offset in data[] at which the EU masks are stored. + */ + __u16 eu_offset; + + /* + * Stride at which each of the EU masks for each subslice are stored. + */ + __u16 eu_stride; + + __u8 data[]; +}; + #if defined(__cplusplus) } #endif diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h index cb077821..d42105c8 100644 --- a/include/drm/nouveau_drm.h +++ b/include/drm/nouveau_drm.h @@ -104,6 +104,7 @@ struct drm_nouveau_setparam { #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) +#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h index 3415a4b7..4117117b 100644 --- a/include/drm/vc4_drm.h +++ b/include/drm/vc4_drm.h @@ -42,6 +42,9 @@ extern "C" { #define DRM_VC4_GET_TILING 0x09 #define DRM_VC4_LABEL_BO 0x0a #define DRM_VC4_GEM_MADVISE 0x0b +#define DRM_VC4_PERFMON_CREATE 0x0c +#define DRM_VC4_PERFMON_DESTROY 0x0d +#define DRM_VC4_PERFMON_GET_VALUES 0x0e #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) @@ -55,6 +58,9 @@ extern "C" { #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) +#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) +#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) +#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) struct drm_vc4_submit_rcl_surface { __u32 hindex; /* Handle index, or ~0 if not present. */ @@ -173,6 +179,15 @@ struct drm_vc4_submit_cl { * wait ioctl). */ __u64 seqno; + + /* ID of the perfmon to attach to this job. 0 means no perfmon. */ + __u32 perfmonid; + + /* Unused field to align this struct on 64 bits. Must be set to 0. + * If one ever needs to add an u32 field to this struct, this field + * can be used. + */ + __u32 pad2; }; /** @@ -308,6 +323,7 @@ struct drm_vc4_get_hang_state { #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 +#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 struct drm_vc4_get_param { __u32 param; @@ -352,6 +368,66 @@ struct drm_vc4_gem_madvise { __u32 pad; }; +enum { + VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, + VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, + VC4_PERFCNT_FEP_CLIPPED_QUADS, + VC4_PERFCNT_FEP_VALID_QUADS, + VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, + VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, + VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, + VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, + VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, + VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, + VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, + VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, + VC4_PERFCNT_PSE_PRIMS_REVERSED, + VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, + VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, + VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, + VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, + VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, + VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, + VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, + VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, + VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, + VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, + VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, + VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, + VC4_PERFCNT_NUM_EVENTS, +}; + +#define DRM_VC4_MAX_PERF_COUNTERS 16 + +struct drm_vc4_perfmon_create { + __u32 id; + __u32 ncounters; + __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; +}; + +struct drm_vc4_perfmon_destroy { + __u32 id; +}; + +/* + * Returns the values of the performance counters tracked by this + * perfmon (as an array of ncounters u64 values). + * + * No implicit synchronization is performed, so the user has to + * guarantee that any jobs using this perfmon have already been + * completed (probably by blocking on the seqno returned by the + * last exec that used the perfmon). + */ +struct drm_vc4_perfmon_get_values { + __u32 id; + __u64 values_ptr; +}; + #if defined(__cplusplus) } #endif diff --git a/include/drm/virtgpu_drm.h b/include/drm/virtgpu_drm.h index 91a31ffe..9a781f06 100644 --- a/include/drm/virtgpu_drm.h +++ b/include/drm/virtgpu_drm.h @@ -63,6 +63,7 @@ struct drm_virtgpu_execbuffer { }; #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ +#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ struct drm_virtgpu_getparam { __u64 param; diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h index d325a410..0bc784f5 100644 --- a/include/drm/vmwgfx_drm.h +++ b/include/drm/vmwgfx_drm.h @@ -41,6 +41,7 @@ extern "C" { #define DRM_VMW_GET_PARAM 0 #define DRM_VMW_ALLOC_DMABUF 1 #define DRM_VMW_UNREF_DMABUF 2 +#define DRM_VMW_HANDLE_CLOSE 2 #define DRM_VMW_CURSOR_BYPASS 3 /* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/ #define DRM_VMW_CONTROL_STREAM 4 @@ -296,13 +297,17 @@ union drm_vmw_surface_reference_arg { * @version: Allows expanding the execbuf ioctl parameters without breaking * backwards compatibility, since user-space will always tell the kernel * which version it uses. - * @flags: Execbuf flags. None currently. + * @flags: Execbuf flags. + * @imported_fence_fd: FD for a fence imported from another device * * Argument to the DRM_VMW_EXECBUF Ioctl. */ #define DRM_VMW_EXECBUF_VERSION 2 +#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0) +#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1) + struct drm_vmw_execbuf_arg { __u64 commands; __u32 command_size; @@ -311,7 +316,7 @@ struct drm_vmw_execbuf_arg { __u32 version; __u32 flags; __u32 context_handle; - __u32 pad64; + __s32 imported_fence_fd; }; /** @@ -327,6 +332,7 @@ struct drm_vmw_execbuf_arg { * @passed_seqno: The highest seqno number processed by the hardware * so far. This can be used to mark user-space fence objects as signaled, and * to determine whether a fence seqno might be stale. + * @fd: FD associated with the fence, -1 if not exported * @error: This member should've been set to -EFAULT on submission. * The following actions should be take on completion: * error == -EFAULT: Fence communication failed. The host is synchronized. @@ -344,7 +350,7 @@ struct drm_vmw_fence_rep { __u32 mask; __u32 seqno; __u32 passed_seqno; - __u32 pad64; + __s32 fd; __s32 error; }; @@ -1092,6 +1098,29 @@ union drm_vmw_extended_context_arg { struct drm_vmw_context_arg rep; }; +/*************************************************************************/ +/* + * DRM_VMW_HANDLE_CLOSE - Close a user-space handle and release its + * underlying resource. + * + * Note that this ioctl is overlaid on the DRM_VMW_UNREF_DMABUF Ioctl. + * The ioctl arguments therefore need to be identical in layout. + * + */ + +/** + * struct drm_vmw_handle_close_arg + * + * @handle: Handle to close. + * + * Argument to the DRM_VMW_HANDLE_CLOSE Ioctl. + */ +struct drm_vmw_handle_close_arg { + __u32 handle; + __u32 pad64; +}; + + #if defined(__cplusplus) } #endif -- cgit v1.2.3-54-g00ecf From 8ec043ecead3aacc017464d5eb133618909f723d Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 30 Mar 2018 13:23:45 +0100 Subject: headers: Update README Nouveau has made a very deliberate choice to hide its actual kernel ABI behind libdrm. i915 is no longer out of date. Signed-off-by: Daniel Stone Acked-by: Alex Deucher --- include/drm/README | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/drm/README b/include/drm/README index 5b518ddf..b4658dd7 100644 --- a/include/drm/README +++ b/include/drm/README @@ -91,14 +91,10 @@ Most UMS headers: Status: ? Promote to fixed size ints, which match the current (32bit) ones. -i915_drm.h - - Missing PARAMS - HAS_POOLED_EU, MIN_EU_IN_POOL CONTEXT_PARAM_NO_ERROR_CAPTURE -Status: Trivial. - nouveau_drm.h - Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs, enums -Status: ? +Status: Deliberate UABI choice; nouveau hides the exact kernel ABI behind libdrm r128_drm.h - Broken compat ioctls. -- cgit v1.2.3-54-g00ecf From 35affe89d5f617a972b1cfee00c51cbe9e7c64a2 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Mon, 2 Apr 2018 20:37:33 -0700 Subject: libdrm: gralloc_handle.h: Fix build issue with Android In trying to integrate the new gralloc_handle.h with the drm_hwcomposer, I started seeing the following compilation errors: In file included from external/drm_hwcomposer/platformdrmgeneric.cpp:28: external/libdrm/android/gralloc_handle.h:108:9: error: cannot initialize return object of type 'native_handle_t *' (aka 'native_handle *') with an lvalue of type 'struct gralloc_handle_t *' return handle; ^~~~~~ 1 error generated. This seems to be due to the gralloc_handle_create() definition needs to return a native_handle_t * type, rather then a gralloc_handle_t *, which is what the code actually returns. After talking w/ Rob Herring, having the code return the native handle should be the proper fix, so that is what this patch changes. Cc: Chih-Wei Huang Cc: Stefan Schake Cc: Robert Foss Cc: Sean Paul Cc: Rob Herring Signed-off-by: John Stultz Reviewed-by: Robert Foss --- android/gralloc_handle.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h index 9cb5a5d7..bcf753da 100644 --- a/android/gralloc_handle.h +++ b/android/gralloc_handle.h @@ -105,7 +105,7 @@ static inline native_handle_t *gralloc_handle_create(int32_t width, handle->usage = usage; handle->prime_fd = -1; - return handle; + return nhandle; } #endif -- cgit v1.2.3-54-g00ecf From 915c5fa5407ef5ace18b1bc69a4686c012273e8e Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 13 Apr 2018 16:26:43 -0700 Subject: Android.bp: Add include exports for android dir This forward ports Stefan Schake's patch 32ee9c0e0566 "android: Add missing include exports" to the Android.bp file. Change-Id: Ie07582b87ae3bda0d49073c524e5c0a394e614bb Signed-off-by: John Stultz --- Android.bp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Android.bp b/Android.bp index 429c22cc..9121068a 100644 --- a/Android.bp +++ b/Android.bp @@ -54,7 +54,7 @@ cc_library { "libdrm_sources", ], - export_include_dirs: ["include/drm"], + export_include_dirs: ["include/drm", "android"], cflags: [ "-Wno-enum-conversion", -- cgit v1.2.3-54-g00ecf