diff options
author | LCPD Auto Merger | 2019-09-10 02:39:31 -0500 |
---|---|---|
committer | LCPD Auto Merger | 2019-09-10 02:39:31 -0500 |
commit | 45e99229e9041fbac14d232692580b8aa07d9bf0 (patch) | |
tree | f9a5215bc61554b3d0d212ee97849cb74ecb4000 | |
parent | 7dff6880e8fdae9f8ebb212e97292bf5b4770173 (diff) | |
parent | ff854b45b49ff244fad75cd128dcc3c0cd253653 (diff) | |
download | kernel-45e99229e9041fbac14d232692580b8aa07d9bf0.tar.gz kernel-45e99229e9041fbac14d232692580b8aa07d9bf0.tar.xz kernel-45e99229e9041fbac14d232692580b8aa07d9bf0.zip |
Merged TI feature platform_base into ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform:
arm64: dts: ti: k3-j721e: Add support for pm2 som
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
-rw-r--r-- | arch/arm64/boot/dts/ti/Makefile | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts | 699 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 37 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-som-tps65917.dtsi | 307 |
5 files changed, 1007 insertions, 38 deletions
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 5ab3778d82ab..264ca1c1d5d7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile | |||
@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb \ | |||
21 | k3-am654-base-board-jailhouse.dtbo | 21 | k3-am654-base-board-jailhouse.dtbo |
22 | 22 | ||
23 | dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb \ | 23 | dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb \ |
24 | k3-j721e-proc-board-tps65917.dtb \ | ||
24 | k3-j721e-common-proc-board-infotainment.dtbo \ | 25 | k3-j721e-common-proc-board-infotainment.dtbo \ |
25 | k3-j721e-common-proc-board-infotainment-display-sharing.dtbo \ | 26 | k3-j721e-common-proc-board-infotainment-display-sharing.dtbo \ |
26 | k3-j721e-common-proc-board-jailhouse.dtbo | 27 | k3-j721e-common-proc-board-jailhouse.dtbo |
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 45227d1aad15..1066e3bff0b2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | |||
@@ -590,7 +590,6 @@ | |||
590 | &main_sdhci1 { | 590 | &main_sdhci1 { |
591 | /* SD/MMC */ | 591 | /* SD/MMC */ |
592 | vmmc-supply = <&vdd_mmc1>; | 592 | vmmc-supply = <&vdd_mmc1>; |
593 | vqmmc-supply = <&ldo1_reg>; | ||
594 | pinctrl-names = "default"; | 593 | pinctrl-names = "default"; |
595 | pinctrl-0 = <&main_mmc1_pins_default>; | 594 | pinctrl-0 = <&main_mmc1_pins_default>; |
596 | }; | 595 | }; |
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts b/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts new file mode 100644 index 000000000000..4fcf2be253ba --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts | |||
@@ -0,0 +1,699 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ | ||
4 | */ | ||
5 | |||
6 | /dts-v1/; | ||
7 | |||
8 | #include "k3-j721e-som-tps65917.dtsi" | ||
9 | #include <dt-bindings/gpio/gpio.h> | ||
10 | #include <dt-bindings/net/ti-dp83867.h> | ||
11 | #include <dt-bindings/pci/pci.h> | ||
12 | #include <dt-bindings/sound/ti-mcasp.h> | ||
13 | |||
14 | / { | ||
15 | chosen { | ||
16 | stdout-path = "serial2:115200n8"; | ||
17 | bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; | ||
18 | }; | ||
19 | |||
20 | evm_12v0: fixedregulator-evm12v0 { | ||
21 | /* main supply */ | ||
22 | compatible = "regulator-fixed"; | ||
23 | regulator-name = "evm_12v0"; | ||
24 | regulator-min-microvolt = <12000000>; | ||
25 | regulator-max-microvolt = <12000000>; | ||
26 | regulator-always-on; | ||
27 | regulator-boot-on; | ||
28 | }; | ||
29 | |||
30 | vsys_3v3: fixedregulator-vsys3v3 { | ||
31 | /* Output of LMS140 */ | ||
32 | compatible = "regulator-fixed"; | ||
33 | regulator-name = "vsys_3v3"; | ||
34 | regulator-min-microvolt = <3300000>; | ||
35 | regulator-max-microvolt = <3300000>; | ||
36 | vin-supply = <&evm_12v0>; | ||
37 | regulator-always-on; | ||
38 | regulator-boot-on; | ||
39 | }; | ||
40 | |||
41 | vsys_5v0: fixedregulator-vsys5v0 { | ||
42 | /* Output of LM5140 */ | ||
43 | compatible = "regulator-fixed"; | ||
44 | regulator-name = "vsys_5v0"; | ||
45 | regulator-min-microvolt = <5000000>; | ||
46 | regulator-max-microvolt = <5000000>; | ||
47 | vin-supply = <&evm_12v0>; | ||
48 | regulator-always-on; | ||
49 | regulator-boot-on; | ||
50 | }; | ||
51 | |||
52 | sound0: sound@0 { | ||
53 | compatible = "simple-audio-card"; | ||
54 | simple-audio-card,name = "j721e-cpb-analog"; | ||
55 | simple-audio-card,widgets = | ||
56 | "Headphone", "Stereo HP 1", | ||
57 | "Headphone", "Stereo HP 2", | ||
58 | "Headphone", "Stereo HP 3", | ||
59 | "Line", "Line Out", | ||
60 | "Microphone", "Stereo Mic 1", | ||
61 | "Microphone", "Stereo Mic 2", | ||
62 | "Line", "Line In"; | ||
63 | simple-audio-card,routing = | ||
64 | "Stereo HP 1", "AOUT1L", | ||
65 | "Stereo HP 1", "AOUT1R", | ||
66 | "Stereo HP 2", "AOUT2L", | ||
67 | "Stereo HP 2", "AOUT2R", | ||
68 | "Stereo HP 3", "AOUT3L", | ||
69 | "Stereo HP 3", "AOUT3R", | ||
70 | "Line Out", "AOUT4L", | ||
71 | "Line Out", "AOUT4R", | ||
72 | "AIN1L", "Stereo Mic 1", | ||
73 | "AIN1R", "Stereo Mic 1", | ||
74 | "AIN2L", "Stereo Mic 2", | ||
75 | "AIN2R", "Stereo Mic 2", | ||
76 | "AIN3L", "Line In", | ||
77 | "AIN3R", "Line In"; | ||
78 | simple-audio-card,mclk-fs = <256>; | ||
79 | |||
80 | simple-audio-card,dai-link@0 { | ||
81 | format = "dsp_a"; | ||
82 | bitclock-master = <&sound0_0_master>; | ||
83 | frame-master = <&sound0_0_master>; | ||
84 | sound0_0_master: cpu { | ||
85 | sound-dai = <&mcasp10>; | ||
86 | clocks = <&k3_clks 184 1>; | ||
87 | system-clock-id = <MCASP_CLK_HCLK_AUXCLK>; | ||
88 | dai-tdm-slot-num = <2>; | ||
89 | dai-tdm-slot-width = <32>; | ||
90 | dai-tdm-slot-tx-mask = <1 1>; | ||
91 | dai-tdm-slot-rx-mask = <1 1>; | ||
92 | }; | ||
93 | |||
94 | codec { | ||
95 | sound-dai = <&pcm3168a_1 0>; | ||
96 | dai-tdm-slot-num = <2>; | ||
97 | dai-tdm-slot-width = <32>; | ||
98 | dai-tdm-slot-tx-mask = <1 1>; | ||
99 | dai-tdm-slot-rx-mask = <1 1>; | ||
100 | }; | ||
101 | }; | ||
102 | |||
103 | simple-audio-card,dai-link@1 { | ||
104 | format = "dsp_a"; | ||
105 | bitclock-master = <&sound0_1_master>; | ||
106 | frame-master = <&sound0_1_master>; | ||
107 | sound0_1_master: cpu { | ||
108 | sound-dai = <&mcasp10>; | ||
109 | clocks = <&k3_clks 184 1>; | ||
110 | system-clock-id = <MCASP_CLK_HCLK_AUXCLK>; | ||
111 | dai-tdm-slot-num = <2>; | ||
112 | dai-tdm-slot-width = <32>; | ||
113 | dai-tdm-slot-tx-mask = <1 1>; | ||
114 | dai-tdm-slot-rx-mask = <1 1>; | ||
115 | }; | ||
116 | |||
117 | codec { | ||
118 | sound-dai = <&pcm3168a_1 1>; | ||
119 | dai-tdm-slot-num = <2>; | ||
120 | dai-tdm-slot-width = <32>; | ||
121 | dai-tdm-slot-tx-mask = <1 1>; | ||
122 | dai-tdm-slot-rx-mask = <1 1>; | ||
123 | }; | ||
124 | }; | ||
125 | }; | ||
126 | |||
127 | vdd_mmc1: fixedregulator-sd { | ||
128 | compatible = "regulator-fixed"; | ||
129 | regulator-name = "vdd_mmc1"; | ||
130 | regulator-min-microvolt = <3300000>; | ||
131 | regulator-max-microvolt = <3300000>; | ||
132 | regulator-boot-on; | ||
133 | enable-active-high; | ||
134 | vin-supply = <&vsys_3v3>; | ||
135 | gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; | ||
136 | }; | ||
137 | |||
138 | dp0: connector { | ||
139 | compatible = "dp-connector"; /* No such binding exists yet.. */ | ||
140 | |||
141 | port { | ||
142 | dp_connector_in: endpoint { | ||
143 | remote-endpoint = <&dp_bridge_output>; | ||
144 | }; | ||
145 | }; | ||
146 | }; | ||
147 | }; | ||
148 | |||
149 | &wkup_pmx0 { | ||
150 | mcu_cpsw_pins_default: mcu_cpsw_pins_default { | ||
151 | pinctrl-single,pins = < | ||
152 | J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ | ||
153 | J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ | ||
154 | J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ | ||
155 | J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ | ||
156 | J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ | ||
157 | J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ | ||
158 | J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ | ||
159 | J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ | ||
160 | J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ | ||
161 | J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ | ||
162 | J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ | ||
163 | J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ | ||
164 | >; | ||
165 | }; | ||
166 | |||
167 | mcu_mdio_pins_default: mcu_mdio1_pins_default { | ||
168 | pinctrl-single,pins = < | ||
169 | J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ | ||
170 | J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ | ||
171 | >; | ||
172 | }; | ||
173 | |||
174 | mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { | ||
175 | pinctrl-single,pins = < | ||
176 | J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ | ||
177 | J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ | ||
178 | J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ | ||
179 | J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ | ||
180 | J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ | ||
181 | J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ | ||
182 | J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ | ||
183 | J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ | ||
184 | >; | ||
185 | }; | ||
186 | }; | ||
187 | |||
188 | &wkup_uart0 { | ||
189 | /* Wakeup UART is used by System firmware */ | ||
190 | status = "disabled"; | ||
191 | }; | ||
192 | |||
193 | &main_uart3 { | ||
194 | /* UART not brought out */ | ||
195 | status = "disabled"; | ||
196 | }; | ||
197 | |||
198 | &main_uart5 { | ||
199 | /* UART not brought out */ | ||
200 | status = "disabled"; | ||
201 | }; | ||
202 | |||
203 | &main_uart6 { | ||
204 | /* UART not brought out */ | ||
205 | status = "disabled"; | ||
206 | }; | ||
207 | |||
208 | &main_uart7 { | ||
209 | /* UART not brought out */ | ||
210 | status = "disabled"; | ||
211 | }; | ||
212 | |||
213 | &main_uart8 { | ||
214 | /* UART not brought out */ | ||
215 | status = "disabled"; | ||
216 | }; | ||
217 | |||
218 | &main_uart9 { | ||
219 | /* UART not brought out */ | ||
220 | status = "disabled"; | ||
221 | }; | ||
222 | |||
223 | &main_gpio2 { | ||
224 | status = "disabled"; | ||
225 | }; | ||
226 | |||
227 | &main_gpio3 { | ||
228 | status = "disabled"; | ||
229 | }; | ||
230 | |||
231 | &main_gpio4 { | ||
232 | status = "disabled"; | ||
233 | }; | ||
234 | |||
235 | &main_gpio5 { | ||
236 | status = "disabled"; | ||
237 | }; | ||
238 | |||
239 | &main_gpio6 { | ||
240 | status = "disabled"; | ||
241 | }; | ||
242 | |||
243 | &main_gpio7 { | ||
244 | status = "disabled"; | ||
245 | }; | ||
246 | |||
247 | &wkup_gpio1 { | ||
248 | status = "disabled"; | ||
249 | }; | ||
250 | |||
251 | &main_pmx0 { | ||
252 | main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { | ||
253 | pinctrl-single,pins = < | ||
254 | J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ | ||
255 | >; | ||
256 | }; | ||
257 | |||
258 | main_i2c0_pins_default: main-i2c0-pins-default { | ||
259 | pinctrl-single,pins = < | ||
260 | J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ | ||
261 | J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ | ||
262 | >; | ||
263 | }; | ||
264 | |||
265 | main_i2c1_pins_default: main-i2c1-pins-default { | ||
266 | pinctrl-single,pins = < | ||
267 | J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ | ||
268 | J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ | ||
269 | >; | ||
270 | }; | ||
271 | |||
272 | main_i2c3_pins_default: main-i2c3-pins-default { | ||
273 | pinctrl-single,pins = < | ||
274 | J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ | ||
275 | J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ | ||
276 | >; | ||
277 | }; | ||
278 | |||
279 | main_i2c6_pins_default: main-i2c6-pins-default { | ||
280 | pinctrl-single,pins = < | ||
281 | J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ | ||
282 | J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ | ||
283 | >; | ||
284 | }; | ||
285 | |||
286 | mcasp10_pins_default: mcasp10_pins_default { | ||
287 | pinctrl-single,pins = < | ||
288 | J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ | ||
289 | J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ | ||
290 | J721E_IOPAD(0x160, PIN_INPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ | ||
291 | J721E_IOPAD(0x164, PIN_INPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ | ||
292 | J721E_IOPAD(0x170, PIN_INPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ | ||
293 | J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ | ||
294 | J721E_IOPAD(0x198, PIN_OUTPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ | ||
295 | J721E_IOPAD(0x19c, PIN_OUTPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ | ||
296 | J721E_IOPAD(0x1a0, PIN_OUTPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ | ||
297 | >; | ||
298 | }; | ||
299 | |||
300 | audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default { | ||
301 | pinctrl-single,pins = < | ||
302 | J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ | ||
303 | >; | ||
304 | }; | ||
305 | |||
306 | main_usbss0_pins_default: main_usbss0_pins_default { | ||
307 | pinctrl-single,pins = < | ||
308 | J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ | ||
309 | J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ | ||
310 | >; | ||
311 | }; | ||
312 | |||
313 | main_usbss1_pins_default: main_usbss1_pins_default { | ||
314 | pinctrl-single,pins = < | ||
315 | J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ | ||
316 | >; | ||
317 | }; | ||
318 | |||
319 | main_mmc1_pins_default: main_mmc1_pins_default { | ||
320 | pinctrl-single,pins = < | ||
321 | J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ | ||
322 | J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ | ||
323 | J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ | ||
324 | J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ | ||
325 | J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ | ||
326 | J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ | ||
327 | J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ | ||
328 | J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ | ||
329 | J721E_IOPAD(0x2ac, PIN_INPUT, 0) | ||
330 | >; | ||
331 | }; | ||
332 | |||
333 | dp0_pins_default: dp0_pins_default { | ||
334 | pinctrl-single,pins = < | ||
335 | J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ | ||
336 | >; | ||
337 | }; | ||
338 | }; | ||
339 | |||
340 | &dss { | ||
341 | status = "ok"; | ||
342 | }; | ||
343 | |||
344 | &dss_ports { | ||
345 | #address-cells = <1>; | ||
346 | #size-cells = <0>; | ||
347 | |||
348 | port@0 { | ||
349 | reg = <0>; | ||
350 | |||
351 | dpi_out_real0: endpoint { | ||
352 | remote-endpoint = <&dp_bridge_input>; | ||
353 | }; | ||
354 | }; | ||
355 | }; | ||
356 | |||
357 | &main_i2c0 { | ||
358 | pinctrl-names = "default"; | ||
359 | pinctrl-0 = <&main_i2c0_pins_default>; | ||
360 | clock-frequency = <400000>; | ||
361 | |||
362 | exp1: gpio@20 { | ||
363 | compatible = "ti,tca6416"; | ||
364 | reg = <0x20>; | ||
365 | gpio-controller; | ||
366 | #gpio-cells = <2>; | ||
367 | }; | ||
368 | |||
369 | exp2: gpio@22 { | ||
370 | compatible = "ti,tca6424"; | ||
371 | reg = <0x22>; | ||
372 | gpio-controller; | ||
373 | #gpio-cells = <2>; | ||
374 | |||
375 | p09 { | ||
376 | /* P11 - MCASP/TRACE_MUX_S0 */ | ||
377 | gpio-hog; | ||
378 | gpios = <9 GPIO_ACTIVE_HIGH>; | ||
379 | output-low; | ||
380 | line-name = "MCASP/TRACE_MUX_S0"; | ||
381 | }; | ||
382 | |||
383 | p10 { | ||
384 | /* P12 - MCASP/TRACE_MUX_S1 */ | ||
385 | gpio-hog; | ||
386 | gpios = <10 GPIO_ACTIVE_HIGH>; | ||
387 | output-high; | ||
388 | line-name = "MCASP/TRACE_MUX_S1"; | ||
389 | }; | ||
390 | }; | ||
391 | }; | ||
392 | |||
393 | &main_i2c1 { | ||
394 | pinctrl-names = "default"; | ||
395 | pinctrl-0 = <&main_i2c1_pins_default>; | ||
396 | clock-frequency = <400000>; | ||
397 | |||
398 | exp4: gpio@20 { | ||
399 | compatible = "ti,tca6408"; | ||
400 | reg = <0x20>; | ||
401 | gpio-controller; | ||
402 | #gpio-cells = <2>; | ||
403 | pinctrl-names = "default"; | ||
404 | pinctrl-0 = <&main_i2c1_exp4_pins_default>; | ||
405 | interrupt-parent = <&main_gpio1>; | ||
406 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; | ||
407 | interrupt-controller; | ||
408 | #interrupt-cells = <2>; | ||
409 | |||
410 | p0 { | ||
411 | /* P0 - DP0_PWR_SW_EN */ | ||
412 | gpio-hog; | ||
413 | gpios = <0 GPIO_ACTIVE_HIGH>; | ||
414 | output-high; | ||
415 | line-name = "DP0_PWR_SW_EN"; | ||
416 | }; | ||
417 | }; | ||
418 | }; | ||
419 | |||
420 | &main_i2c3 { | ||
421 | pinctrl-names = "default"; | ||
422 | pinctrl-0 = <&main_i2c3_pins_default>; | ||
423 | clock-frequency = <400000>; | ||
424 | |||
425 | exp3: gpio@20 { | ||
426 | compatible = "ti,tca6408"; | ||
427 | reg = <0x20>; | ||
428 | gpio-controller; | ||
429 | #gpio-cells = <2>; | ||
430 | |||
431 | p0 { | ||
432 | /* P0 - CODEC_RSTz */ | ||
433 | gpio-hog; | ||
434 | gpios = <0 GPIO_ACTIVE_HIGH>; | ||
435 | output-high; | ||
436 | line-name = "CODEC_RSTz"; | ||
437 | }; | ||
438 | }; | ||
439 | |||
440 | pcm3168a_1: audio-codec@44 { | ||
441 | compatible = "ti,pcm3168a"; | ||
442 | reg = <0x44>; | ||
443 | |||
444 | pinctrl-names = "default"; | ||
445 | pinctrl-0 = <&audi_ext_refclk2_pins_default>; | ||
446 | |||
447 | #sound-dai-cells = <1>; | ||
448 | |||
449 | /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ | ||
450 | clocks = <&k3_clks 157 371>; | ||
451 | clock-names = "scki"; | ||
452 | |||
453 | /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ | ||
454 | assigned-clocks = <&k3_clks 157 371>; | ||
455 | assigned-clock-parents = <&k3_clks 157 400>; | ||
456 | assigned-clock-rates = <24576000>; /* for 48KHz */ | ||
457 | |||
458 | VDD1-supply = <&vsys_3v3>; | ||
459 | VDD2-supply = <&vsys_3v3>; | ||
460 | VCCAD1-supply = <&vsys_5v0>; | ||
461 | VCCAD2-supply = <&vsys_5v0>; | ||
462 | VCCDA1-supply = <&vsys_5v0>; | ||
463 | VCCDA2-supply = <&vsys_5v0>; | ||
464 | }; | ||
465 | }; | ||
466 | |||
467 | &main_i2c6 { | ||
468 | pinctrl-names = "default"; | ||
469 | pinctrl-0 = <&main_i2c6_pins_default>; | ||
470 | clock-frequency = <400000>; | ||
471 | |||
472 | exp5: gpio@20 { | ||
473 | compatible = "ti,tca6408"; | ||
474 | reg = <0x20>; | ||
475 | gpio-controller; | ||
476 | #gpio-cells = <2>; | ||
477 | }; | ||
478 | }; | ||
479 | |||
480 | &mcu_cpsw { | ||
481 | pinctrl-names = "default"; | ||
482 | pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; | ||
483 | |||
484 | cpts { | ||
485 | ti,pps = <3 1>; | ||
486 | }; | ||
487 | }; | ||
488 | |||
489 | &davinci_mdio { | ||
490 | phy0: ethernet-phy@0 { | ||
491 | reg = <0>; | ||
492 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; | ||
493 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; | ||
494 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; | ||
495 | }; | ||
496 | }; | ||
497 | |||
498 | &cpsw_port1 { | ||
499 | phy-mode = "rgmii-id"; | ||
500 | phy-handle = <&phy0>; | ||
501 | }; | ||
502 | |||
503 | #define TS_OFFSET(pa, val) (0x4 + (pa) * 4) (0x10000 | val) | ||
504 | |||
505 | ×ync_router { | ||
506 | pinctrl-names = "default"; | ||
507 | pinctrl-0 = <&mcu_cpts>; | ||
508 | |||
509 | mcu_cpts: mcu_cpts { | ||
510 | pinctrl-single,pins = < | ||
511 | /* pps [cpts genf1] in17 -> out25 [cpts hw4_push] */ | ||
512 | TS_OFFSET(25, 17) | ||
513 | >; | ||
514 | }; | ||
515 | }; | ||
516 | |||
517 | &ospi1 { | ||
518 | pinctrl-names = "default"; | ||
519 | pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; | ||
520 | |||
521 | flash@0{ | ||
522 | compatible = "jedec,spi-nor"; | ||
523 | reg = <0x0>; | ||
524 | spi-tx-bus-width = <1>; | ||
525 | spi-rx-bus-width = <4>; | ||
526 | spi-max-frequency = <100000000>; | ||
527 | cdns,tshsl-ns = <60>; | ||
528 | cdns,tsd2d-ns = <60>; | ||
529 | cdns,tchsh-ns = <60>; | ||
530 | cdns,tslch-ns = <60>; | ||
531 | cdns,read-delay = <2>; | ||
532 | #address-cells = <1>; | ||
533 | #size-cells = <1>; | ||
534 | }; | ||
535 | }; | ||
536 | |||
537 | &mcasp10 { | ||
538 | #sound-dai-cells = <0>; | ||
539 | |||
540 | pinctrl-names = "default"; | ||
541 | pinctrl-0 = <&mcasp10_pins_default>; | ||
542 | |||
543 | op-mode = <0>; /* MCASP_IIS_MODE */ | ||
544 | tdm-slots = <2>; | ||
545 | auxclk-fs-ratio = <256>; | ||
546 | |||
547 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | ||
548 | 2 2 2 1 | ||
549 | 1 1 1 0 | ||
550 | >; | ||
551 | tx-num-evt = <0>; | ||
552 | rx-num-evt = <0>; | ||
553 | |||
554 | status = "okay"; | ||
555 | }; | ||
556 | |||
557 | &usb_serdes_mux { | ||
558 | idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ | ||
559 | }; | ||
560 | |||
561 | &serdes_ln_ctrl { | ||
562 | idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, | ||
563 | <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, | ||
564 | <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, | ||
565 | <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>, | ||
566 | <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; | ||
567 | }; | ||
568 | |||
569 | &serdes_wiz3 { | ||
570 | typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; | ||
571 | }; | ||
572 | |||
573 | &serdes3 { | ||
574 | serdes3_usb_link: link@0 { | ||
575 | reg = <0>; | ||
576 | cdns,num-lanes = <2>; | ||
577 | #phy-cells = <0>; | ||
578 | cdns,phy-type = <PHY_TYPE_USB3>; | ||
579 | resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; | ||
580 | }; | ||
581 | }; | ||
582 | |||
583 | &usbss0 { | ||
584 | pinctrl-names = "default"; | ||
585 | pinctrl-0 = <&main_usbss0_pins_default>; | ||
586 | ti,vbus-divider; | ||
587 | }; | ||
588 | |||
589 | &usb0 { | ||
590 | dr_mode = "otg"; | ||
591 | maximum-speed = "super-speed"; | ||
592 | phys = <&serdes3_usb_link>; | ||
593 | phy-names = "cdns3,usbphy"; | ||
594 | }; | ||
595 | |||
596 | &usbss1 { | ||
597 | pinctrl-names = "default"; | ||
598 | pinctrl-0 = <&main_usbss1_pins_default>; | ||
599 | ti,usb2-only; | ||
600 | }; | ||
601 | |||
602 | &usb1 { | ||
603 | dr_mode = "host"; | ||
604 | maximum-speed = "high-speed"; | ||
605 | }; | ||
606 | |||
607 | &main_sdhci0 { | ||
608 | /* eMMC */ | ||
609 | non-removable; | ||
610 | ti,driver-strength-ohm = <50>; | ||
611 | }; | ||
612 | |||
613 | &main_sdhci1 { | ||
614 | /* SD/MMC */ | ||
615 | vmmc-supply = <&vdd_mmc1>; | ||
616 | vqmmc-supply = <&ldo1_reg>; | ||
617 | pinctrl-names = "default"; | ||
618 | pinctrl-0 = <&main_mmc1_pins_default>; | ||
619 | }; | ||
620 | |||
621 | &main_sdhci2 { | ||
622 | /* Unused */ | ||
623 | status = "disabled"; | ||
624 | }; | ||
625 | |||
626 | &serdes0 { | ||
627 | serdes0_pcie_link: link@0 { | ||
628 | reg = <0>; | ||
629 | cdns,num-lanes = <1>; | ||
630 | #phy-cells = <0>; | ||
631 | cdns,phy-type = <PHY_TYPE_PCIE>; | ||
632 | resets = <&serdes_wiz0 1>; | ||
633 | }; | ||
634 | }; | ||
635 | |||
636 | &serdes1 { | ||
637 | serdes1_pcie_link: link@0 { | ||
638 | reg = <0>; | ||
639 | cdns,num-lanes = <2>; | ||
640 | #phy-cells = <0>; | ||
641 | cdns,phy-type = <PHY_TYPE_PCIE>; | ||
642 | resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; | ||
643 | }; | ||
644 | }; | ||
645 | |||
646 | &serdes2 { | ||
647 | serdes2_pcie_link: link@0 { | ||
648 | reg = <0>; | ||
649 | cdns,num-lanes = <2>; | ||
650 | #phy-cells = <0>; | ||
651 | cdns,phy-type = <PHY_TYPE_PCIE>; | ||
652 | resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; | ||
653 | }; | ||
654 | }; | ||
655 | |||
656 | &pcie0 { | ||
657 | pci-mode = <PCI_MODE_RC>; | ||
658 | num-lanes = <1>; | ||
659 | }; | ||
660 | |||
661 | &pcie1 { | ||
662 | pci-mode = <PCI_MODE_RC>; | ||
663 | num-lanes = <2>; | ||
664 | }; | ||
665 | |||
666 | &pcie2 { | ||
667 | pci-mode = <PCI_MODE_RC>; | ||
668 | num-lanes = <2>; | ||
669 | }; | ||
670 | |||
671 | &pcie0_rc { | ||
672 | reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; | ||
673 | phys = <&serdes0_pcie_link>; | ||
674 | phy-names = "pcie_phy"; | ||
675 | }; | ||
676 | |||
677 | &pcie1_rc { | ||
678 | reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; | ||
679 | phys = <&serdes1_pcie_link>; | ||
680 | phy-names = "pcie_phy"; | ||
681 | }; | ||
682 | |||
683 | &pcie2_rc { | ||
684 | reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; | ||
685 | phys = <&serdes2_pcie_link>; | ||
686 | phy-names = "pcie_phy"; | ||
687 | }; | ||
688 | |||
689 | &tscadc0 { | ||
690 | adc { | ||
691 | ti,adc-channels = <0 1 2 3 4 5 6 7>; | ||
692 | }; | ||
693 | }; | ||
694 | |||
695 | &tscadc1 { | ||
696 | adc { | ||
697 | ti,adc-channels = <0 1 2 3 4 5 6 7>; | ||
698 | }; | ||
699 | }; | ||
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 8e7433814b85..1d3277dade37 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | |||
@@ -186,43 +186,6 @@ | |||
186 | }; | 186 | }; |
187 | }; | 187 | }; |
188 | 188 | ||
189 | &wkup_i2c0 { | ||
190 | pinctrl-names = "default"; | ||
191 | pinctrl-0 = <&wkup_i2c0_pins_default>; | ||
192 | clock-frequency = <400000>; | ||
193 | |||
194 | tps65917: tps65917@58 { | ||
195 | reg = <0x58>; | ||
196 | compatible = "ti,tps65917"; | ||
197 | |||
198 | tps65917_pmic { | ||
199 | compatible = "ti,tps65917-pmic"; | ||
200 | |||
201 | ldo1-in-supply = <&vsys_3v3>; | ||
202 | |||
203 | tps65917_regulators: regulators { | ||
204 | ldo1_reg: ldo1 { | ||
205 | /* LDO1_OUT --> VDD_SD_DV_REG */ | ||
206 | regulator-name = "ldo1"; | ||
207 | regulator-min-microvolt = <1800000>; | ||
208 | regulator-max-microvolt = <3300000>; | ||
209 | regulator-allow-bypass; | ||
210 | }; | ||
211 | |||
212 | ldo2_reg: ldo2 { | ||
213 | /* LDO2_OUT --> VDA_USB_3V3_REG */ | ||
214 | regulator-name = "ldo2"; | ||
215 | regulator-min-microvolt = <3300000>; | ||
216 | regulator-max-microvolt = <3300000>; | ||
217 | regulator-allow-bypass; | ||
218 | regulator-always-on; | ||
219 | regulator-boot-on; | ||
220 | }; | ||
221 | }; | ||
222 | }; | ||
223 | }; | ||
224 | }; | ||
225 | |||
226 | &ospi0 { | 189 | &ospi0 { |
227 | pinctrl-names = "default"; | 190 | pinctrl-names = "default"; |
228 | pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; | 191 | pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; |
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-tps65917.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-tps65917.dtsi new file mode 100644 index 000000000000..8e7433814b85 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-tps65917.dtsi | |||
@@ -0,0 +1,307 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ | ||
4 | */ | ||
5 | |||
6 | /dts-v1/; | ||
7 | |||
8 | #include "k3-j721e.dtsi" | ||
9 | |||
10 | / { | ||
11 | memory@80000000 { | ||
12 | device_type = "memory"; | ||
13 | /* 4G RAM */ | ||
14 | reg = <0x00000000 0x80000000 0x00000000 0x80000000>, | ||
15 | <0x00000008 0x80000000 0x00000000 0x80000000>; | ||
16 | }; | ||
17 | |||
18 | reserved_memory: reserved-memory { | ||
19 | #address-cells = <2>; | ||
20 | #size-cells = <2>; | ||
21 | ranges; | ||
22 | |||
23 | secure_ddr: optee@9e800000 { | ||
24 | reg = <0x00 0x9e800000 0x00 0x01800000>; | ||
25 | alignment = <0x1000>; | ||
26 | no-map; | ||
27 | }; | ||
28 | |||
29 | mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { | ||
30 | compatible = "shared-dma-pool"; | ||
31 | reg = <0x00 0xa0000000 0x00 0x100000>; | ||
32 | no-map; | ||
33 | }; | ||
34 | |||
35 | mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { | ||
36 | compatible = "shared-dma-pool"; | ||
37 | reg = <0x00 0xa0100000 0x00 0xf00000>; | ||
38 | no-map; | ||
39 | }; | ||
40 | |||
41 | mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { | ||
42 | compatible = "shared-dma-pool"; | ||
43 | reg = <0x00 0xa1000000 0x00 0x100000>; | ||
44 | no-map; | ||
45 | }; | ||
46 | |||
47 | mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { | ||
48 | compatible = "shared-dma-pool"; | ||
49 | reg = <0x00 0xa1100000 0x00 0xf00000>; | ||
50 | no-map; | ||
51 | }; | ||
52 | |||
53 | main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { | ||
54 | compatible = "shared-dma-pool"; | ||
55 | reg = <0x00 0xa2000000 0x00 0x100000>; | ||
56 | no-map; | ||
57 | }; | ||
58 | |||
59 | main_r5fss0_core0_memory_region: r5f-memory@a2100000 { | ||
60 | compatible = "shared-dma-pool"; | ||
61 | reg = <0x00 0xa2100000 0x00 0xf00000>; | ||
62 | no-map; | ||
63 | }; | ||
64 | |||
65 | main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { | ||
66 | compatible = "shared-dma-pool"; | ||
67 | reg = <0x00 0xa3000000 0x00 0x100000>; | ||
68 | no-map; | ||
69 | }; | ||
70 | |||
71 | main_r5fss0_core1_memory_region: r5f-memory@a3100000 { | ||
72 | compatible = "shared-dma-pool"; | ||
73 | reg = <0x00 0xa3100000 0x00 0xf00000>; | ||
74 | no-map; | ||
75 | }; | ||
76 | |||
77 | main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { | ||
78 | compatible = "shared-dma-pool"; | ||
79 | reg = <0x00 0xa4000000 0x00 0x100000>; | ||
80 | no-map; | ||
81 | }; | ||
82 | |||
83 | main_r5fss1_core0_memory_region: r5f-memory@a4100000 { | ||
84 | compatible = "shared-dma-pool"; | ||
85 | reg = <0x00 0xa4100000 0x00 0xf00000>; | ||
86 | no-map; | ||
87 | }; | ||
88 | |||
89 | main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { | ||
90 | compatible = "shared-dma-pool"; | ||
91 | reg = <0x00 0xa5000000 0x00 0x100000>; | ||
92 | no-map; | ||
93 | }; | ||
94 | |||
95 | main_r5fss1_core1_memory_region: r5f-memory@a5100000 { | ||
96 | compatible = "shared-dma-pool"; | ||
97 | reg = <0x00 0xa5100000 0x00 0xf00000>; | ||
98 | no-map; | ||
99 | }; | ||
100 | |||
101 | c66_1_dma_memory_region: c66-dma-memory@a6000000 { | ||
102 | compatible = "shared-dma-pool"; | ||
103 | reg = <0x00 0xa6000000 0x00 0x100000>; | ||
104 | no-map; | ||
105 | }; | ||
106 | |||
107 | c66_0_memory_region: c66-memory@a6100000 { | ||
108 | compatible = "shared-dma-pool"; | ||
109 | reg = <0x00 0xa6100000 0x00 0xf00000>; | ||
110 | no-map; | ||
111 | }; | ||
112 | |||
113 | c66_0_dma_memory_region: c66-dma-memory@a7000000 { | ||
114 | compatible = "shared-dma-pool"; | ||
115 | reg = <0x00 0xa7000000 0x00 0x100000>; | ||
116 | no-map; | ||
117 | }; | ||
118 | |||
119 | c66_1_memory_region: c66-memory@a7100000 { | ||
120 | compatible = "shared-dma-pool"; | ||
121 | reg = <0x00 0xa7100000 0x00 0xf00000>; | ||
122 | no-map; | ||
123 | }; | ||
124 | |||
125 | c71_0_dma_memory_region: c71-dma-memory@a8000000 { | ||
126 | compatible = "shared-dma-pool"; | ||
127 | reg = <0x00 0xa8000000 0x00 0x100000>; | ||
128 | no-map; | ||
129 | }; | ||
130 | |||
131 | c71_0_memory_region: c71-memory@a8100000 { | ||
132 | compatible = "shared-dma-pool"; | ||
133 | reg = <0x00 0xa8100000 0x00 0xf00000>; | ||
134 | no-map; | ||
135 | }; | ||
136 | |||
137 | rtos_ipc_memory_region: ipc-memories@aa000000 { | ||
138 | reg = <0x00 0xaa000000 0x00 0x01c00000>; | ||
139 | alignment = <0x1000>; | ||
140 | no-map; | ||
141 | }; | ||
142 | }; | ||
143 | }; | ||
144 | |||
145 | &wkup_pmx0 { | ||
146 | wkup_i2c0_pins_default: wkup_i2c0_pins_default { | ||
147 | pinctrl-single,pins = < | ||
148 | J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ | ||
149 | J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ | ||
150 | >; | ||
151 | }; | ||
152 | |||
153 | mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { | ||
154 | pinctrl-single,pins = < | ||
155 | J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ | ||
156 | J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ | ||
157 | J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ | ||
158 | J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ | ||
159 | J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ | ||
160 | J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ | ||
161 | J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ | ||
162 | J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ | ||
163 | J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ | ||
164 | J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ | ||
165 | J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ | ||
166 | >; | ||
167 | }; | ||
168 | |||
169 | mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { | ||
170 | pinctrl-single,pins = < | ||
171 | J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ | ||
172 | J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ | ||
173 | J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ | ||
174 | J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ | ||
175 | J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ | ||
176 | J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ | ||
177 | J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ | ||
178 | J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ | ||
179 | J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ | ||
180 | J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ | ||
181 | J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ | ||
182 | J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ | ||
183 | J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ | ||
184 | J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ | ||
185 | >; | ||
186 | }; | ||
187 | }; | ||
188 | |||
189 | &wkup_i2c0 { | ||
190 | pinctrl-names = "default"; | ||
191 | pinctrl-0 = <&wkup_i2c0_pins_default>; | ||
192 | clock-frequency = <400000>; | ||
193 | |||
194 | tps65917: tps65917@58 { | ||
195 | reg = <0x58>; | ||
196 | compatible = "ti,tps65917"; | ||
197 | |||
198 | tps65917_pmic { | ||
199 | compatible = "ti,tps65917-pmic"; | ||
200 | |||
201 | ldo1-in-supply = <&vsys_3v3>; | ||
202 | |||
203 | tps65917_regulators: regulators { | ||
204 | ldo1_reg: ldo1 { | ||
205 | /* LDO1_OUT --> VDD_SD_DV_REG */ | ||
206 | regulator-name = "ldo1"; | ||
207 | regulator-min-microvolt = <1800000>; | ||
208 | regulator-max-microvolt = <3300000>; | ||
209 | regulator-allow-bypass; | ||
210 | }; | ||
211 | |||
212 | ldo2_reg: ldo2 { | ||
213 | /* LDO2_OUT --> VDA_USB_3V3_REG */ | ||
214 | regulator-name = "ldo2"; | ||
215 | regulator-min-microvolt = <3300000>; | ||
216 | regulator-max-microvolt = <3300000>; | ||
217 | regulator-allow-bypass; | ||
218 | regulator-always-on; | ||
219 | regulator-boot-on; | ||
220 | }; | ||
221 | }; | ||
222 | }; | ||
223 | }; | ||
224 | }; | ||
225 | |||
226 | &ospi0 { | ||
227 | pinctrl-names = "default"; | ||
228 | pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; | ||
229 | |||
230 | flash@0{ | ||
231 | compatible = "jedec,spi-nor"; | ||
232 | reg = <0x0>; | ||
233 | spi-tx-bus-width = <8>; | ||
234 | spi-rx-bus-width = <8>; | ||
235 | spi-max-frequency = <50000000>; | ||
236 | spi-dqs; | ||
237 | cdns,tshsl-ns = <60>; | ||
238 | cdns,tsd2d-ns = <60>; | ||
239 | cdns,tchsh-ns = <60>; | ||
240 | cdns,tslch-ns = <60>; | ||
241 | cdns,read-delay = <0>; | ||
242 | cdns,phy-mode; | ||
243 | #address-cells = <1>; | ||
244 | #size-cells = <1>; | ||
245 | }; | ||
246 | }; | ||
247 | |||
248 | &mcu_r5fss0_core0 { | ||
249 | memory-region = <&mcu_r5fss0_core0_dma_memory_region>, | ||
250 | <&mcu_r5fss0_core0_memory_region>; | ||
251 | }; | ||
252 | |||
253 | &mcu_r5fss0_core1 { | ||
254 | memory-region = <&mcu_r5fss0_core1_dma_memory_region>, | ||
255 | <&mcu_r5fss0_core1_memory_region>; | ||
256 | }; | ||
257 | |||
258 | &main_r5fss0_core0 { | ||
259 | memory-region = <&main_r5fss0_core0_dma_memory_region>, | ||
260 | <&main_r5fss0_core0_memory_region>; | ||
261 | }; | ||
262 | |||
263 | &main_r5fss0_core1 { | ||
264 | memory-region = <&main_r5fss0_core1_dma_memory_region>, | ||
265 | <&main_r5fss0_core1_memory_region>; | ||
266 | }; | ||
267 | |||
268 | &main_r5fss1_core0 { | ||
269 | memory-region = <&main_r5fss1_core0_dma_memory_region>, | ||
270 | <&main_r5fss1_core0_memory_region>; | ||
271 | }; | ||
272 | |||
273 | &main_r5fss1_core1 { | ||
274 | memory-region = <&main_r5fss1_core1_dma_memory_region>, | ||
275 | <&main_r5fss1_core1_memory_region>; | ||
276 | }; | ||
277 | |||
278 | &c66_0 { | ||
279 | memory-region = <&c66_0_dma_memory_region>, | ||
280 | <&c66_0_memory_region>; | ||
281 | }; | ||
282 | |||
283 | &c66_1 { | ||
284 | memory-region = <&c66_1_dma_memory_region>, | ||
285 | <&c66_1_memory_region>; | ||
286 | }; | ||
287 | |||
288 | &c71_0 { | ||
289 | memory-region = <&c71_0_dma_memory_region>, | ||
290 | <&c71_0_memory_region>; | ||
291 | }; | ||
292 | |||
293 | &hbmc { | ||
294 | /* OSPI and HBMC are muxed inside FSS, Bootloader will enable | ||
295 | * appropriate node based on board detection | ||
296 | */ | ||
297 | status = "disabled"; | ||
298 | pinctrl-names = "default"; | ||
299 | pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; | ||
300 | ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ | ||
301 | <0x1 0x0 0x5 0x04000000 0x800000>; /* 8MB RAM on CS1 */ | ||
302 | |||
303 | flash@0,0 { | ||
304 | compatible = "cypress,hyperflash", "cfi-flash"; | ||
305 | reg = <0x0 0x0 0x4000000>; | ||
306 | }; | ||
307 | }; | ||