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authorOlof Johansson2017-04-19 08:33:08 -0500
committerOlof Johansson2017-04-19 08:33:08 -0500
commit13ed63b6cbdf3b99abf47fd92325a18dc6282152 (patch)
tree4478a0b7f6252bb00dab20856ef54af4b8cc9cad
parentab719074fa14666139376d6b6e5e0e75325d582f (diff)
parent6678254bb4a46dc47620f993a4b71480a3c56ee4 (diff)
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Merge tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.12: - Add support of LS2088A SoC, which is a derivative of existing LS2080A SoC, and the major difference is on ARM cores. - Add support of LS1088A SoC which includes eight Cortex-A53 cores with 32 KB L1 D-cache and I-cache respectively. - Add crypto and thermal device support for LS1012A platform. - Add ECC register region for SATA device on LS1012A, LS1043A and LS1046A platforms. * tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards dt-bindings: clockgen: Add compatible string for LS1088A arm64: dts: Add support for FSL's LS1088A SoC arm64: dts: ls1012a: add crypto node arm64: dts: ls1012a: add thermal monitor node arm64: dts: updated sata node on ls1012a platform arm64: dts: added ecc register address to sata node on ls1046a arm64: dts: added ecc register address to sata node on ls1043a arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC arm64: dts: freescale: ls2080a: Split devicetree for code resuability dt-bindings: Add compatible for LS2088A QDS and RDB board Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt23
-rw-r--r--Documentation/devicetree/bindings/clock/qoriq-clock.txt1
-rw-r--r--arch/arm64/boot/dts/freescale/Makefile4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi182
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts123
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts107
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi275
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts155
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts110
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi863
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts64
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts64
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi165
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi196
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi151
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi737
21 files changed, 2206 insertions, 1034 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index c9c567ae227f..cdb9dd705754 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -179,6 +179,18 @@ LS1046A ARMv8 based RDB Board
179Required root node properties: 179Required root node properties:
180 - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; 180 - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
181 181
182LS1088A SoC
183Required root node properties:
184 - compatible = "fsl,ls1088a";
185
186LS1088A ARMv8 based QDS Board
187Required root node properties:
188 - compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
189
190LS1088A ARMv8 based RDB Board
191Required root node properties:
192 - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
193
182LS2080A SoC 194LS2080A SoC
183Required root node properties: 195Required root node properties:
184 - compatible = "fsl,ls2080a"; 196 - compatible = "fsl,ls2080a";
@@ -195,3 +207,14 @@ LS2080A ARMv8 based RDB Board
195Required root node properties: 207Required root node properties:
196 - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; 208 - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
197 209
210LS2088A SoC
211Required root node properties:
212 - compatible = "fsl,ls2088a";
213
214LS2088A ARMv8 based QDS Board
215Required root node properties:
216 - compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
217
218LS2088A ARMv8 based RDB Board
219Required root node properties:
220 - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f229a7..6ed469c66b32 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -35,6 +35,7 @@ Required properties:
35 * "fsl,ls1021a-clockgen" 35 * "fsl,ls1021a-clockgen"
36 * "fsl,ls1043a-clockgen" 36 * "fsl,ls1043a-clockgen"
37 * "fsl,ls1046a-clockgen" 37 * "fsl,ls1046a-clockgen"
38 * "fsl,ls1088a-clockgen"
38 * "fsl,ls2080a-clockgen" 39 * "fsl,ls2080a-clockgen"
39 Chassis-version clock strings include: 40 Chassis-version clock strings include:
40 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks 41 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 39db645b268e..72c4b525726f 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -5,9 +5,13 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
5dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb 5dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
6dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb 6dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
7dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb 7dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
8dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
9dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
8dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb 10dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
9dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb 11dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
10dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb 12dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
13dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
14dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
11 15
12always := $(dtb-y) 16always := $(dtb-y)
13subdir-y := $(dts-dirs) 17subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
index a619f6496a4c..17fae8112e4d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -113,3 +113,7 @@
113&sai2 { 113&sai2 {
114 status = "okay"; 114 status = "okay";
115}; 115};
116
117&sata {
118 status = "okay";
119};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index 14a67f1709e7..e2a93d53d3d8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -126,3 +126,7 @@
126&sai2 { 126&sai2 {
127 status = "okay"; 127 status = "okay";
128}; 128};
129
130&sata {
131 status = "okay";
132};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
index 62c5c7123a15..ed77f6b0937b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -57,3 +57,7 @@
57&i2c0 { 57&i2c0 {
58 status = "okay"; 58 status = "okay";
59}; 59};
60
61&sata {
62 status = "okay";
63};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index cffebb4b3df1..b497ac196ccc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -42,7 +42,8 @@
42 * OTHER DEALINGS IN THE SOFTWARE. 42 * OTHER DEALINGS IN THE SOFTWARE.
43 */ 43 */
44 44
45#include <dt-bindings/interrupt-controller/irq.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/thermal/thermal.h>
46 47
47/ { 48/ {
48 compatible = "fsl,ls1012a"; 49 compatible = "fsl,ls1012a";
@@ -50,6 +51,15 @@
50 #address-cells = <2>; 51 #address-cells = <2>;
51 #size-cells = <2>; 52 #size-cells = <2>;
52 53
54 aliases {
55 crypto = &crypto;
56 rtic_a = &rtic_a;
57 rtic_b = &rtic_b;
58 rtic_c = &rtic_c;
59 rtic_d = &rtic_d;
60 sec_mon = &sec_mon;
61 };
62
53 cpus { 63 cpus {
54 #address-cells = <1>; 64 #address-cells = <1>;
55 #size-cells = <0>; 65 #size-cells = <0>;
@@ -113,6 +123,95 @@
113 big-endian; 123 big-endian;
114 }; 124 };
115 125
126 crypto: crypto@1700000 {
127 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
128 "fsl,sec-v4.0";
129 fsl,sec-era = <8>;
130 #address-cells = <1>;
131 #size-cells = <1>;
132 ranges = <0x0 0x00 0x1700000 0x100000>;
133 reg = <0x00 0x1700000 0x0 0x100000>;
134 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
135
136 sec_jr0: jr@10000 {
137 compatible = "fsl,sec-v5.4-job-ring",
138 "fsl,sec-v5.0-job-ring",
139 "fsl,sec-v4.0-job-ring";
140 reg = <0x10000 0x10000>;
141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 };
143
144 sec_jr1: jr@20000 {
145 compatible = "fsl,sec-v5.4-job-ring",
146 "fsl,sec-v5.0-job-ring",
147 "fsl,sec-v4.0-job-ring";
148 reg = <0x20000 0x10000>;
149 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 sec_jr2: jr@30000 {
153 compatible = "fsl,sec-v5.4-job-ring",
154 "fsl,sec-v5.0-job-ring",
155 "fsl,sec-v4.0-job-ring";
156 reg = <0x30000 0x10000>;
157 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
158 };
159
160 sec_jr3: jr@40000 {
161 compatible = "fsl,sec-v5.4-job-ring",
162 "fsl,sec-v5.0-job-ring",
163 "fsl,sec-v4.0-job-ring";
164 reg = <0x40000 0x10000>;
165 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
166 };
167
168 rtic@60000 {
169 compatible = "fsl,sec-v5.4-rtic",
170 "fsl,sec-v5.0-rtic",
171 "fsl,sec-v4.0-rtic";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x60000 0x100 0x60e00 0x18>;
175 ranges = <0x0 0x60100 0x500>;
176
177 rtic_a: rtic-a@0 {
178 compatible = "fsl,sec-v5.4-rtic-memory",
179 "fsl,sec-v5.0-rtic-memory",
180 "fsl,sec-v4.0-rtic-memory";
181 reg = <0x00 0x20 0x100 0x100>;
182 };
183
184 rtic_b: rtic-b@20 {
185 compatible = "fsl,sec-v5.4-rtic-memory",
186 "fsl,sec-v5.0-rtic-memory",
187 "fsl,sec-v4.0-rtic-memory";
188 reg = <0x20 0x20 0x200 0x100>;
189 };
190
191 rtic_c: rtic-c@40 {
192 compatible = "fsl,sec-v5.4-rtic-memory",
193 "fsl,sec-v5.0-rtic-memory",
194 "fsl,sec-v4.0-rtic-memory";
195 reg = <0x40 0x20 0x300 0x100>;
196 };
197
198 rtic_d: rtic-d@60 {
199 compatible = "fsl,sec-v5.4-rtic-memory",
200 "fsl,sec-v5.0-rtic-memory",
201 "fsl,sec-v4.0-rtic-memory";
202 reg = <0x60 0x20 0x400 0x100>;
203 };
204 };
205 };
206
207 sec_mon: sec_mon@1e90000 {
208 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
209 "fsl,sec-v4.0-mon";
210 reg = <0x0 0x1e90000 0x0 0x10000>;
211 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
116 dcfg: dcfg@1ee0000 { 215 dcfg: dcfg@1ee0000 {
117 compatible = "fsl,ls1012a-dcfg", 216 compatible = "fsl,ls1012a-dcfg",
118 "syscon"; 217 "syscon";
@@ -127,6 +226,82 @@
127 clocks = <&sysclk>; 226 clocks = <&sysclk>;
128 }; 227 };
129 228
229 tmu: tmu@1f00000 {
230 compatible = "fsl,qoriq-tmu";
231 reg = <0x0 0x1f00000 0x0 0x10000>;
232 interrupts = <0 33 0x4>;
233 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
234 fsl,tmu-calibration = <0x00000000 0x00000026
235 0x00000001 0x0000002d
236 0x00000002 0x00000032
237 0x00000003 0x00000039
238 0x00000004 0x0000003f
239 0x00000005 0x00000046
240 0x00000006 0x0000004d
241 0x00000007 0x00000054
242 0x00000008 0x0000005a
243 0x00000009 0x00000061
244 0x0000000a 0x0000006a
245 0x0000000b 0x00000071
246
247 0x00010000 0x00000025
248 0x00010001 0x0000002c
249 0x00010002 0x00000035
250 0x00010003 0x0000003d
251 0x00010004 0x00000045
252 0x00010005 0x0000004e
253 0x00010006 0x00000057
254 0x00010007 0x00000061
255 0x00010008 0x0000006b
256 0x00010009 0x00000076
257
258 0x00020000 0x00000029
259 0x00020001 0x00000033
260 0x00020002 0x0000003d
261 0x00020003 0x00000049
262 0x00020004 0x00000056
263 0x00020005 0x00000061
264 0x00020006 0x0000006d
265
266 0x00030000 0x00000021
267 0x00030001 0x0000002a
268 0x00030002 0x0000003c
269 0x00030003 0x0000004e>;
270 big-endian;
271 #thermal-sensor-cells = <1>;
272 };
273
274 thermal-zones {
275 cpu_thermal: cpu-thermal {
276 polling-delay-passive = <1000>;
277 polling-delay = <5000>;
278 thermal-sensors = <&tmu 0>;
279
280 trips {
281 cpu_alert: cpu-alert {
282 temperature = <85000>;
283 hysteresis = <2000>;
284 type = "passive";
285 };
286
287 cpu_crit: cpu-crit {
288 temperature = <95000>;
289 hysteresis = <2000>;
290 type = "critical";
291 };
292 };
293
294 cooling-maps {
295 map0 {
296 trip = <&cpu_alert>;
297 cooling-device =
298 <&cpu0 THERMAL_NO_LIMIT
299 THERMAL_NO_LIMIT>;
300 };
301 };
302 };
303 };
304
130 i2c0: i2c@2180000 { 305 i2c0: i2c@2180000 {
131 compatible = "fsl,vf610-i2c"; 306 compatible = "fsl,vf610-i2c";
132 #address-cells = <1>; 307 #address-cells = <1>;
@@ -238,9 +413,12 @@
238 413
239 sata: sata@3200000 { 414 sata: sata@3200000 {
240 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; 415 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
241 reg = <0x0 0x3200000 0x0 0x10000>; 416 reg = <0x0 0x3200000 0x0 0x10000>,
417 <0x0 0x20140520 0x0 0x4>;
418 reg-names = "ahci", "sata-ecc";
242 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 419 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&clockgen 4 0>; 420 clocks = <&clockgen 4 0>;
421 dma-coherent;
244 status = "disabled"; 422 status = "disabled";
245 }; 423 };
246 }; 424 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index ec13a6ecb754..45cface08cbb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -582,7 +582,9 @@
582 582
583 sata: sata@3200000 { 583 sata: sata@3200000 {
584 compatible = "fsl,ls1043a-ahci"; 584 compatible = "fsl,ls1043a-ahci";
585 reg = <0x0 0x3200000 0x0 0x10000>; 585 reg = <0x0 0x3200000 0x0 0x10000>,
586 <0x0 0x20140520 0x0 0x4>;
587 reg-names = "ahci", "sata-ecc";
586 interrupts = <0 69 0x4>; 588 interrupts = <0 69 0x4>;
587 clocks = <&clockgen 4 0>; 589 clocks = <&clockgen 4 0>;
588 dma-coherent; 590 dma-coherent;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 4a164b801882..f4b8b7edaf9d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -587,7 +587,9 @@
587 587
588 sata: sata@3200000 { 588 sata: sata@3200000 {
589 compatible = "fsl,ls1046a-ahci"; 589 compatible = "fsl,ls1046a-ahci";
590 reg = <0x0 0x3200000 0x0 0x10000>; 590 reg = <0x0 0x3200000 0x0 0x10000>,
591 <0x0 0x20140520 0x0 0x4>;
592 reg-names = "ahci", "sata-ecc";
591 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 593 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clockgen 4 1>; 594 clocks = <&clockgen 4 1>;
593 }; 595 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
new file mode 100644
index 000000000000..8c3cae530f8f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
@@ -0,0 +1,123 @@
1/*
2 * Device Tree file for NXP LS1088A QDS Board.
3 *
4 * Copyright 2017 NXP
5 *
6 * Harninder Rai <harninder.rai@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls1088a.dtsi"
50
51/ {
52 model = "LS1088A QDS Board";
53 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
54};
55
56&i2c0 {
57 status = "okay";
58
59 i2c-switch@77 {
60 compatible = "nxp,pca9547";
61 reg = <0x77>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 i2c@2 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = <0x2>;
69
70 ina220@40 {
71 compatible = "ti,ina220";
72 reg = <0x40>;
73 shunt-resistor = <1000>;
74 };
75
76 ina220@41 {
77 compatible = "ti,ina220";
78 reg = <0x41>;
79 shunt-resistor = <1000>;
80 };
81 };
82
83 i2c@3 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0x3>;
87
88 temp-sensor@4c {
89 compatible = "adi,adt7461a";
90 reg = <0x4c>;
91 };
92
93 rtc@51 {
94 compatible = "nxp,pcf2129";
95 reg = <0x51>;
96 /* IRQ10_B */
97 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
98 };
99
100 eeprom@56 {
101 compatible = "atmel,24c512";
102 reg = <0x56>;
103 };
104
105 eeprom@57 {
106 compatible = "atmel,24c512";
107 reg = <0x57>;
108 };
109 };
110 };
111};
112
113&duart0 {
114 status = "okay";
115};
116
117&duart1 {
118 status = "okay";
119};
120
121&sata {
122 status = "okay";
123};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
new file mode 100644
index 000000000000..8a04fbb25cb4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -0,0 +1,107 @@
1/*
2 * Device Tree file for NXP LS1088A RDB Board.
3 *
4 * Copyright 2017 NXP
5 *
6 * Harninder Rai <harninder.rai@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls1088a.dtsi"
50
51/ {
52 model = "L1088A RDB Board";
53 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
54};
55
56&i2c0 {
57 status = "okay";
58
59 i2c-switch@77 {
60 compatible = "nxp,pca9547";
61 reg = <0x77>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 i2c@2 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = <0x2>;
69
70 ina220@40 {
71 compatible = "ti,ina220";
72 reg = <0x40>;
73 shunt-resistor = <1000>;
74 };
75 };
76
77 i2c@3 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0x3>;
81
82 temp-sensor@4c {
83 compatible = "adi,adt7461a";
84 reg = <0x4c>;
85 };
86
87 rtc@51 {
88 compatible = "nxp,pcf2129";
89 reg = <0x51>;
90 /* IRQ10_B */
91 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
92 };
93 };
94 };
95};
96
97&duart0 {
98 status = "okay";
99};
100
101&duart1 {
102 status = "okay";
103};
104
105&sata {
106 status = "okay";
107};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
new file mode 100644
index 000000000000..2946fd797121
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -0,0 +1,275 @@
1/*
2 * Device Tree Include file for NXP Layerscape-1088A family SoC.
3 *
4 * Copyright 2017 NXP
5 *
6 * Harninder Rai <harninder.rai@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46#include <dt-bindings/interrupt-controller/arm-gic.h>
47
48/ {
49 compatible = "fsl,ls1088a";
50 interrupt-parent = <&gic>;
51 #address-cells = <2>;
52 #size-cells = <2>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 /* We have 2 clusters having 4 Cortex-A53 cores each */
59 cpu0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clocks = <&clockgen 1 0>;
64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a53";
69 reg = <0x1>;
70 clocks = <&clockgen 1 0>;
71 };
72
73 cpu2: cpu@2 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a53";
76 reg = <0x2>;
77 clocks = <&clockgen 1 0>;
78 };
79
80 cpu3: cpu@3 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a53";
83 reg = <0x3>;
84 clocks = <&clockgen 1 0>;
85 };
86
87 cpu4: cpu@100 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x100>;
91 clocks = <&clockgen 1 1>;
92 };
93
94 cpu5: cpu@101 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a53";
97 reg = <0x101>;
98 clocks = <&clockgen 1 1>;
99 };
100
101 cpu6: cpu@102 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a53";
104 reg = <0x102>;
105 clocks = <&clockgen 1 1>;
106 };
107
108 cpu7: cpu@103 {
109 device_type = "cpu";
110 compatible = "arm,cortex-a53";
111 reg = <0x103>;
112 clocks = <&clockgen 1 1>;
113 };
114 };
115
116 gic: interrupt-controller@6000000 {
117 compatible = "arm,gic-v3";
118 #interrupt-cells = <3>;
119 interrupt-controller;
120 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
121 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
122 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
123 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
124 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
125 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
128 timer {
129 compatible = "arm,armv8-timer";
130 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
131 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
132 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
133 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
134 };
135
136 sysclk: sysclk {
137 compatible = "fixed-clock";
138 #clock-cells = <0>;
139 clock-frequency = <100000000>;
140 clock-output-names = "sysclk";
141 };
142
143 soc {
144 compatible = "simple-bus";
145 #address-cells = <2>;
146 #size-cells = <2>;
147 ranges;
148
149 clockgen: clocking@1300000 {
150 compatible = "fsl,ls1088a-clockgen";
151 reg = <0 0x1300000 0 0xa0000>;
152 #clock-cells = <2>;
153 clocks = <&sysclk>;
154 };
155
156 duart0: serial@21c0500 {
157 compatible = "fsl,ns16550", "ns16550a";
158 reg = <0x0 0x21c0500 0x0 0x100>;
159 clocks = <&clockgen 4 3>;
160 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
161 status = "disabled";
162 };
163
164 duart1: serial@21c0600 {
165 compatible = "fsl,ns16550", "ns16550a";
166 reg = <0x0 0x21c0600 0x0 0x100>;
167 clocks = <&clockgen 4 3>;
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
169 status = "disabled";
170 };
171
172 gpio0: gpio@2300000 {
173 compatible = "fsl,qoriq-gpio";
174 reg = <0x0 0x2300000 0x0 0x10000>;
175 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-controller;
177 #gpio-cells = <2>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 };
181
182 gpio1: gpio@2310000 {
183 compatible = "fsl,qoriq-gpio";
184 reg = <0x0 0x2310000 0x0 0x10000>;
185 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
186 gpio-controller;
187 #gpio-cells = <2>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 };
191
192 gpio2: gpio@2320000 {
193 compatible = "fsl,qoriq-gpio";
194 reg = <0x0 0x2320000 0x0 0x10000>;
195 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 gpio3: gpio@2330000 {
203 compatible = "fsl,qoriq-gpio";
204 reg = <0x0 0x2330000 0x0 0x10000>;
205 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 };
211
212 ifc: ifc@2240000 {
213 compatible = "fsl,ifc", "simple-bus";
214 reg = <0x0 0x2240000 0x0 0x20000>;
215 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
216 little-endian;
217 #address-cells = <2>;
218 #size-cells = <1>;
219
220 ranges = <0 0 0x5 0x80000000 0x08000000
221 2 0 0x5 0x30000000 0x00010000
222 3 0 0x5 0x20000000 0x00010000>;
223 status = "disabled";
224 };
225
226 i2c0: i2c@2000000 {
227 compatible = "fsl,vf610-i2c";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 reg = <0x0 0x2000000 0x0 0x10000>;
231 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&clockgen 4 3>;
233 status = "disabled";
234 };
235
236 i2c1: i2c@2010000 {
237 compatible = "fsl,vf610-i2c";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 reg = <0x0 0x2010000 0x0 0x10000>;
241 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clockgen 4 3>;
243 status = "disabled";
244 };
245
246 i2c2: i2c@2020000 {
247 compatible = "fsl,vf610-i2c";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 reg = <0x0 0x2020000 0x0 0x10000>;
251 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clockgen 4 3>;
253 status = "disabled";
254 };
255
256 i2c3: i2c@2030000 {
257 compatible = "fsl,vf610-i2c";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <0x0 0x2030000 0x0 0x10000>;
261 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clockgen 4 3>;
263 status = "disabled";
264 };
265
266 sata: sata@3200000 {
267 compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
268 reg = <0x0 0x3200000 0x0 0x10000>;
269 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clockgen 4 3>;
271 status = "disabled";
272 };
273 };
274
275};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index 8bc1f8f6fcfc..c1e76dfca48e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -1,8 +1,9 @@
1/* 1/*
2 * Device Tree file for Freescale LS2080a QDS Board. 2 * Device Tree file for Freescale LS2080a QDS Board.
3 * 3 *
4 * Copyright (C) 2015, Freescale Semiconductor 4 * Copyright (C) 2015-17, Freescale Semiconductor
5 * 5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 7 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
7 * 8 *
8 * This file is dual-licensed: you can use it either under the terms 9 * This file is dual-licensed: you can use it either under the terms
@@ -47,6 +48,7 @@
47/dts-v1/; 48/dts-v1/;
48 49
49#include "fsl-ls2080a.dtsi" 50#include "fsl-ls2080a.dtsi"
51#include "fsl-ls208xa-qds.dtsi"
50 52
51/ { 53/ {
52 model = "Freescale Layerscape 2080a QDS Board"; 54 model = "Freescale Layerscape 2080a QDS Board";
@@ -61,154 +63,3 @@
61 stdout-path = "serial0:115200n8"; 63 stdout-path = "serial0:115200n8";
62 }; 64 };
63}; 65};
64
65&esdhc {
66 status = "okay";
67};
68
69&ifc {
70 status = "okay";
71 #address-cells = <2>;
72 #size-cells = <1>;
73 ranges = <0x0 0x0 0x5 0x80000000 0x08000000
74 0x2 0x0 0x5 0x30000000 0x00010000
75 0x3 0x0 0x5 0x20000000 0x00010000>;
76
77 nor@0,0 {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "cfi-flash";
81 reg = <0x0 0x0 0x8000000>;
82 bank-width = <2>;
83 device-width = <1>;
84 };
85
86 nand@2,0 {
87 compatible = "fsl,ifc-nand";
88 reg = <0x2 0x0 0x10000>;
89 };
90
91 cpld@3,0 {
92 reg = <0x3 0x0 0x10000>;
93 compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
94 };
95};
96
97&i2c0 {
98 status = "okay";
99 pca9547@77 {
100 compatible = "nxp,pca9547";
101 reg = <0x77>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 i2c@0 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 reg = <0x00>;
108 rtc@68 {
109 compatible = "dallas,ds3232";
110 reg = <0x68>;
111 };
112 };
113
114 i2c@2 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 reg = <0x02>;
118
119 ina220@40 {
120 compatible = "ti,ina220";
121 reg = <0x40>;
122 shunt-resistor = <500>;
123 };
124
125 ina220@41 {
126 compatible = "ti,ina220";
127 reg = <0x41>;
128 shunt-resistor = <1000>;
129 };
130 };
131
132 i2c@3 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 reg = <0x3>;
136
137 adt7481@4c {
138 compatible = "adi,adt7461";
139 reg = <0x4c>;
140 };
141 };
142 };
143};
144
145&i2c1 {
146 status = "disabled";
147};
148
149&i2c2 {
150 status = "disabled";
151};
152
153&i2c3 {
154 status = "disabled";
155};
156
157&dspi {
158 status = "okay";
159 dflash0: n25q128a {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 compatible = "st,m25p80";
163 spi-max-frequency = <3000000>;
164 reg = <0>;
165 };
166 dflash1: sst25wf040b {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 compatible = "st,m25p80";
170 spi-max-frequency = <3000000>;
171 reg = <1>;
172 };
173 dflash2: en25s64 {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 compatible = "st,m25p80";
177 spi-max-frequency = <3000000>;
178 reg = <2>;
179 };
180};
181
182&qspi {
183 status = "okay";
184 flash0: s25fl256s1@0 {
185 #address-cells = <1>;
186 #size-cells = <1>;
187 compatible = "st,m25p80";
188 spi-max-frequency = <20000000>;
189 reg = <0>;
190 };
191 flash2: s25fl256s1@2 {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 compatible = "st,m25p80";
195 spi-max-frequency = <20000000>;
196 reg = <0>;
197 };
198};
199
200&sata0 {
201 status = "okay";
202};
203
204&sata1 {
205 status = "okay";
206};
207
208&usb0 {
209 status = "okay";
210};
211
212&usb1 {
213 status = "okay";
214};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index 2ff46ca450b1..18ad19587311 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -1,8 +1,9 @@
1/* 1/*
2 * Device Tree file for Freescale LS2080a RDB Board. 2 * Device Tree file for Freescale LS2080a RDB Board.
3 * 3 *
4 * Copyright (C) 2015, Freescale Semiconductor 4 * Copyright (C) 2016-17, Freescale Semiconductor
5 * 5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 7 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
7 * 8 *
8 * This file is dual-licensed: you can use it either under the terms 9 * This file is dual-licensed: you can use it either under the terms
@@ -47,6 +48,7 @@
47/dts-v1/; 48/dts-v1/;
48 49
49#include "fsl-ls2080a.dtsi" 50#include "fsl-ls2080a.dtsi"
51#include "fsl-ls208xa-rdb.dtsi"
50 52
51/ { 53/ {
52 model = "Freescale Layerscape 2080a RDB Board"; 54 model = "Freescale Layerscape 2080a RDB Board";
@@ -61,109 +63,3 @@
61 stdout-path = "serial1:115200n8"; 63 stdout-path = "serial1:115200n8";
62 }; 64 };
63}; 65};
64
65&esdhc {
66 status = "okay";
67};
68
69&ifc {
70 status = "okay";
71 #address-cells = <2>;
72 #size-cells = <1>;
73 ranges = <0x0 0x0 0x5 0x80000000 0x08000000
74 0x2 0x0 0x5 0x30000000 0x00010000
75 0x3 0x0 0x5 0x20000000 0x00010000>;
76
77 nor@0,0 {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "cfi-flash";
81 reg = <0x0 0x0 0x8000000>;
82 bank-width = <2>;
83 device-width = <1>;
84 };
85
86 nand@2,0 {
87 compatible = "fsl,ifc-nand";
88 reg = <0x2 0x0 0x10000>;
89 };
90
91 cpld@3,0 {
92 reg = <0x3 0x0 0x10000>;
93 compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
94 };
95
96};
97
98&i2c0 {
99 status = "okay";
100 pca9547@75 {
101 compatible = "nxp,pca9547";
102 reg = <0x75>;
103 #address-cells = <1>;
104 #size-cells = <0>;
105 i2c@1 {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 reg = <0x01>;
109 rtc@68 {
110 compatible = "dallas,ds3232";
111 reg = <0x68>;
112 };
113 };
114
115 i2c@3 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 reg = <0x3>;
119
120 adt7481@4c {
121 compatible = "adi,adt7461";
122 reg = <0x4c>;
123 };
124 };
125 };
126};
127
128&i2c1 {
129 status = "disabled";
130};
131
132&i2c2 {
133 status = "disabled";
134};
135
136&i2c3 {
137 status = "disabled";
138};
139
140&dspi {
141 status = "okay";
142 dflash0: n25q512a {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "st,m25p80";
146 spi-max-frequency = <3000000>;
147 reg = <0>;
148 };
149};
150
151&qspi {
152 status = "disabled";
153};
154
155&sata0 {
156 status = "okay";
157};
158
159&sata1 {
160 status = "okay";
161};
162
163&usb0 {
164 status = "okay";
165};
166
167&usb1 {
168 status = "okay";
169};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index e5935f28848c..46a26c021421 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -1,8 +1,9 @@
1/* 1/*
2 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 2 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
3 * 3 *
4 * Copyright (C) 2014-2015, Freescale Semiconductor 4 * Copyright (C) 2014-2016, Freescale Semiconductor
5 * 5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 7 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
7 * 8 *
8 * This file is dual-licensed: you can use it either under the terms 9 * This file is dual-licensed: you can use it either under the terms
@@ -44,802 +45,122 @@
44 * OTHER DEALINGS IN THE SOFTWARE. 45 * OTHER DEALINGS IN THE SOFTWARE.
45 */ 46 */
46 47
47#include <dt-bindings/thermal/thermal.h> 48#include "fsl-ls208xa.dtsi"
48 49
49/ { 50&cpu {
50 compatible = "fsl,ls2080a"; 51 cpu0: cpu@0 {
51 interrupt-parent = <&gic>; 52 device_type = "cpu";
52 #address-cells = <2>; 53 compatible = "arm,cortex-a57";
53 #size-cells = <2>; 54 reg = <0x0>;
54 55 clocks = <&clockgen 1 0>;
55 cpus { 56 next-level-cache = <&cluster0_l2>;
56 #address-cells = <1>; 57 #cooling-cells = <2>;
57 #size-cells = <0>;
58
59 /*
60 * We expect the enable-method for cpu's to be "psci", but this
61 * is dependent on the SoC FW, which will fill this in.
62 *
63 * Currently supported enable-method is psci v0.2
64 */
65
66 /* We have 4 clusters having 2 Cortex-A57 cores each */
67 cpu0: cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a57";
70 reg = <0x0>;
71 clocks = <&clockgen 1 0>;
72 next-level-cache = <&cluster0_l2>;
73 #cooling-cells = <2>;
74 };
75
76 cpu1: cpu@1 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a57";
79 reg = <0x1>;
80 clocks = <&clockgen 1 0>;
81 next-level-cache = <&cluster0_l2>;
82 };
83
84 cpu2: cpu@100 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a57";
87 reg = <0x100>;
88 clocks = <&clockgen 1 1>;
89 next-level-cache = <&cluster1_l2>;
90 #cooling-cells = <2>;
91 };
92
93 cpu3: cpu@101 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a57";
96 reg = <0x101>;
97 clocks = <&clockgen 1 1>;
98 next-level-cache = <&cluster1_l2>;
99 };
100
101 cpu4: cpu@200 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a57";
104 reg = <0x200>;
105 clocks = <&clockgen 1 2>;
106 next-level-cache = <&cluster2_l2>;
107 #cooling-cells = <2>;
108 };
109
110 cpu5: cpu@201 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a57";
113 reg = <0x201>;
114 clocks = <&clockgen 1 2>;
115 next-level-cache = <&cluster2_l2>;
116 };
117
118 cpu6: cpu@300 {
119 device_type = "cpu";
120 compatible = "arm,cortex-a57";
121 reg = <0x300>;
122 clocks = <&clockgen 1 3>;
123 next-level-cache = <&cluster3_l2>;
124 #cooling-cells = <2>;
125 };
126
127 cpu7: cpu@301 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a57";
130 reg = <0x301>;
131 clocks = <&clockgen 1 3>;
132 next-level-cache = <&cluster3_l2>;
133 };
134
135 cluster0_l2: l2-cache0 {
136 compatible = "cache";
137 };
138
139 cluster1_l2: l2-cache1 {
140 compatible = "cache";
141 };
142
143 cluster2_l2: l2-cache2 {
144 compatible = "cache";
145 };
146
147 cluster3_l2: l2-cache3 {
148 compatible = "cache";
149 };
150 }; 58 };
151 59
152 memory@80000000 { 60 cpu1: cpu@1 {
153 device_type = "memory"; 61 device_type = "cpu";
154 reg = <0x00000000 0x80000000 0 0x80000000>; 62 compatible = "arm,cortex-a57";
155 /* DRAM space - 1, size : 2 GB DRAM */ 63 reg = <0x1>;
64 clocks = <&clockgen 1 0>;
65 next-level-cache = <&cluster0_l2>;
156 }; 66 };
157 67
158 sysclk: sysclk { 68 cpu2: cpu@100 {
159 compatible = "fixed-clock"; 69 device_type = "cpu";
160 #clock-cells = <0>; 70 compatible = "arm,cortex-a57";
161 clock-frequency = <100000000>; 71 reg = <0x100>;
162 clock-output-names = "sysclk"; 72 clocks = <&clockgen 1 1>;
73 next-level-cache = <&cluster1_l2>;
74 #cooling-cells = <2>;
163 }; 75 };
164 76
165 gic: interrupt-controller@6000000 { 77 cpu3: cpu@101 {
166 compatible = "arm,gic-v3"; 78 device_type = "cpu";
167 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 79 compatible = "arm,cortex-a57";
168 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 80 reg = <0x101>;
169 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 81 clocks = <&clockgen 1 1>;
170 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 82 next-level-cache = <&cluster1_l2>;
171 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
172 #interrupt-cells = <3>;
173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges;
176 interrupt-controller;
177 interrupts = <1 9 0x4>;
178
179 its: gic-its@6020000 {
180 compatible = "arm,gic-v3-its";
181 msi-controller;
182 reg = <0x0 0x6020000 0 0x20000>;
183 };
184 }; 83 };
185 84
186 rstcr: syscon@1e60000 { 85 cpu4: cpu@200 {
187 compatible = "fsl,ls2080a-rstcr", "syscon"; 86 device_type = "cpu";
188 reg = <0x0 0x1e60000 0x0 0x4>; 87 compatible = "arm,cortex-a57";
88 reg = <0x200>;
89 clocks = <&clockgen 1 2>;
90 next-level-cache = <&cluster2_l2>;
91 #cooling-cells = <2>;
189 }; 92 };
190 93
191 reboot { 94 cpu5: cpu@201 {
192 compatible ="syscon-reboot"; 95 device_type = "cpu";
193 regmap = <&rstcr>; 96 compatible = "arm,cortex-a57";
194 offset = <0x0>; 97 reg = <0x201>;
195 mask = <0x2>; 98 clocks = <&clockgen 1 2>;
99 next-level-cache = <&cluster2_l2>;
196 }; 100 };
197 101
198 timer { 102 cpu6: cpu@300 {
199 compatible = "arm,armv8-timer"; 103 device_type = "cpu";
200 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 104 compatible = "arm,cortex-a57";
201 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 105 reg = <0x300>;
202 <1 11 4>, /* Virtual PPI, active-low */ 106 clocks = <&clockgen 1 3>;
203 <1 10 4>; /* Hypervisor PPI, active-low */ 107 next-level-cache = <&cluster3_l2>;
204 fsl,erratum-a008585; 108 #cooling-cells = <2>;
205 }; 109 };
206 110
207 pmu { 111 cpu7: cpu@301 {
208 compatible = "arm,armv8-pmuv3"; 112 device_type = "cpu";
209 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 113 compatible = "arm,cortex-a57";
114 reg = <0x301>;
115 clocks = <&clockgen 1 3>;
116 next-level-cache = <&cluster3_l2>;
210 }; 117 };
211 118
212 soc { 119 cluster0_l2: l2-cache0 {
213 compatible = "simple-bus"; 120 compatible = "cache";
214 #address-cells = <2>; 121 };
215 #size-cells = <2>;
216 ranges;
217
218 clockgen: clocking@1300000 {
219 compatible = "fsl,ls2080a-clockgen";
220 reg = <0 0x1300000 0 0xa0000>;
221 #clock-cells = <2>;
222 clocks = <&sysclk>;
223 };
224
225 dcfg: dcfg@1e00000 {
226 compatible = "fsl,ls2080a-dcfg", "syscon";
227 reg = <0x0 0x1e00000 0x0 0x10000>;
228 little-endian;
229 };
230
231 tmu: tmu@1f80000 {
232 compatible = "fsl,qoriq-tmu";
233 reg = <0x0 0x1f80000 0x0 0x10000>;
234 interrupts = <0 23 0x4>;
235 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
236 fsl,tmu-calibration = <0x00000000 0x00000026
237 0x00000001 0x0000002d
238 0x00000002 0x00000032
239 0x00000003 0x00000039
240 0x00000004 0x0000003f
241 0x00000005 0x00000046
242 0x00000006 0x0000004d
243 0x00000007 0x00000054
244 0x00000008 0x0000005a
245 0x00000009 0x00000061
246 0x0000000a 0x0000006a
247 0x0000000b 0x00000071
248
249 0x00010000 0x00000025
250 0x00010001 0x0000002c
251 0x00010002 0x00000035
252 0x00010003 0x0000003d
253 0x00010004 0x00000045
254 0x00010005 0x0000004e
255 0x00010006 0x00000057
256 0x00010007 0x00000061
257 0x00010008 0x0000006b
258 0x00010009 0x00000076
259
260 0x00020000 0x00000029
261 0x00020001 0x00000033
262 0x00020002 0x0000003d
263 0x00020003 0x00000049
264 0x00020004 0x00000056
265 0x00020005 0x00000061
266 0x00020006 0x0000006d
267
268 0x00030000 0x00000021
269 0x00030001 0x0000002a
270 0x00030002 0x0000003c
271 0x00030003 0x0000004e>;
272 little-endian;
273 #thermal-sensor-cells = <1>;
274 };
275
276 thermal-zones {
277 cpu_thermal: cpu-thermal {
278 polling-delay-passive = <1000>;
279 polling-delay = <5000>;
280
281 thermal-sensors = <&tmu 4>;
282
283 trips {
284 cpu_alert: cpu-alert {
285 temperature = <75000>;
286 hysteresis = <2000>;
287 type = "passive";
288 };
289 cpu_crit: cpu-crit {
290 temperature = <85000>;
291 hysteresis = <2000>;
292 type = "critical";
293 };
294 };
295
296 cooling-maps {
297 map0 {
298 trip = <&cpu_alert>;
299 cooling-device =
300 <&cpu0 THERMAL_NO_LIMIT
301 THERMAL_NO_LIMIT>;
302 };
303 map1 {
304 trip = <&cpu_alert>;
305 cooling-device =
306 <&cpu2 THERMAL_NO_LIMIT
307 THERMAL_NO_LIMIT>;
308 };
309 map2 {
310 trip = <&cpu_alert>;
311 cooling-device =
312 <&cpu4 THERMAL_NO_LIMIT
313 THERMAL_NO_LIMIT>;
314 };
315 map3 {
316 trip = <&cpu_alert>;
317 cooling-device =
318 <&cpu6 THERMAL_NO_LIMIT
319 THERMAL_NO_LIMIT>;
320 };
321 };
322 };
323 };
324
325 serial0: serial@21c0500 {
326 compatible = "fsl,ns16550", "ns16550a";
327 reg = <0x0 0x21c0500 0x0 0x100>;
328 clocks = <&clockgen 4 3>;
329 interrupts = <0 32 0x4>; /* Level high type */
330 };
331
332 serial1: serial@21c0600 {
333 compatible = "fsl,ns16550", "ns16550a";
334 reg = <0x0 0x21c0600 0x0 0x100>;
335 clocks = <&clockgen 4 3>;
336 interrupts = <0 32 0x4>; /* Level high type */
337 };
338
339 cluster1_core0_watchdog: wdt@c000000 {
340 compatible = "arm,sp805-wdt", "arm,primecell";
341 reg = <0x0 0xc000000 0x0 0x1000>;
342 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
343 clock-names = "apb_pclk", "wdog_clk";
344 };
345
346 cluster1_core1_watchdog: wdt@c010000 {
347 compatible = "arm,sp805-wdt", "arm,primecell";
348 reg = <0x0 0xc010000 0x0 0x1000>;
349 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
350 clock-names = "apb_pclk", "wdog_clk";
351 };
352
353 cluster2_core0_watchdog: wdt@c100000 {
354 compatible = "arm,sp805-wdt", "arm,primecell";
355 reg = <0x0 0xc100000 0x0 0x1000>;
356 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
357 clock-names = "apb_pclk", "wdog_clk";
358 };
359
360 cluster2_core1_watchdog: wdt@c110000 {
361 compatible = "arm,sp805-wdt", "arm,primecell";
362 reg = <0x0 0xc110000 0x0 0x1000>;
363 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
364 clock-names = "apb_pclk", "wdog_clk";
365 };
366
367 cluster3_core0_watchdog: wdt@c200000 {
368 compatible = "arm,sp805-wdt", "arm,primecell";
369 reg = <0x0 0xc200000 0x0 0x1000>;
370 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
371 clock-names = "apb_pclk", "wdog_clk";
372 };
373
374 cluster3_core1_watchdog: wdt@c210000 {
375 compatible = "arm,sp805-wdt", "arm,primecell";
376 reg = <0x0 0xc210000 0x0 0x1000>;
377 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
378 clock-names = "apb_pclk", "wdog_clk";
379 };
380
381 cluster4_core0_watchdog: wdt@c300000 {
382 compatible = "arm,sp805-wdt", "arm,primecell";
383 reg = <0x0 0xc300000 0x0 0x1000>;
384 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
385 clock-names = "apb_pclk", "wdog_clk";
386 };
387
388 cluster4_core1_watchdog: wdt@c310000 {
389 compatible = "arm,sp805-wdt", "arm,primecell";
390 reg = <0x0 0xc310000 0x0 0x1000>;
391 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
392 clock-names = "apb_pclk", "wdog_clk";
393 };
394
395 fsl_mc: fsl-mc@80c000000 {
396 compatible = "fsl,qoriq-mc";
397 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
398 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
399 msi-parent = <&its>;
400 #address-cells = <3>;
401 #size-cells = <1>;
402
403 /*
404 * Region type 0x0 - MC portals
405 * Region type 0x1 - QBMAN portals
406 */
407 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
408 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
409
410 /*
411 * Define the maximum number of MACs present on the SoC.
412 */
413 dpmacs {
414 #address-cells = <1>;
415 #size-cells = <0>;
416
417 dpmac1: dpmac@1 {
418 compatible = "fsl,qoriq-mc-dpmac";
419 reg = <0x1>;
420 };
421
422 dpmac2: dpmac@2 {
423 compatible = "fsl,qoriq-mc-dpmac";
424 reg = <0x2>;
425 };
426
427 dpmac3: dpmac@3 {
428 compatible = "fsl,qoriq-mc-dpmac";
429 reg = <0x3>;
430 };
431
432 dpmac4: dpmac@4 {
433 compatible = "fsl,qoriq-mc-dpmac";
434 reg = <0x4>;
435 };
436
437 dpmac5: dpmac@5 {
438 compatible = "fsl,qoriq-mc-dpmac";
439 reg = <0x5>;
440 };
441
442 dpmac6: dpmac@6 {
443 compatible = "fsl,qoriq-mc-dpmac";
444 reg = <0x6>;
445 };
446
447 dpmac7: dpmac@7 {
448 compatible = "fsl,qoriq-mc-dpmac";
449 reg = <0x7>;
450 };
451
452 dpmac8: dpmac@8 {
453 compatible = "fsl,qoriq-mc-dpmac";
454 reg = <0x8>;
455 };
456
457 dpmac9: dpmac@9 {
458 compatible = "fsl,qoriq-mc-dpmac";
459 reg = <0x9>;
460 };
461
462 dpmac10: dpmac@a {
463 compatible = "fsl,qoriq-mc-dpmac";
464 reg = <0xa>;
465 };
466
467 dpmac11: dpmac@b {
468 compatible = "fsl,qoriq-mc-dpmac";
469 reg = <0xb>;
470 };
471
472 dpmac12: dpmac@c {
473 compatible = "fsl,qoriq-mc-dpmac";
474 reg = <0xc>;
475 };
476
477 dpmac13: dpmac@d {
478 compatible = "fsl,qoriq-mc-dpmac";
479 reg = <0xd>;
480 };
481
482 dpmac14: dpmac@e {
483 compatible = "fsl,qoriq-mc-dpmac";
484 reg = <0xe>;
485 };
486
487 dpmac15: dpmac@f {
488 compatible = "fsl,qoriq-mc-dpmac";
489 reg = <0xf>;
490 };
491
492 dpmac16: dpmac@10 {
493 compatible = "fsl,qoriq-mc-dpmac";
494 reg = <0x10>;
495 };
496 };
497 };
498
499 smmu: iommu@5000000 {
500 compatible = "arm,mmu-500";
501 reg = <0 0x5000000 0 0x800000>;
502 #global-interrupts = <12>;
503 interrupts = <0 13 4>, /* global secure fault */
504 <0 14 4>, /* combined secure interrupt */
505 <0 15 4>, /* global non-secure fault */
506 <0 16 4>, /* combined non-secure interrupt */
507 /* performance counter interrupts 0-7 */
508 <0 211 4>, <0 212 4>,
509 <0 213 4>, <0 214 4>,
510 <0 215 4>, <0 216 4>,
511 <0 217 4>, <0 218 4>,
512 /* per context interrupt, 64 interrupts */
513 <0 146 4>, <0 147 4>,
514 <0 148 4>, <0 149 4>,
515 <0 150 4>, <0 151 4>,
516 <0 152 4>, <0 153 4>,
517 <0 154 4>, <0 155 4>,
518 <0 156 4>, <0 157 4>,
519 <0 158 4>, <0 159 4>,
520 <0 160 4>, <0 161 4>,
521 <0 162 4>, <0 163 4>,
522 <0 164 4>, <0 165 4>,
523 <0 166 4>, <0 167 4>,
524 <0 168 4>, <0 169 4>,
525 <0 170 4>, <0 171 4>,
526 <0 172 4>, <0 173 4>,
527 <0 174 4>, <0 175 4>,
528 <0 176 4>, <0 177 4>,
529 <0 178 4>, <0 179 4>,
530 <0 180 4>, <0 181 4>,
531 <0 182 4>, <0 183 4>,
532 <0 184 4>, <0 185 4>,
533 <0 186 4>, <0 187 4>,
534 <0 188 4>, <0 189 4>,
535 <0 190 4>, <0 191 4>,
536 <0 192 4>, <0 193 4>,
537 <0 194 4>, <0 195 4>,
538 <0 196 4>, <0 197 4>,
539 <0 198 4>, <0 199 4>,
540 <0 200 4>, <0 201 4>,
541 <0 202 4>, <0 203 4>,
542 <0 204 4>, <0 205 4>,
543 <0 206 4>, <0 207 4>,
544 <0 208 4>, <0 209 4>;
545 mmu-masters = <&fsl_mc 0x300 0>;
546 };
547
548 dspi: dspi@2100000 {
549 status = "disabled";
550 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
551 #address-cells = <1>;
552 #size-cells = <0>;
553 reg = <0x0 0x2100000 0x0 0x10000>;
554 interrupts = <0 26 0x4>; /* Level high type */
555 clocks = <&clockgen 4 3>;
556 clock-names = "dspi";
557 spi-num-chipselects = <5>;
558 bus-num = <0>;
559 };
560
561 esdhc: esdhc@2140000 {
562 status = "disabled";
563 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
564 reg = <0x0 0x2140000 0x0 0x10000>;
565 interrupts = <0 28 0x4>; /* Level high type */
566 clock-frequency = <0>; /* Updated by bootloader */
567 voltage-ranges = <1800 1800 3300 3300>;
568 sdhci,auto-cmd12;
569 little-endian;
570 bus-width = <4>;
571 };
572
573 gpio0: gpio@2300000 {
574 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
575 reg = <0x0 0x2300000 0x0 0x10000>;
576 interrupts = <0 36 0x4>; /* Level high type */
577 gpio-controller;
578 little-endian;
579 #gpio-cells = <2>;
580 interrupt-controller;
581 #interrupt-cells = <2>;
582 };
583
584 gpio1: gpio@2310000 {
585 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
586 reg = <0x0 0x2310000 0x0 0x10000>;
587 interrupts = <0 36 0x4>; /* Level high type */
588 gpio-controller;
589 little-endian;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 };
594
595 gpio2: gpio@2320000 {
596 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
597 reg = <0x0 0x2320000 0x0 0x10000>;
598 interrupts = <0 37 0x4>; /* Level high type */
599 gpio-controller;
600 little-endian;
601 #gpio-cells = <2>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
604 };
605
606 gpio3: gpio@2330000 {
607 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
608 reg = <0x0 0x2330000 0x0 0x10000>;
609 interrupts = <0 37 0x4>; /* Level high type */
610 gpio-controller;
611 little-endian;
612 #gpio-cells = <2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 };
616
617 i2c0: i2c@2000000 {
618 status = "disabled";
619 compatible = "fsl,vf610-i2c";
620 #address-cells = <1>;
621 #size-cells = <0>;
622 reg = <0x0 0x2000000 0x0 0x10000>;
623 interrupts = <0 34 0x4>; /* Level high type */
624 clock-names = "i2c";
625 clocks = <&clockgen 4 3>;
626 };
627
628 i2c1: i2c@2010000 {
629 status = "disabled";
630 compatible = "fsl,vf610-i2c";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 reg = <0x0 0x2010000 0x0 0x10000>;
634 interrupts = <0 34 0x4>; /* Level high type */
635 clock-names = "i2c";
636 clocks = <&clockgen 4 3>;
637 };
638
639 i2c2: i2c@2020000 {
640 status = "disabled";
641 compatible = "fsl,vf610-i2c";
642 #address-cells = <1>;
643 #size-cells = <0>;
644 reg = <0x0 0x2020000 0x0 0x10000>;
645 interrupts = <0 35 0x4>; /* Level high type */
646 clock-names = "i2c";
647 clocks = <&clockgen 4 3>;
648 };
649
650 i2c3: i2c@2030000 {
651 status = "disabled";
652 compatible = "fsl,vf610-i2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
655 reg = <0x0 0x2030000 0x0 0x10000>;
656 interrupts = <0 35 0x4>; /* Level high type */
657 clock-names = "i2c";
658 clocks = <&clockgen 4 3>;
659 };
660
661 ifc: ifc@2240000 {
662 compatible = "fsl,ifc", "simple-bus";
663 reg = <0x0 0x2240000 0x0 0x20000>;
664 interrupts = <0 21 0x4>; /* Level high type */
665 little-endian;
666 #address-cells = <2>;
667 #size-cells = <1>;
668
669 ranges = <0 0 0x5 0x80000000 0x08000000
670 2 0 0x5 0x30000000 0x00010000
671 3 0 0x5 0x20000000 0x00010000>;
672 };
673
674 qspi: quadspi@20c0000 {
675 status = "disabled";
676 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
677 #address-cells = <1>;
678 #size-cells = <0>;
679 reg = <0x0 0x20c0000 0x0 0x10000>,
680 <0x0 0x20000000 0x0 0x10000000>;
681 reg-names = "QuadSPI", "QuadSPI-memory";
682 interrupts = <0 25 0x4>; /* Level high type */
683 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
684 clock-names = "qspi_en", "qspi";
685 };
686 122
687 pcie@3400000 { 123 cluster1_l2: l2-cache1 {
688 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 124 compatible = "cache";
689 "snps,dw-pcie"; 125 };
690 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
691 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
692 reg-names = "regs", "config";
693 interrupts = <0 108 0x4>; /* Level high type */
694 interrupt-names = "intr";
695 #address-cells = <3>;
696 #size-cells = <2>;
697 device_type = "pci";
698 dma-coherent;
699 num-lanes = <4>;
700 bus-range = <0x0 0xff>;
701 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
702 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
703 msi-parent = <&its>;
704 #interrupt-cells = <1>;
705 interrupt-map-mask = <0 0 0 7>;
706 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
707 <0000 0 0 2 &gic 0 0 0 110 4>,
708 <0000 0 0 3 &gic 0 0 0 111 4>,
709 <0000 0 0 4 &gic 0 0 0 112 4>;
710 };
711 126
712 pcie@3500000 { 127 cluster2_l2: l2-cache2 {
713 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 128 compatible = "cache";
714 "snps,dw-pcie"; 129 };
715 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
716 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
717 reg-names = "regs", "config";
718 interrupts = <0 113 0x4>; /* Level high type */
719 interrupt-names = "intr";
720 #address-cells = <3>;
721 #size-cells = <2>;
722 device_type = "pci";
723 dma-coherent;
724 num-lanes = <4>;
725 bus-range = <0x0 0xff>;
726 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
727 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
728 msi-parent = <&its>;
729 #interrupt-cells = <1>;
730 interrupt-map-mask = <0 0 0 7>;
731 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
732 <0000 0 0 2 &gic 0 0 0 115 4>,
733 <0000 0 0 3 &gic 0 0 0 116 4>,
734 <0000 0 0 4 &gic 0 0 0 117 4>;
735 };
736 130
737 pcie@3600000 { 131 cluster3_l2: l2-cache3 {
738 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 132 compatible = "cache";
739 "snps,dw-pcie"; 133 };
740 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 134};
741 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
742 reg-names = "regs", "config";
743 interrupts = <0 118 0x4>; /* Level high type */
744 interrupt-names = "intr";
745 #address-cells = <3>;
746 #size-cells = <2>;
747 device_type = "pci";
748 dma-coherent;
749 num-lanes = <8>;
750 bus-range = <0x0 0xff>;
751 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
752 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
753 msi-parent = <&its>;
754 #interrupt-cells = <1>;
755 interrupt-map-mask = <0 0 0 7>;
756 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
757 <0000 0 0 2 &gic 0 0 0 120 4>,
758 <0000 0 0 3 &gic 0 0 0 121 4>,
759 <0000 0 0 4 &gic 0 0 0 122 4>;
760 };
761 135
762 pcie@3700000 { 136&pcie1 {
763 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 137 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
764 "snps,dw-pcie"; 138 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
765 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
766 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
767 reg-names = "regs", "config";
768 interrupts = <0 123 0x4>; /* Level high type */
769 interrupt-names = "intr";
770 #address-cells = <3>;
771 #size-cells = <2>;
772 device_type = "pci";
773 dma-coherent;
774 num-lanes = <4>;
775 bus-range = <0x0 0xff>;
776 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
777 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
778 msi-parent = <&its>;
779 #interrupt-cells = <1>;
780 interrupt-map-mask = <0 0 0 7>;
781 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
782 <0000 0 0 2 &gic 0 0 0 125 4>,
783 <0000 0 0 3 &gic 0 0 0 126 4>,
784 <0000 0 0 4 &gic 0 0 0 127 4>;
785 };
786 139
787 sata0: sata@3200000 { 140 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
788 status = "disabled"; 141 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
789 compatible = "fsl,ls2080a-ahci"; 142};
790 reg = <0x0 0x3200000 0x0 0x10000>;
791 interrupts = <0 133 0x4>; /* Level high type */
792 clocks = <&clockgen 4 3>;
793 dma-coherent;
794 };
795 143
796 sata1: sata@3210000 { 144&pcie2 {
797 status = "disabled"; 145 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
798 compatible = "fsl,ls2080a-ahci"; 146 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
799 reg = <0x0 0x3210000 0x0 0x10000>;
800 interrupts = <0 136 0x4>; /* Level high type */
801 clocks = <&clockgen 4 3>;
802 dma-coherent;
803 };
804 147
805 usb0: usb3@3100000 { 148 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
806 status = "disabled"; 149 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
807 compatible = "snps,dwc3"; 150};
808 reg = <0x0 0x3100000 0x0 0x10000>;
809 interrupts = <0 80 0x4>; /* Level high type */
810 dr_mode = "host";
811 snps,quirk-frame-length-adjustment = <0x20>;
812 snps,dis_rxdet_inp3_quirk;
813 };
814 151
815 usb1: usb3@3110000 { 152&pcie3 {
816 status = "disabled"; 153 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
817 compatible = "snps,dwc3"; 154 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
818 reg = <0x0 0x3110000 0x0 0x10000>;
819 interrupts = <0 81 0x4>; /* Level high type */
820 dr_mode = "host";
821 snps,quirk-frame-length-adjustment = <0x20>;
822 snps,dis_rxdet_inp3_quirk;
823 };
824 155
825 ccn@4000000 { 156 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
826 compatible = "arm,ccn-504"; 157 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
827 reg = <0x0 0x04000000 0x0 0x01000000>; 158};
828 interrupts = <0 12 4>;
829 };
830 };
831 159
832 ddr1: memory-controller@1080000 { 160&pcie4 {
833 compatible = "fsl,qoriq-memory-controller"; 161 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
834 reg = <0x0 0x1080000 0x0 0x1000>; 162 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
835 interrupts = <0 17 0x4>;
836 little-endian;
837 };
838 163
839 ddr2: memory-controller@1090000 { 164 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
840 compatible = "fsl,qoriq-memory-controller"; 165 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
841 reg = <0x0 0x1090000 0x0 0x1000>;
842 interrupts = <0 18 0x4>;
843 little-endian;
844 };
845}; 166};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
new file mode 100644
index 000000000000..ebcd6ee4da0d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
@@ -0,0 +1,64 @@
1/*
2 * Device Tree file for Freescale LS2088A QDS Board.
3 *
4 * Copyright (C) 2016-17, Freescale Semiconductor
5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls2088a.dtsi"
50#include "fsl-ls208xa-qds.dtsi"
51
52/ {
53 model = "Freescale Layerscape 2088A QDS Board";
54 compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
55
56 aliases {
57 serial0 = &serial0;
58 serial1 = &serial1;
59 };
60
61 chosen {
62 stdout-path = "serial0:115200n8";
63 };
64};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
new file mode 100644
index 000000000000..5992dc130faa
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
@@ -0,0 +1,64 @@
1/*
2 * Device Tree file for Freescale LS2088A RDB Board.
3 *
4 * Copyright (C) 2016-17, Freescale Semiconductor
5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls2088a.dtsi"
50#include "fsl-ls208xa-rdb.dtsi"
51
52/ {
53 model = "Freescale Layerscape 2088A RDB Board";
54 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
55
56 aliases {
57 serial0 = &serial0;
58 serial1 = &serial1;
59 };
60
61 chosen {
62 stdout-path = "serial1:115200n8";
63 };
64};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
new file mode 100644
index 000000000000..33ce404cf7e4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -0,0 +1,165 @@
1/*
2 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
3 *
4 * Copyright (C) 2016-17, Freescale Semiconductor
5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include "fsl-ls208xa.dtsi"
48
49&cpu {
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a72";
53 reg = <0x0>;
54 clocks = <&clockgen 1 0>;
55 next-level-cache = <&cluster0_l2>;
56 #cooling-cells = <2>;
57 };
58
59 cpu1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a72";
62 reg = <0x1>;
63 clocks = <&clockgen 1 0>;
64 next-level-cache = <&cluster0_l2>;
65 };
66
67 cpu2: cpu@100 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a72";
70 reg = <0x100>;
71 clocks = <&clockgen 1 1>;
72 next-level-cache = <&cluster1_l2>;
73 #cooling-cells = <2>;
74 };
75
76 cpu3: cpu@101 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a72";
79 reg = <0x101>;
80 clocks = <&clockgen 1 1>;
81 next-level-cache = <&cluster1_l2>;
82 };
83
84 cpu4: cpu@200 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a72";
87 reg = <0x200>;
88 clocks = <&clockgen 1 2>;
89 next-level-cache = <&cluster2_l2>;
90 #cooling-cells = <2>;
91 };
92
93 cpu5: cpu@201 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a72";
96 reg = <0x201>;
97 clocks = <&clockgen 1 2>;
98 next-level-cache = <&cluster2_l2>;
99 };
100
101 cpu6: cpu@300 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a72";
104 reg = <0x300>;
105 clocks = <&clockgen 1 3>;
106 next-level-cache = <&cluster3_l2>;
107 #cooling-cells = <2>;
108 };
109
110 cpu7: cpu@301 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a72";
113 reg = <0x301>;
114 clocks = <&clockgen 1 3>;
115 next-level-cache = <&cluster3_l2>;
116 };
117
118 cluster0_l2: l2-cache0 {
119 compatible = "cache";
120 };
121
122 cluster1_l2: l2-cache1 {
123 compatible = "cache";
124 };
125
126 cluster2_l2: l2-cache2 {
127 compatible = "cache";
128 };
129
130 cluster3_l2: l2-cache3 {
131 compatible = "cache";
132 };
133};
134
135&pcie1 {
136 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
137 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
138
139 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
140 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
141};
142
143&pcie2 {
144 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
145 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
146
147 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
148 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
149};
150
151&pcie3 {
152 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
153 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
154
155 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
156 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
157};
158
159&pcie4 {
160 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
161 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
162
163 ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
164 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
165};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
new file mode 100644
index 000000000000..8b6204845973
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
@@ -0,0 +1,196 @@
1/*
2 * Device Tree file for Freescale LS2080A QDS Board.
3 *
4 * Copyright (C) 2016-17, Freescale Semiconductor
5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47&esdhc {
48 status = "okay";
49};
50
51&ifc {
52 status = "okay";
53 #address-cells = <2>;
54 #size-cells = <1>;
55 ranges = <0x0 0x0 0x5 0x80000000 0x08000000
56 0x2 0x0 0x5 0x30000000 0x00010000
57 0x3 0x0 0x5 0x20000000 0x00010000>;
58
59 nor@0,0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "cfi-flash";
63 reg = <0x0 0x0 0x8000000>;
64 bank-width = <2>;
65 device-width = <1>;
66 };
67
68 nand@2,0 {
69 compatible = "fsl,ifc-nand";
70 reg = <0x2 0x0 0x10000>;
71 };
72
73 cpld@3,0 {
74 reg = <0x3 0x0 0x10000>;
75 compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
76 };
77};
78
79&i2c0 {
80 status = "okay";
81 pca9547@77 {
82 compatible = "nxp,pca9547";
83 reg = <0x77>;
84 #address-cells = <1>;
85 #size-cells = <0>;
86 i2c@0 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <0x00>;
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 };
94 };
95
96 i2c@2 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <0x02>;
100
101 ina220@40 {
102 compatible = "ti,ina220";
103 reg = <0x40>;
104 shunt-resistor = <500>;
105 };
106
107 ina220@41 {
108 compatible = "ti,ina220";
109 reg = <0x41>;
110 shunt-resistor = <1000>;
111 };
112 };
113
114 i2c@3 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 reg = <0x3>;
118
119 adt7481@4c {
120 compatible = "adi,adt7461";
121 reg = <0x4c>;
122 };
123 };
124 };
125};
126
127&i2c1 {
128 status = "disabled";
129};
130
131&i2c2 {
132 status = "disabled";
133};
134
135&i2c3 {
136 status = "disabled";
137};
138
139&dspi {
140 status = "okay";
141 dflash0: n25q128a {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "st,m25p80";
145 spi-max-frequency = <3000000>;
146 reg = <0>;
147 };
148 dflash1: sst25wf040b {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "st,m25p80";
152 spi-max-frequency = <3000000>;
153 reg = <1>;
154 };
155 dflash2: en25s64 {
156 #address-cells = <1>;
157 #size-cells = <1>;
158 compatible = "st,m25p80";
159 spi-max-frequency = <3000000>;
160 reg = <2>;
161 };
162};
163
164&qspi {
165 status = "okay";
166 flash0: s25fl256s1@0 {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 compatible = "st,m25p80";
170 spi-max-frequency = <20000000>;
171 reg = <0>;
172 };
173 flash2: s25fl256s1@2 {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 compatible = "st,m25p80";
177 spi-max-frequency = <20000000>;
178 reg = <0>;
179 };
180};
181
182&sata0 {
183 status = "okay";
184};
185
186&sata1 {
187 status = "okay";
188};
189
190&usb0 {
191 status = "okay";
192};
193
194&usb1 {
195 status = "okay";
196};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
new file mode 100644
index 000000000000..3737587ffb33
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -0,0 +1,151 @@
1/*
2 * Device Tree file for Freescale LS2080A RDB Board.
3 *
4 * Copyright (C) 2016-17, Freescale Semiconductor
5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47&esdhc {
48 status = "okay";
49};
50
51&ifc {
52 status = "okay";
53 #address-cells = <2>;
54 #size-cells = <1>;
55 ranges = <0x0 0x0 0x5 0x80000000 0x08000000
56 0x2 0x0 0x5 0x30000000 0x00010000
57 0x3 0x0 0x5 0x20000000 0x00010000>;
58
59 nor@0,0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "cfi-flash";
63 reg = <0x0 0x0 0x8000000>;
64 bank-width = <2>;
65 device-width = <1>;
66 };
67
68 nand@2,0 {
69 compatible = "fsl,ifc-nand";
70 reg = <0x2 0x0 0x10000>;
71 };
72
73 cpld@3,0 {
74 reg = <0x3 0x0 0x10000>;
75 compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
76 };
77
78};
79
80&i2c0 {
81 status = "okay";
82 pca9547@75 {
83 compatible = "nxp,pca9547";
84 reg = <0x75>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 i2c@1 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 reg = <0x01>;
91 rtc@68 {
92 compatible = "dallas,ds3232";
93 reg = <0x68>;
94 };
95 };
96
97 i2c@3 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 reg = <0x3>;
101
102 adt7481@4c {
103 compatible = "adi,adt7461";
104 reg = <0x4c>;
105 };
106 };
107 };
108};
109
110&i2c1 {
111 status = "disabled";
112};
113
114&i2c2 {
115 status = "disabled";
116};
117
118&i2c3 {
119 status = "disabled";
120};
121
122&dspi {
123 status = "okay";
124 dflash0: n25q512a {
125 #address-cells = <1>;
126 #size-cells = <1>;
127 compatible = "st,m25p80";
128 spi-max-frequency = <3000000>;
129 reg = <0>;
130 };
131};
132
133&qspi {
134 status = "disabled";
135};
136
137&sata0 {
138 status = "okay";
139};
140
141&sata1 {
142 status = "okay";
143};
144
145&usb0 {
146 status = "okay";
147};
148
149&usb1 {
150 status = "okay";
151};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
new file mode 100644
index 000000000000..abb2fff7d162
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -0,0 +1,737 @@
1/*
2 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
3 *
4 * Copyright (C) 2016-2017, Freescale Semiconductor
5 *
6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/thermal/thermal.h>
48
49/ {
50 compatible = "fsl,ls2080a";
51 interrupt-parent = <&gic>;
52 #address-cells = <2>;
53 #size-cells = <2>;
54
55 cpu: cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 };
59
60 memory@80000000 {
61 device_type = "memory";
62 reg = <0x00000000 0x80000000 0 0x80000000>;
63 /* DRAM space - 1, size : 2 GB DRAM */
64 };
65
66 sysclk: sysclk {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <100000000>;
70 clock-output-names = "sysclk";
71 };
72
73 gic: interrupt-controller@6000000 {
74 compatible = "arm,gic-v3";
75 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
76 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
77 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
78 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
79 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
80 #interrupt-cells = <3>;
81 #address-cells = <2>;
82 #size-cells = <2>;
83 ranges;
84 interrupt-controller;
85 interrupts = <1 9 0x4>;
86
87 its: gic-its@6020000 {
88 compatible = "arm,gic-v3-its";
89 msi-controller;
90 reg = <0x0 0x6020000 0 0x20000>;
91 };
92 };
93
94 rstcr: syscon@1e60000 {
95 compatible = "fsl,ls2080a-rstcr", "syscon";
96 reg = <0x0 0x1e60000 0x0 0x4>;
97 };
98
99 reboot {
100 compatible ="syscon-reboot";
101 regmap = <&rstcr>;
102 offset = <0x0>;
103 mask = <0x2>;
104 };
105
106 timer {
107 compatible = "arm,armv8-timer";
108 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
109 <1 14 4>, /* Physical Non-Secure PPI, active-low */
110 <1 11 4>, /* Virtual PPI, active-low */
111 <1 10 4>; /* Hypervisor PPI, active-low */
112 fsl,erratum-a008585;
113 };
114
115 pmu {
116 compatible = "arm,armv8-pmuv3";
117 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
118 };
119
120 soc {
121 compatible = "simple-bus";
122 #address-cells = <2>;
123 #size-cells = <2>;
124 ranges;
125
126 clockgen: clocking@1300000 {
127 compatible = "fsl,ls2080a-clockgen";
128 reg = <0 0x1300000 0 0xa0000>;
129 #clock-cells = <2>;
130 clocks = <&sysclk>;
131 };
132
133 dcfg: dcfg@1e00000 {
134 compatible = "fsl,ls2080a-dcfg", "syscon";
135 reg = <0x0 0x1e00000 0x0 0x10000>;
136 little-endian;
137 };
138
139 tmu: tmu@1f80000 {
140 compatible = "fsl,qoriq-tmu";
141 reg = <0x0 0x1f80000 0x0 0x10000>;
142 interrupts = <0 23 0x4>;
143 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
144 fsl,tmu-calibration = <0x00000000 0x00000026
145 0x00000001 0x0000002d
146 0x00000002 0x00000032
147 0x00000003 0x00000039
148 0x00000004 0x0000003f
149 0x00000005 0x00000046
150 0x00000006 0x0000004d
151 0x00000007 0x00000054
152 0x00000008 0x0000005a
153 0x00000009 0x00000061
154 0x0000000a 0x0000006a
155 0x0000000b 0x00000071
156
157 0x00010000 0x00000025
158 0x00010001 0x0000002c
159 0x00010002 0x00000035
160 0x00010003 0x0000003d
161 0x00010004 0x00000045
162 0x00010005 0x0000004e
163 0x00010006 0x00000057
164 0x00010007 0x00000061
165 0x00010008 0x0000006b
166 0x00010009 0x00000076
167
168 0x00020000 0x00000029
169 0x00020001 0x00000033
170 0x00020002 0x0000003d
171 0x00020003 0x00000049
172 0x00020004 0x00000056
173 0x00020005 0x00000061
174 0x00020006 0x0000006d
175
176 0x00030000 0x00000021
177 0x00030001 0x0000002a
178 0x00030002 0x0000003c
179 0x00030003 0x0000004e>;
180 little-endian;
181 #thermal-sensor-cells = <1>;
182 };
183
184 thermal-zones {
185 cpu_thermal: cpu-thermal {
186 polling-delay-passive = <1000>;
187 polling-delay = <5000>;
188
189 thermal-sensors = <&tmu 4>;
190
191 trips {
192 cpu_alert: cpu-alert {
193 temperature = <75000>;
194 hysteresis = <2000>;
195 type = "passive";
196 };
197 cpu_crit: cpu-crit {
198 temperature = <85000>;
199 hysteresis = <2000>;
200 type = "critical";
201 };
202 };
203
204 cooling-maps {
205 map0 {
206 trip = <&cpu_alert>;
207 cooling-device =
208 <&cpu0 THERMAL_NO_LIMIT
209 THERMAL_NO_LIMIT>;
210 };
211 map1 {
212 trip = <&cpu_alert>;
213 cooling-device =
214 <&cpu2 THERMAL_NO_LIMIT
215 THERMAL_NO_LIMIT>;
216 };
217 map2 {
218 trip = <&cpu_alert>;
219 cooling-device =
220 <&cpu4 THERMAL_NO_LIMIT
221 THERMAL_NO_LIMIT>;
222 };
223 map3 {
224 trip = <&cpu_alert>;
225 cooling-device =
226 <&cpu6 THERMAL_NO_LIMIT
227 THERMAL_NO_LIMIT>;
228 };
229 };
230 };
231 };
232
233 serial0: serial@21c0500 {
234 compatible = "fsl,ns16550", "ns16550a";
235 reg = <0x0 0x21c0500 0x0 0x100>;
236 clocks = <&clockgen 4 3>;
237 interrupts = <0 32 0x4>; /* Level high type */
238 };
239
240 serial1: serial@21c0600 {
241 compatible = "fsl,ns16550", "ns16550a";
242 reg = <0x0 0x21c0600 0x0 0x100>;
243 clocks = <&clockgen 4 3>;
244 interrupts = <0 32 0x4>; /* Level high type */
245 };
246
247 cluster1_core0_watchdog: wdt@c000000 {
248 compatible = "arm,sp805-wdt", "arm,primecell";
249 reg = <0x0 0xc000000 0x0 0x1000>;
250 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
251 clock-names = "apb_pclk", "wdog_clk";
252 };
253
254 cluster1_core1_watchdog: wdt@c010000 {
255 compatible = "arm,sp805-wdt", "arm,primecell";
256 reg = <0x0 0xc010000 0x0 0x1000>;
257 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
258 clock-names = "apb_pclk", "wdog_clk";
259 };
260
261 cluster2_core0_watchdog: wdt@c100000 {
262 compatible = "arm,sp805-wdt", "arm,primecell";
263 reg = <0x0 0xc100000 0x0 0x1000>;
264 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
265 clock-names = "apb_pclk", "wdog_clk";
266 };
267
268 cluster2_core1_watchdog: wdt@c110000 {
269 compatible = "arm,sp805-wdt", "arm,primecell";
270 reg = <0x0 0xc110000 0x0 0x1000>;
271 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
272 clock-names = "apb_pclk", "wdog_clk";
273 };
274
275 cluster3_core0_watchdog: wdt@c200000 {
276 compatible = "arm,sp805-wdt", "arm,primecell";
277 reg = <0x0 0xc200000 0x0 0x1000>;
278 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
279 clock-names = "apb_pclk", "wdog_clk";
280 };
281
282 cluster3_core1_watchdog: wdt@c210000 {
283 compatible = "arm,sp805-wdt", "arm,primecell";
284 reg = <0x0 0xc210000 0x0 0x1000>;
285 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
286 clock-names = "apb_pclk", "wdog_clk";
287 };
288
289 cluster4_core0_watchdog: wdt@c300000 {
290 compatible = "arm,sp805-wdt", "arm,primecell";
291 reg = <0x0 0xc300000 0x0 0x1000>;
292 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
293 clock-names = "apb_pclk", "wdog_clk";
294 };
295
296 cluster4_core1_watchdog: wdt@c310000 {
297 compatible = "arm,sp805-wdt", "arm,primecell";
298 reg = <0x0 0xc310000 0x0 0x1000>;
299 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
300 clock-names = "apb_pclk", "wdog_clk";
301 };
302
303 fsl_mc: fsl-mc@80c000000 {
304 compatible = "fsl,qoriq-mc";
305 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
306 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
307 msi-parent = <&its>;
308 #address-cells = <3>;
309 #size-cells = <1>;
310
311 /*
312 * Region type 0x0 - MC portals
313 * Region type 0x1 - QBMAN portals
314 */
315 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
316 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
317
318 /*
319 * Define the maximum number of MACs present on the SoC.
320 */
321 dpmacs {
322 #address-cells = <1>;
323 #size-cells = <0>;
324
325 dpmac1: dpmac@1 {
326 compatible = "fsl,qoriq-mc-dpmac";
327 reg = <0x1>;
328 };
329
330 dpmac2: dpmac@2 {
331 compatible = "fsl,qoriq-mc-dpmac";
332 reg = <0x2>;
333 };
334
335 dpmac3: dpmac@3 {
336 compatible = "fsl,qoriq-mc-dpmac";
337 reg = <0x3>;
338 };
339
340 dpmac4: dpmac@4 {
341 compatible = "fsl,qoriq-mc-dpmac";
342 reg = <0x4>;
343 };
344
345 dpmac5: dpmac@5 {
346 compatible = "fsl,qoriq-mc-dpmac";
347 reg = <0x5>;
348 };
349
350 dpmac6: dpmac@6 {
351 compatible = "fsl,qoriq-mc-dpmac";
352 reg = <0x6>;
353 };
354
355 dpmac7: dpmac@7 {
356 compatible = "fsl,qoriq-mc-dpmac";
357 reg = <0x7>;
358 };
359
360 dpmac8: dpmac@8 {
361 compatible = "fsl,qoriq-mc-dpmac";
362 reg = <0x8>;
363 };
364
365 dpmac9: dpmac@9 {
366 compatible = "fsl,qoriq-mc-dpmac";
367 reg = <0x9>;
368 };
369
370 dpmac10: dpmac@a {
371 compatible = "fsl,qoriq-mc-dpmac";
372 reg = <0xa>;
373 };
374
375 dpmac11: dpmac@b {
376 compatible = "fsl,qoriq-mc-dpmac";
377 reg = <0xb>;
378 };
379
380 dpmac12: dpmac@c {
381 compatible = "fsl,qoriq-mc-dpmac";
382 reg = <0xc>;
383 };
384
385 dpmac13: dpmac@d {
386 compatible = "fsl,qoriq-mc-dpmac";
387 reg = <0xd>;
388 };
389
390 dpmac14: dpmac@e {
391 compatible = "fsl,qoriq-mc-dpmac";
392 reg = <0xe>;
393 };
394
395 dpmac15: dpmac@f {
396 compatible = "fsl,qoriq-mc-dpmac";
397 reg = <0xf>;
398 };
399
400 dpmac16: dpmac@10 {
401 compatible = "fsl,qoriq-mc-dpmac";
402 reg = <0x10>;
403 };
404 };
405 };
406
407 smmu: iommu@5000000 {
408 compatible = "arm,mmu-500";
409 reg = <0 0x5000000 0 0x800000>;
410 #global-interrupts = <12>;
411 interrupts = <0 13 4>, /* global secure fault */
412 <0 14 4>, /* combined secure interrupt */
413 <0 15 4>, /* global non-secure fault */
414 <0 16 4>, /* combined non-secure interrupt */
415 /* performance counter interrupts 0-7 */
416 <0 211 4>, <0 212 4>,
417 <0 213 4>, <0 214 4>,
418 <0 215 4>, <0 216 4>,
419 <0 217 4>, <0 218 4>,
420 /* per context interrupt, 64 interrupts */
421 <0 146 4>, <0 147 4>,
422 <0 148 4>, <0 149 4>,
423 <0 150 4>, <0 151 4>,
424 <0 152 4>, <0 153 4>,
425 <0 154 4>, <0 155 4>,
426 <0 156 4>, <0 157 4>,
427 <0 158 4>, <0 159 4>,
428 <0 160 4>, <0 161 4>,
429 <0 162 4>, <0 163 4>,
430 <0 164 4>, <0 165 4>,
431 <0 166 4>, <0 167 4>,
432 <0 168 4>, <0 169 4>,
433 <0 170 4>, <0 171 4>,
434 <0 172 4>, <0 173 4>,
435 <0 174 4>, <0 175 4>,
436 <0 176 4>, <0 177 4>,
437 <0 178 4>, <0 179 4>,
438 <0 180 4>, <0 181 4>,
439 <0 182 4>, <0 183 4>,
440 <0 184 4>, <0 185 4>,
441 <0 186 4>, <0 187 4>,
442 <0 188 4>, <0 189 4>,
443 <0 190 4>, <0 191 4>,
444 <0 192 4>, <0 193 4>,
445 <0 194 4>, <0 195 4>,
446 <0 196 4>, <0 197 4>,
447 <0 198 4>, <0 199 4>,
448 <0 200 4>, <0 201 4>,
449 <0 202 4>, <0 203 4>,
450 <0 204 4>, <0 205 4>,
451 <0 206 4>, <0 207 4>,
452 <0 208 4>, <0 209 4>;
453 mmu-masters = <&fsl_mc 0x300 0>;
454 };
455
456 dspi: dspi@2100000 {
457 status = "disabled";
458 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 reg = <0x0 0x2100000 0x0 0x10000>;
462 interrupts = <0 26 0x4>; /* Level high type */
463 clocks = <&clockgen 4 3>;
464 clock-names = "dspi";
465 spi-num-chipselects = <5>;
466 bus-num = <0>;
467 };
468
469 esdhc: esdhc@2140000 {
470 status = "disabled";
471 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
472 reg = <0x0 0x2140000 0x0 0x10000>;
473 interrupts = <0 28 0x4>; /* Level high type */
474 clock-frequency = <0>; /* Updated by bootloader */
475 voltage-ranges = <1800 1800 3300 3300>;
476 sdhci,auto-cmd12;
477 little-endian;
478 bus-width = <4>;
479 };
480
481 gpio0: gpio@2300000 {
482 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
483 reg = <0x0 0x2300000 0x0 0x10000>;
484 interrupts = <0 36 0x4>; /* Level high type */
485 gpio-controller;
486 little-endian;
487 #gpio-cells = <2>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 };
491
492 gpio1: gpio@2310000 {
493 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
494 reg = <0x0 0x2310000 0x0 0x10000>;
495 interrupts = <0 36 0x4>; /* Level high type */
496 gpio-controller;
497 little-endian;
498 #gpio-cells = <2>;
499 interrupt-controller;
500 #interrupt-cells = <2>;
501 };
502
503 gpio2: gpio@2320000 {
504 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
505 reg = <0x0 0x2320000 0x0 0x10000>;
506 interrupts = <0 37 0x4>; /* Level high type */
507 gpio-controller;
508 little-endian;
509 #gpio-cells = <2>;
510 interrupt-controller;
511 #interrupt-cells = <2>;
512 };
513
514 gpio3: gpio@2330000 {
515 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
516 reg = <0x0 0x2330000 0x0 0x10000>;
517 interrupts = <0 37 0x4>; /* Level high type */
518 gpio-controller;
519 little-endian;
520 #gpio-cells = <2>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 };
524
525 i2c0: i2c@2000000 {
526 status = "disabled";
527 compatible = "fsl,vf610-i2c";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <0x0 0x2000000 0x0 0x10000>;
531 interrupts = <0 34 0x4>; /* Level high type */
532 clock-names = "i2c";
533 clocks = <&clockgen 4 3>;
534 };
535
536 i2c1: i2c@2010000 {
537 status = "disabled";
538 compatible = "fsl,vf610-i2c";
539 #address-cells = <1>;
540 #size-cells = <0>;
541 reg = <0x0 0x2010000 0x0 0x10000>;
542 interrupts = <0 34 0x4>; /* Level high type */
543 clock-names = "i2c";
544 clocks = <&clockgen 4 3>;
545 };
546
547 i2c2: i2c@2020000 {
548 status = "disabled";
549 compatible = "fsl,vf610-i2c";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 reg = <0x0 0x2020000 0x0 0x10000>;
553 interrupts = <0 35 0x4>; /* Level high type */
554 clock-names = "i2c";
555 clocks = <&clockgen 4 3>;
556 };
557
558 i2c3: i2c@2030000 {
559 status = "disabled";
560 compatible = "fsl,vf610-i2c";
561 #address-cells = <1>;
562 #size-cells = <0>;
563 reg = <0x0 0x2030000 0x0 0x10000>;
564 interrupts = <0 35 0x4>; /* Level high type */
565 clock-names = "i2c";
566 clocks = <&clockgen 4 3>;
567 };
568
569 ifc: ifc@2240000 {
570 compatible = "fsl,ifc", "simple-bus";
571 reg = <0x0 0x2240000 0x0 0x20000>;
572 interrupts = <0 21 0x4>; /* Level high type */
573 little-endian;
574 #address-cells = <2>;
575 #size-cells = <1>;
576
577 ranges = <0 0 0x5 0x80000000 0x08000000
578 2 0 0x5 0x30000000 0x00010000
579 3 0 0x5 0x20000000 0x00010000>;
580 };
581
582 qspi: quadspi@20c0000 {
583 status = "disabled";
584 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
585 #address-cells = <1>;
586 #size-cells = <0>;
587 reg = <0x0 0x20c0000 0x0 0x10000>,
588 <0x0 0x20000000 0x0 0x10000000>;
589 reg-names = "QuadSPI", "QuadSPI-memory";
590 interrupts = <0 25 0x4>; /* Level high type */
591 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
592 clock-names = "qspi_en", "qspi";
593 };
594
595 pcie1: pcie@3400000 {
596 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
597 "snps,dw-pcie";
598 reg-names = "regs", "config";
599 interrupts = <0 108 0x4>; /* Level high type */
600 interrupt-names = "intr";
601 #address-cells = <3>;
602 #size-cells = <2>;
603 device_type = "pci";
604 dma-coherent;
605 num-lanes = <4>;
606 bus-range = <0x0 0xff>;
607 msi-parent = <&its>;
608 #interrupt-cells = <1>;
609 interrupt-map-mask = <0 0 0 7>;
610 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
611 <0000 0 0 2 &gic 0 0 0 110 4>,
612 <0000 0 0 3 &gic 0 0 0 111 4>,
613 <0000 0 0 4 &gic 0 0 0 112 4>;
614 };
615
616 pcie2: pcie@3500000 {
617 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
618 "snps,dw-pcie";
619 reg-names = "regs", "config";
620 interrupts = <0 113 0x4>; /* Level high type */
621 interrupt-names = "intr";
622 #address-cells = <3>;
623 #size-cells = <2>;
624 device_type = "pci";
625 dma-coherent;
626 num-lanes = <4>;
627 bus-range = <0x0 0xff>;
628 msi-parent = <&its>;
629 #interrupt-cells = <1>;
630 interrupt-map-mask = <0 0 0 7>;
631 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
632 <0000 0 0 2 &gic 0 0 0 115 4>,
633 <0000 0 0 3 &gic 0 0 0 116 4>,
634 <0000 0 0 4 &gic 0 0 0 117 4>;
635 };
636
637 pcie3: pcie@3600000 {
638 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
639 "snps,dw-pcie";
640 reg-names = "regs", "config";
641 interrupts = <0 118 0x4>; /* Level high type */
642 interrupt-names = "intr";
643 #address-cells = <3>;
644 #size-cells = <2>;
645 device_type = "pci";
646 dma-coherent;
647 num-lanes = <8>;
648 bus-range = <0x0 0xff>;
649 msi-parent = <&its>;
650 #interrupt-cells = <1>;
651 interrupt-map-mask = <0 0 0 7>;
652 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
653 <0000 0 0 2 &gic 0 0 0 120 4>,
654 <0000 0 0 3 &gic 0 0 0 121 4>,
655 <0000 0 0 4 &gic 0 0 0 122 4>;
656 };
657
658 pcie4: pcie@3700000 {
659 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
660 "snps,dw-pcie";
661 reg-names = "regs", "config";
662 interrupts = <0 123 0x4>; /* Level high type */
663 interrupt-names = "intr";
664 #address-cells = <3>;
665 #size-cells = <2>;
666 device_type = "pci";
667 dma-coherent;
668 num-lanes = <4>;
669 bus-range = <0x0 0xff>;
670 msi-parent = <&its>;
671 #interrupt-cells = <1>;
672 interrupt-map-mask = <0 0 0 7>;
673 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
674 <0000 0 0 2 &gic 0 0 0 125 4>,
675 <0000 0 0 3 &gic 0 0 0 126 4>,
676 <0000 0 0 4 &gic 0 0 0 127 4>;
677 };
678
679 sata0: sata@3200000 {
680 status = "disabled";
681 compatible = "fsl,ls2080a-ahci";
682 reg = <0x0 0x3200000 0x0 0x10000>;
683 interrupts = <0 133 0x4>; /* Level high type */
684 clocks = <&clockgen 4 3>;
685 dma-coherent;
686 };
687
688 sata1: sata@3210000 {
689 status = "disabled";
690 compatible = "fsl,ls2080a-ahci";
691 reg = <0x0 0x3210000 0x0 0x10000>;
692 interrupts = <0 136 0x4>; /* Level high type */
693 clocks = <&clockgen 4 3>;
694 dma-coherent;
695 };
696
697 usb0: usb3@3100000 {
698 status = "disabled";
699 compatible = "snps,dwc3";
700 reg = <0x0 0x3100000 0x0 0x10000>;
701 interrupts = <0 80 0x4>; /* Level high type */
702 dr_mode = "host";
703 snps,quirk-frame-length-adjustment = <0x20>;
704 snps,dis_rxdet_inp3_quirk;
705 };
706
707 usb1: usb3@3110000 {
708 status = "disabled";
709 compatible = "snps,dwc3";
710 reg = <0x0 0x3110000 0x0 0x10000>;
711 interrupts = <0 81 0x4>; /* Level high type */
712 dr_mode = "host";
713 snps,quirk-frame-length-adjustment = <0x20>;
714 snps,dis_rxdet_inp3_quirk;
715 };
716
717 ccn@4000000 {
718 compatible = "arm,ccn-504";
719 reg = <0x0 0x04000000 0x0 0x01000000>;
720 interrupts = <0 12 4>;
721 };
722 };
723
724 ddr1: memory-controller@1080000 {
725 compatible = "fsl,qoriq-memory-controller";
726 reg = <0x0 0x1080000 0x0 0x1000>;
727 interrupts = <0 17 0x4>;
728 little-endian;
729 };
730
731 ddr2: memory-controller@1090000 {
732 compatible = "fsl,qoriq-memory-controller";
733 reg = <0x0 0x1090000 0x0 0x1000>;
734 interrupts = <0 18 0x4>;
735 little-endian;
736 };
737};