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authorOlof Johansson2017-04-19 07:39:41 -0500
committerOlof Johansson2017-04-19 07:39:41 -0500
commit2149ed8d6fcd43cf99a10c3304f84286d64f6eed (patch)
tree1a6bdee91e600362c53e39bd97aa200be989be49
parent6929f0f6a49f56565fd0d2f87dafa5c7bcd970ba (diff)
parentd7bb5b966174fee6e4b0085124b75787a5d81b8a (diff)
downloadkernel-2149ed8d6fcd43cf99a10c3304f84286d64f6eed.tar.gz
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Merge tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64
Allwinner H5 DT changes for 4.12 H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to be usable on the arm64 H5 DTSI, that shares almost everything with the H3 but the CPU cores. We then have patches to support the H5 boards on top. * tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board arm64: allwinner: h5: add support for the Orange Pi PC 2 board arm64: allwinner: h5: add Allwinner H5 .dtsi ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5 arm: sun8i: h3: split Allwinner H3 .dtsi arm: sun8i: h3: correct the GIC compatible in H3 to gic-400 arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi602
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5.dtsi601
-rw-r--r--arch/arm64/boot/dts/allwinner/Makefile1
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts188
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi124
l---------arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi1
6 files changed, 955 insertions, 562 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 27780b97c863..b36f9f423c39 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -40,16 +40,9 @@
40 * OTHER DEALINGS IN THE SOFTWARE. 40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 41 */
42 42
43#include "skeleton.dtsi" 43#include "sunxi-h3-h5.dtsi"
44
45#include <dt-bindings/clock/sun8i-h3-ccu.h>
46#include <dt-bindings/interrupt-controller/arm-gic.h>
47#include <dt-bindings/pinctrl/sun4i-a10.h>
48#include <dt-bindings/reset/sun8i-h3-ccu.h>
49 44
50/ { 45/ {
51 interrupt-parent = <&gic>;
52
53 cpus { 46 cpus {
54 #address-cells = <1>; 47 #address-cells = <1>;
55 #size-cells = <0>; 48 #size-cells = <0>;
@@ -86,563 +79,48 @@
86 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 80 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
88 }; 81 };
82};
89 83
90 clocks { 84&ccu {
91 #address-cells = <1>; 85 compatible = "allwinner,sun8i-h3-ccu";
92 #size-cells = <1>; 86};
93 ranges;
94
95 osc24M: osc24M_clk {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <24000000>;
99 clock-output-names = "osc24M";
100 };
101
102 osc32k: osc32k_clk {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 clock-frequency = <32768>;
106 clock-output-names = "osc32k";
107 };
108
109 apb0: apb0_clk {
110 compatible = "fixed-factor-clock";
111 #clock-cells = <0>;
112 clock-div = <1>;
113 clock-mult = <1>;
114 clocks = <&osc24M>;
115 clock-output-names = "apb0";
116 };
117
118 apb0_gates: clk@01f01428 {
119 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
120 "allwinner,sun4i-a10-gates-clk";
121 reg = <0x01f01428 0x4>;
122 #clock-cells = <1>;
123 clocks = <&apb0>;
124 clock-indices = <0>, <1>;
125 clock-output-names = "apb0_pio", "apb0_ir";
126 };
127
128 ir_clk: ir_clk@01f01454 {
129 compatible = "allwinner,sun4i-a10-mod0-clk";
130 reg = <0x01f01454 0x4>;
131 #clock-cells = <0>;
132 clocks = <&osc32k>, <&osc24M>;
133 clock-output-names = "ir";
134 };
135 };
136
137 soc {
138 compatible = "simple-bus";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 ranges;
142
143 dma: dma-controller@01c02000 {
144 compatible = "allwinner,sun8i-h3-dma";
145 reg = <0x01c02000 0x1000>;
146 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&ccu CLK_BUS_DMA>;
148 resets = <&ccu RST_BUS_DMA>;
149 #dma-cells = <1>;
150 };
151
152 mmc0: mmc@01c0f000 {
153 compatible = "allwinner,sun7i-a20-mmc";
154 reg = <0x01c0f000 0x1000>;
155 clocks = <&ccu CLK_BUS_MMC0>,
156 <&ccu CLK_MMC0>,
157 <&ccu CLK_MMC0_OUTPUT>,
158 <&ccu CLK_MMC0_SAMPLE>;
159 clock-names = "ahb",
160 "mmc",
161 "output",
162 "sample";
163 resets = <&ccu RST_BUS_MMC0>;
164 reset-names = "ahb";
165 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
166 status = "disabled";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 };
170
171 mmc1: mmc@01c10000 {
172 compatible = "allwinner,sun7i-a20-mmc";
173 reg = <0x01c10000 0x1000>;
174 clocks = <&ccu CLK_BUS_MMC1>,
175 <&ccu CLK_MMC1>,
176 <&ccu CLK_MMC1_OUTPUT>,
177 <&ccu CLK_MMC1_SAMPLE>;
178 clock-names = "ahb",
179 "mmc",
180 "output",
181 "sample";
182 resets = <&ccu RST_BUS_MMC1>;
183 reset-names = "ahb";
184 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
185 status = "disabled";
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 mmc2: mmc@01c11000 {
191 compatible = "allwinner,sun7i-a20-mmc";
192 reg = <0x01c11000 0x1000>;
193 clocks = <&ccu CLK_BUS_MMC2>,
194 <&ccu CLK_MMC2>,
195 <&ccu CLK_MMC2_OUTPUT>,
196 <&ccu CLK_MMC2_SAMPLE>;
197 clock-names = "ahb",
198 "mmc",
199 "output",
200 "sample";
201 resets = <&ccu RST_BUS_MMC2>;
202 reset-names = "ahb";
203 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
204 status = "disabled";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 };
208
209 usbphy: phy@01c19400 {
210 compatible = "allwinner,sun8i-h3-usb-phy";
211 reg = <0x01c19400 0x2c>,
212 <0x01c1a800 0x4>,
213 <0x01c1b800 0x4>,
214 <0x01c1c800 0x4>,
215 <0x01c1d800 0x4>;
216 reg-names = "phy_ctrl",
217 "pmu0",
218 "pmu1",
219 "pmu2",
220 "pmu3";
221 clocks = <&ccu CLK_USB_PHY0>,
222 <&ccu CLK_USB_PHY1>,
223 <&ccu CLK_USB_PHY2>,
224 <&ccu CLK_USB_PHY3>;
225 clock-names = "usb0_phy",
226 "usb1_phy",
227 "usb2_phy",
228 "usb3_phy";
229 resets = <&ccu RST_USB_PHY0>,
230 <&ccu RST_USB_PHY1>,
231 <&ccu RST_USB_PHY2>,
232 <&ccu RST_USB_PHY3>;
233 reset-names = "usb0_reset",
234 "usb1_reset",
235 "usb2_reset",
236 "usb3_reset";
237 status = "disabled";
238 #phy-cells = <1>;
239 };
240
241 ehci1: usb@01c1b000 {
242 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
243 reg = <0x01c1b000 0x100>;
244 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
246 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
247 phys = <&usbphy 1>;
248 phy-names = "usb";
249 status = "disabled";
250 };
251
252 ohci1: usb@01c1b400 {
253 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
254 reg = <0x01c1b400 0x100>;
255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
257 <&ccu CLK_USB_OHCI1>;
258 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
259 phys = <&usbphy 1>;
260 phy-names = "usb";
261 status = "disabled";
262 };
263
264 ehci2: usb@01c1c000 {
265 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
266 reg = <0x01c1c000 0x100>;
267 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
269 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
270 phys = <&usbphy 2>;
271 phy-names = "usb";
272 status = "disabled";
273 };
274
275 ohci2: usb@01c1c400 {
276 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
277 reg = <0x01c1c400 0x100>;
278 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
280 <&ccu CLK_USB_OHCI2>;
281 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
282 phys = <&usbphy 2>;
283 phy-names = "usb";
284 status = "disabled";
285 };
286
287 ehci3: usb@01c1d000 {
288 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
289 reg = <0x01c1d000 0x100>;
290 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
292 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
293 phys = <&usbphy 3>;
294 phy-names = "usb";
295 status = "disabled";
296 };
297
298 ohci3: usb@01c1d400 {
299 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
300 reg = <0x01c1d400 0x100>;
301 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
303 <&ccu CLK_USB_OHCI3>;
304 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
305 phys = <&usbphy 3>;
306 phy-names = "usb";
307 status = "disabled";
308 };
309
310 ccu: clock@01c20000 {
311 compatible = "allwinner,sun8i-h3-ccu";
312 reg = <0x01c20000 0x400>;
313 clocks = <&osc24M>, <&osc32k>;
314 clock-names = "hosc", "losc";
315 #clock-cells = <1>;
316 #reset-cells = <1>;
317 };
318
319 pio: pinctrl@01c20800 {
320 compatible = "allwinner,sun8i-h3-pinctrl";
321 reg = <0x01c20800 0x400>;
322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
325 clock-names = "apb", "hosc", "losc";
326 gpio-controller;
327 #gpio-cells = <3>;
328 interrupt-controller;
329 #interrupt-cells = <3>;
330
331 i2c0_pins: i2c0 {
332 pins = "PA11", "PA12";
333 function = "i2c0";
334 };
335
336 i2c1_pins: i2c1 {
337 pins = "PA18", "PA19";
338 function = "i2c1";
339 };
340
341 i2c2_pins: i2c2 {
342 pins = "PE12", "PE13";
343 function = "i2c2";
344 };
345
346 mmc0_pins_a: mmc0@0 {
347 pins = "PF0", "PF1", "PF2", "PF3",
348 "PF4", "PF5";
349 function = "mmc0";
350 drive-strength = <30>;
351 bias-pull-up;
352 };
353
354 mmc0_cd_pin: mmc0_cd_pin@0 {
355 pins = "PF6";
356 function = "gpio_in";
357 bias-pull-up;
358 };
359
360 mmc1_pins_a: mmc1@0 {
361 pins = "PG0", "PG1", "PG2", "PG3",
362 "PG4", "PG5";
363 function = "mmc1";
364 drive-strength = <30>;
365 bias-pull-up;
366 };
367
368 mmc2_8bit_pins: mmc2_8bit {
369 pins = "PC5", "PC6", "PC8",
370 "PC9", "PC10", "PC11",
371 "PC12", "PC13", "PC14",
372 "PC15", "PC16";
373 function = "mmc2";
374 drive-strength = <30>;
375 bias-pull-up;
376 };
377
378 spdif_tx_pins_a: spdif@0 {
379 pins = "PA17";
380 function = "spdif";
381 };
382
383 spi0_pins: spi0 {
384 pins = "PC0", "PC1", "PC2", "PC3";
385 function = "spi0";
386 };
387
388 spi1_pins: spi1 {
389 pins = "PA15", "PA16", "PA14", "PA13";
390 function = "spi1";
391 };
392
393 uart0_pins_a: uart0@0 {
394 pins = "PA4", "PA5";
395 function = "uart0";
396 };
397
398 uart1_pins: uart1 {
399 pins = "PG6", "PG7";
400 function = "uart1";
401 };
402
403 uart1_rts_cts_pins: uart1_rts_cts {
404 pins = "PG8", "PG9";
405 function = "uart1";
406 };
407
408 uart2_pins: uart2 {
409 pins = "PA0", "PA1";
410 function = "uart2";
411 };
412
413 uart3_pins: uart3 {
414 pins = "PA13", "PA14";
415 function = "uart3";
416 };
417 };
418
419 timer@01c20c00 {
420 compatible = "allwinner,sun4i-a10-timer";
421 reg = <0x01c20c00 0xa0>;
422 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&osc24M>;
425 };
426
427 spi0: spi@01c68000 {
428 compatible = "allwinner,sun8i-h3-spi";
429 reg = <0x01c68000 0x1000>;
430 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
432 clock-names = "ahb", "mod";
433 dmas = <&dma 23>, <&dma 23>;
434 dma-names = "rx", "tx";
435 pinctrl-names = "default";
436 pinctrl-0 = <&spi0_pins>;
437 resets = <&ccu RST_BUS_SPI0>;
438 status = "disabled";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 };
442
443 spi1: spi@01c69000 {
444 compatible = "allwinner,sun8i-h3-spi";
445 reg = <0x01c69000 0x1000>;
446 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
448 clock-names = "ahb", "mod";
449 dmas = <&dma 24>, <&dma 24>;
450 dma-names = "rx", "tx";
451 pinctrl-names = "default";
452 pinctrl-0 = <&spi1_pins>;
453 resets = <&ccu RST_BUS_SPI1>;
454 status = "disabled";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 };
458
459 wdt0: watchdog@01c20ca0 {
460 compatible = "allwinner,sun6i-a31-wdt";
461 reg = <0x01c20ca0 0x20>;
462 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
463 };
464
465 spdif: spdif@01c21000 {
466 #sound-dai-cells = <0>;
467 compatible = "allwinner,sun8i-h3-spdif";
468 reg = <0x01c21000 0x400>;
469 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
471 resets = <&ccu RST_BUS_SPDIF>;
472 clock-names = "apb", "spdif";
473 dmas = <&dma 2>;
474 dma-names = "tx";
475 status = "disabled";
476 };
477
478 pwm: pwm@01c21400 {
479 compatible = "allwinner,sun8i-h3-pwm";
480 reg = <0x01c21400 0x8>;
481 clocks = <&osc24M>;
482 #pwm-cells = <3>;
483 status = "disabled";
484 };
485
486 codec: codec@01c22c00 {
487 #sound-dai-cells = <0>;
488 compatible = "allwinner,sun8i-h3-codec";
489 reg = <0x01c22c00 0x400>;
490 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
492 clock-names = "apb", "codec";
493 resets = <&ccu RST_BUS_CODEC>;
494 dmas = <&dma 15>, <&dma 15>;
495 dma-names = "rx", "tx";
496 allwinner,codec-analog-controls = <&codec_analog>;
497 status = "disabled";
498 };
499
500 uart0: serial@01c28000 {
501 compatible = "snps,dw-apb-uart";
502 reg = <0x01c28000 0x400>;
503 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
504 reg-shift = <2>;
505 reg-io-width = <4>;
506 clocks = <&ccu CLK_BUS_UART0>;
507 resets = <&ccu RST_BUS_UART0>;
508 dmas = <&dma 6>, <&dma 6>;
509 dma-names = "rx", "tx";
510 status = "disabled";
511 };
512
513 uart1: serial@01c28400 {
514 compatible = "snps,dw-apb-uart";
515 reg = <0x01c28400 0x400>;
516 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
517 reg-shift = <2>;
518 reg-io-width = <4>;
519 clocks = <&ccu CLK_BUS_UART1>;
520 resets = <&ccu RST_BUS_UART1>;
521 dmas = <&dma 7>, <&dma 7>;
522 dma-names = "rx", "tx";
523 status = "disabled";
524 };
525
526 uart2: serial@01c28800 {
527 compatible = "snps,dw-apb-uart";
528 reg = <0x01c28800 0x400>;
529 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
530 reg-shift = <2>;
531 reg-io-width = <4>;
532 clocks = <&ccu CLK_BUS_UART2>;
533 resets = <&ccu RST_BUS_UART2>;
534 dmas = <&dma 8>, <&dma 8>;
535 dma-names = "rx", "tx";
536 status = "disabled";
537 };
538
539 uart3: serial@01c28c00 {
540 compatible = "snps,dw-apb-uart";
541 reg = <0x01c28c00 0x400>;
542 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
543 reg-shift = <2>;
544 reg-io-width = <4>;
545 clocks = <&ccu CLK_BUS_UART3>;
546 resets = <&ccu RST_BUS_UART3>;
547 dmas = <&dma 9>, <&dma 9>;
548 dma-names = "rx", "tx";
549 status = "disabled";
550 };
551
552 i2c0: i2c@01c2ac00 {
553 compatible = "allwinner,sun6i-a31-i2c";
554 reg = <0x01c2ac00 0x400>;
555 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&ccu CLK_BUS_I2C0>;
557 resets = <&ccu RST_BUS_I2C0>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&i2c0_pins>;
560 status = "disabled";
561 #address-cells = <1>;
562 #size-cells = <0>;
563 };
564
565 i2c1: i2c@01c2b000 {
566 compatible = "allwinner,sun6i-a31-i2c";
567 reg = <0x01c2b000 0x400>;
568 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&ccu CLK_BUS_I2C1>;
570 resets = <&ccu RST_BUS_I2C1>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c1_pins>;
573 status = "disabled";
574 #address-cells = <1>;
575 #size-cells = <0>;
576 };
577
578 i2c2: i2c@01c2b400 {
579 compatible = "allwinner,sun6i-a31-i2c";
580 reg = <0x01c2b000 0x400>;
581 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&ccu CLK_BUS_I2C2>;
583 resets = <&ccu RST_BUS_I2C2>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c2_pins>;
586 status = "disabled";
587 #address-cells = <1>;
588 #size-cells = <0>;
589 };
590
591 gic: interrupt-controller@01c81000 {
592 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
593 reg = <0x01c81000 0x1000>,
594 <0x01c82000 0x2000>,
595 <0x01c84000 0x2000>,
596 <0x01c86000 0x2000>;
597 interrupt-controller;
598 #interrupt-cells = <3>;
599 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
600 };
601
602 rtc: rtc@01f00000 {
603 compatible = "allwinner,sun6i-a31-rtc";
604 reg = <0x01f00000 0x54>;
605 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
607 };
608
609 apb0_reset: reset@01f014b0 {
610 reg = <0x01f014b0 0x4>;
611 compatible = "allwinner,sun6i-a31-clock-reset";
612 #reset-cells = <1>;
613 };
614 87
615 codec_analog: codec-analog@01f015c0 { 88&mmc0 {
616 compatible = "allwinner,sun8i-h3-codec-analog"; 89 compatible = "allwinner,sun7i-a20-mmc";
617 reg = <0x01f015c0 0x4>; 90 clocks = <&ccu CLK_BUS_MMC0>,
618 }; 91 <&ccu CLK_MMC0>,
92 <&ccu CLK_MMC0_OUTPUT>,
93 <&ccu CLK_MMC0_SAMPLE>;
94 clock-names = "ahb",
95 "mmc",
96 "output",
97 "sample";
98};
619 99
620 ir: ir@01f02000 { 100&mmc1 {
621 compatible = "allwinner,sun5i-a13-ir"; 101 compatible = "allwinner,sun7i-a20-mmc";
622 clocks = <&apb0_gates 1>, <&ir_clk>; 102 clocks = <&ccu CLK_BUS_MMC1>,
623 clock-names = "apb", "ir"; 103 <&ccu CLK_MMC1>,
624 resets = <&apb0_reset 1>; 104 <&ccu CLK_MMC1_OUTPUT>,
625 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 105 <&ccu CLK_MMC1_SAMPLE>;
626 reg = <0x01f02000 0x40>; 106 clock-names = "ahb",
627 status = "disabled"; 107 "mmc",
628 }; 108 "output",
109 "sample";
110};
629 111
630 r_pio: pinctrl@01f02c00 { 112&mmc2 {
631 compatible = "allwinner,sun8i-h3-r-pinctrl"; 113 compatible = "allwinner,sun7i-a20-mmc";
632 reg = <0x01f02c00 0x400>; 114 clocks = <&ccu CLK_BUS_MMC2>,
633 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 115 <&ccu CLK_MMC2>,
634 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; 116 <&ccu CLK_MMC2_OUTPUT>,
635 clock-names = "apb", "hosc", "losc"; 117 <&ccu CLK_MMC2_SAMPLE>;
636 resets = <&apb0_reset 0>; 118 clock-names = "ahb",
637 gpio-controller; 119 "mmc",
638 #gpio-cells = <3>; 120 "output",
639 interrupt-controller; 121 "sample";
640 #interrupt-cells = <3>; 122};
641 123
642 ir_pins_a: ir@0 { 124&pio {
643 pins = "PL11"; 125 compatible = "allwinner,sun8i-h3-pinctrl";
644 function = "s_cir_rx";
645 };
646 };
647 };
648}; 126};
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
new file mode 100644
index 000000000000..1aeeacb3a884
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -0,0 +1,601 @@
1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/sun8i-h3-ccu.h>
44#include <dt-bindings/interrupt-controller/arm-gic.h>
45#include <dt-bindings/reset/sun8i-h3-ccu.h>
46
47/ {
48 interrupt-parent = <&gic>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51
52 clocks {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 osc24M: osc24M_clk {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 clock-output-names = "osc24M";
62 };
63
64 osc32k: osc32k_clk {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32768>;
68 clock-output-names = "osc32k";
69 };
70
71 iosc: internal-osc-clk {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <16000000>;
75 clock-accuracy = <300000000>;
76 clock-output-names = "iosc";
77 };
78 };
79
80 soc {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 dma: dma-controller@01c02000 {
87 compatible = "allwinner,sun8i-h3-dma";
88 reg = <0x01c02000 0x1000>;
89 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&ccu CLK_BUS_DMA>;
91 resets = <&ccu RST_BUS_DMA>;
92 #dma-cells = <1>;
93 };
94
95 mmc0: mmc@01c0f000 {
96 /* compatible and clocks are in per SoC .dtsi file */
97 reg = <0x01c0f000 0x1000>;
98 resets = <&ccu RST_BUS_MMC0>;
99 reset-names = "ahb";
100 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
101 status = "disabled";
102 #address-cells = <1>;
103 #size-cells = <0>;
104 };
105
106 mmc1: mmc@01c10000 {
107 /* compatible and clocks are in per SoC .dtsi file */
108 reg = <0x01c10000 0x1000>;
109 resets = <&ccu RST_BUS_MMC1>;
110 reset-names = "ahb";
111 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
112 status = "disabled";
113 #address-cells = <1>;
114 #size-cells = <0>;
115 };
116
117 mmc2: mmc@01c11000 {
118 /* compatible and clocks are in per SoC .dtsi file */
119 reg = <0x01c11000 0x1000>;
120 resets = <&ccu RST_BUS_MMC2>;
121 reset-names = "ahb";
122 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
123 status = "disabled";
124 #address-cells = <1>;
125 #size-cells = <0>;
126 };
127
128 usb_otg: usb@01c19000 {
129 compatible = "allwinner,sun8i-h3-musb";
130 reg = <0x01c19000 0x400>;
131 clocks = <&ccu CLK_BUS_OTG>;
132 resets = <&ccu RST_BUS_OTG>;
133 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "mc";
135 phys = <&usbphy 0>;
136 phy-names = "usb";
137 extcon = <&usbphy 0>;
138 status = "disabled";
139 };
140
141 usbphy: phy@01c19400 {
142 compatible = "allwinner,sun8i-h3-usb-phy";
143 reg = <0x01c19400 0x2c>,
144 <0x01c1a800 0x4>,
145 <0x01c1b800 0x4>,
146 <0x01c1c800 0x4>,
147 <0x01c1d800 0x4>;
148 reg-names = "phy_ctrl",
149 "pmu0",
150 "pmu1",
151 "pmu2",
152 "pmu3";
153 clocks = <&ccu CLK_USB_PHY0>,
154 <&ccu CLK_USB_PHY1>,
155 <&ccu CLK_USB_PHY2>,
156 <&ccu CLK_USB_PHY3>;
157 clock-names = "usb0_phy",
158 "usb1_phy",
159 "usb2_phy",
160 "usb3_phy";
161 resets = <&ccu RST_USB_PHY0>,
162 <&ccu RST_USB_PHY1>,
163 <&ccu RST_USB_PHY2>,
164 <&ccu RST_USB_PHY3>;
165 reset-names = "usb0_reset",
166 "usb1_reset",
167 "usb2_reset",
168 "usb3_reset";
169 status = "disabled";
170 #phy-cells = <1>;
171 };
172
173 ehci0: usb@01c1a000 {
174 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
175 reg = <0x01c1a000 0x100>;
176 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
178 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
179 status = "disabled";
180 };
181
182 ohci0: usb@01c1a400 {
183 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
184 reg = <0x01c1a400 0x100>;
185 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
187 <&ccu CLK_USB_OHCI0>;
188 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
189 status = "disabled";
190 };
191
192 ehci1: usb@01c1b000 {
193 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
194 reg = <0x01c1b000 0x100>;
195 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
197 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
198 phys = <&usbphy 1>;
199 phy-names = "usb";
200 status = "disabled";
201 };
202
203 ohci1: usb@01c1b400 {
204 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
205 reg = <0x01c1b400 0x100>;
206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
208 <&ccu CLK_USB_OHCI1>;
209 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
210 phys = <&usbphy 1>;
211 phy-names = "usb";
212 status = "disabled";
213 };
214
215 ehci2: usb@01c1c000 {
216 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
217 reg = <0x01c1c000 0x100>;
218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
220 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
221 phys = <&usbphy 2>;
222 phy-names = "usb";
223 status = "disabled";
224 };
225
226 ohci2: usb@01c1c400 {
227 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
228 reg = <0x01c1c400 0x100>;
229 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
231 <&ccu CLK_USB_OHCI2>;
232 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
233 phys = <&usbphy 2>;
234 phy-names = "usb";
235 status = "disabled";
236 };
237
238 ehci3: usb@01c1d000 {
239 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
240 reg = <0x01c1d000 0x100>;
241 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
243 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
244 phys = <&usbphy 3>;
245 phy-names = "usb";
246 status = "disabled";
247 };
248
249 ohci3: usb@01c1d400 {
250 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
251 reg = <0x01c1d400 0x100>;
252 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
254 <&ccu CLK_USB_OHCI3>;
255 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
256 phys = <&usbphy 3>;
257 phy-names = "usb";
258 status = "disabled";
259 };
260
261 ccu: clock@01c20000 {
262 /* compatible is in per SoC .dtsi file */
263 reg = <0x01c20000 0x400>;
264 clocks = <&osc24M>, <&osc32k>;
265 clock-names = "hosc", "losc";
266 #clock-cells = <1>;
267 #reset-cells = <1>;
268 };
269
270 pio: pinctrl@01c20800 {
271 /* compatible is in per SoC .dtsi file */
272 reg = <0x01c20800 0x400>;
273 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
276 clock-names = "apb", "hosc", "losc";
277 gpio-controller;
278 #gpio-cells = <3>;
279 interrupt-controller;
280 #interrupt-cells = <3>;
281
282 i2c0_pins: i2c0 {
283 pins = "PA11", "PA12";
284 function = "i2c0";
285 };
286
287 i2c1_pins: i2c1 {
288 pins = "PA18", "PA19";
289 function = "i2c1";
290 };
291
292 i2c2_pins: i2c2 {
293 pins = "PE12", "PE13";
294 function = "i2c2";
295 };
296
297 mmc0_pins_a: mmc0@0 {
298 pins = "PF0", "PF1", "PF2", "PF3",
299 "PF4", "PF5";
300 function = "mmc0";
301 drive-strength = <30>;
302 bias-pull-up;
303 };
304
305 mmc0_cd_pin: mmc0_cd_pin@0 {
306 pins = "PF6";
307 function = "gpio_in";
308 bias-pull-up;
309 };
310
311 mmc1_pins_a: mmc1@0 {
312 pins = "PG0", "PG1", "PG2", "PG3",
313 "PG4", "PG5";
314 function = "mmc1";
315 drive-strength = <30>;
316 bias-pull-up;
317 };
318
319 mmc2_8bit_pins: mmc2_8bit {
320 pins = "PC5", "PC6", "PC8",
321 "PC9", "PC10", "PC11",
322 "PC12", "PC13", "PC14",
323 "PC15", "PC16";
324 function = "mmc2";
325 drive-strength = <30>;
326 bias-pull-up;
327 };
328
329 spdif_tx_pins_a: spdif@0 {
330 pins = "PA17";
331 function = "spdif";
332 };
333
334 spi0_pins: spi0 {
335 pins = "PC0", "PC1", "PC2", "PC3";
336 function = "spi0";
337 };
338
339 spi1_pins: spi1 {
340 pins = "PA15", "PA16", "PA14", "PA13";
341 function = "spi1";
342 };
343
344 uart0_pins_a: uart0@0 {
345 pins = "PA4", "PA5";
346 function = "uart0";
347 };
348
349 uart1_pins: uart1 {
350 pins = "PG6", "PG7";
351 function = "uart1";
352 };
353
354 uart1_rts_cts_pins: uart1_rts_cts {
355 pins = "PG8", "PG9";
356 function = "uart1";
357 };
358
359 uart2_pins: uart2 {
360 pins = "PA0", "PA1";
361 function = "uart2";
362 };
363
364 uart3_pins: uart3 {
365 pins = "PA13", "PA14";
366 function = "uart3";
367 };
368 };
369
370 timer@01c20c00 {
371 compatible = "allwinner,sun4i-a10-timer";
372 reg = <0x01c20c00 0xa0>;
373 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&osc24M>;
376 };
377
378 spi0: spi@01c68000 {
379 compatible = "allwinner,sun8i-h3-spi";
380 reg = <0x01c68000 0x1000>;
381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
383 clock-names = "ahb", "mod";
384 dmas = <&dma 23>, <&dma 23>;
385 dma-names = "rx", "tx";
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi0_pins>;
388 resets = <&ccu RST_BUS_SPI0>;
389 status = "disabled";
390 #address-cells = <1>;
391 #size-cells = <0>;
392 };
393
394 spi1: spi@01c69000 {
395 compatible = "allwinner,sun8i-h3-spi";
396 reg = <0x01c69000 0x1000>;
397 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
399 clock-names = "ahb", "mod";
400 dmas = <&dma 24>, <&dma 24>;
401 dma-names = "rx", "tx";
402 pinctrl-names = "default";
403 pinctrl-0 = <&spi1_pins>;
404 resets = <&ccu RST_BUS_SPI1>;
405 status = "disabled";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 };
409
410 wdt0: watchdog@01c20ca0 {
411 compatible = "allwinner,sun6i-a31-wdt";
412 reg = <0x01c20ca0 0x20>;
413 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
414 };
415
416 spdif: spdif@01c21000 {
417 #sound-dai-cells = <0>;
418 compatible = "allwinner,sun8i-h3-spdif";
419 reg = <0x01c21000 0x400>;
420 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
422 resets = <&ccu RST_BUS_SPDIF>;
423 clock-names = "apb", "spdif";
424 dmas = <&dma 2>;
425 dma-names = "tx";
426 status = "disabled";
427 };
428
429 pwm: pwm@01c21400 {
430 compatible = "allwinner,sun8i-h3-pwm";
431 reg = <0x01c21400 0x8>;
432 clocks = <&osc24M>;
433 #pwm-cells = <3>;
434 status = "disabled";
435 };
436
437 codec: codec@01c22c00 {
438 #sound-dai-cells = <0>;
439 compatible = "allwinner,sun8i-h3-codec";
440 reg = <0x01c22c00 0x400>;
441 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
443 clock-names = "apb", "codec";
444 resets = <&ccu RST_BUS_CODEC>;
445 dmas = <&dma 15>, <&dma 15>;
446 dma-names = "rx", "tx";
447 allwinner,codec-analog-controls = <&codec_analog>;
448 status = "disabled";
449 };
450
451 uart0: serial@01c28000 {
452 compatible = "snps,dw-apb-uart";
453 reg = <0x01c28000 0x400>;
454 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
455 reg-shift = <2>;
456 reg-io-width = <4>;
457 clocks = <&ccu CLK_BUS_UART0>;
458 resets = <&ccu RST_BUS_UART0>;
459 dmas = <&dma 6>, <&dma 6>;
460 dma-names = "rx", "tx";
461 status = "disabled";
462 };
463
464 uart1: serial@01c28400 {
465 compatible = "snps,dw-apb-uart";
466 reg = <0x01c28400 0x400>;
467 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
468 reg-shift = <2>;
469 reg-io-width = <4>;
470 clocks = <&ccu CLK_BUS_UART1>;
471 resets = <&ccu RST_BUS_UART1>;
472 dmas = <&dma 7>, <&dma 7>;
473 dma-names = "rx", "tx";
474 status = "disabled";
475 };
476
477 uart2: serial@01c28800 {
478 compatible = "snps,dw-apb-uart";
479 reg = <0x01c28800 0x400>;
480 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
481 reg-shift = <2>;
482 reg-io-width = <4>;
483 clocks = <&ccu CLK_BUS_UART2>;
484 resets = <&ccu RST_BUS_UART2>;
485 dmas = <&dma 8>, <&dma 8>;
486 dma-names = "rx", "tx";
487 status = "disabled";
488 };
489
490 uart3: serial@01c28c00 {
491 compatible = "snps,dw-apb-uart";
492 reg = <0x01c28c00 0x400>;
493 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
494 reg-shift = <2>;
495 reg-io-width = <4>;
496 clocks = <&ccu CLK_BUS_UART3>;
497 resets = <&ccu RST_BUS_UART3>;
498 dmas = <&dma 9>, <&dma 9>;
499 dma-names = "rx", "tx";
500 status = "disabled";
501 };
502
503 i2c0: i2c@01c2ac00 {
504 compatible = "allwinner,sun6i-a31-i2c";
505 reg = <0x01c2ac00 0x400>;
506 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&ccu CLK_BUS_I2C0>;
508 resets = <&ccu RST_BUS_I2C0>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&i2c0_pins>;
511 status = "disabled";
512 #address-cells = <1>;
513 #size-cells = <0>;
514 };
515
516 i2c1: i2c@01c2b000 {
517 compatible = "allwinner,sun6i-a31-i2c";
518 reg = <0x01c2b000 0x400>;
519 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&ccu CLK_BUS_I2C1>;
521 resets = <&ccu RST_BUS_I2C1>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&i2c1_pins>;
524 status = "disabled";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 };
528
529 i2c2: i2c@01c2b400 {
530 compatible = "allwinner,sun6i-a31-i2c";
531 reg = <0x01c2b000 0x400>;
532 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&ccu CLK_BUS_I2C2>;
534 resets = <&ccu RST_BUS_I2C2>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2c2_pins>;
537 status = "disabled";
538 #address-cells = <1>;
539 #size-cells = <0>;
540 };
541
542 gic: interrupt-controller@01c81000 {
543 compatible = "arm,gic-400";
544 reg = <0x01c81000 0x1000>,
545 <0x01c82000 0x2000>,
546 <0x01c84000 0x2000>,
547 <0x01c86000 0x2000>;
548 interrupt-controller;
549 #interrupt-cells = <3>;
550 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
551 };
552
553 rtc: rtc@01f00000 {
554 compatible = "allwinner,sun6i-a31-rtc";
555 reg = <0x01f00000 0x54>;
556 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
558 };
559
560 r_ccu: clock@1f01400 {
561 compatible = "allwinner,sun50i-a64-r-ccu";
562 reg = <0x01f01400 0x100>;
563 clocks = <&osc24M>, <&osc32k>, <&iosc>;
564 clock-names = "hosc", "losc", "iosc";
565 #clock-cells = <1>;
566 #reset-cells = <1>;
567 };
568
569 codec_analog: codec-analog@01f015c0 {
570 compatible = "allwinner,sun8i-h3-codec-analog";
571 reg = <0x01f015c0 0x4>;
572 };
573
574 ir: ir@01f02000 {
575 compatible = "allwinner,sun5i-a13-ir";
576 clocks = <&r_ccu 4>, <&r_ccu 11>;
577 clock-names = "apb", "ir";
578 resets = <&r_ccu 0>;
579 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
580 reg = <0x01f02000 0x40>;
581 status = "disabled";
582 };
583
584 r_pio: pinctrl@01f02c00 {
585 compatible = "allwinner,sun8i-h3-r-pinctrl";
586 reg = <0x01f02c00 0x400>;
587 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
589 clock-names = "apb", "hosc", "losc";
590 gpio-controller;
591 #gpio-cells = <3>;
592 interrupt-controller;
593 #interrupt-cells = <3>;
594
595 ir_pins_a: ir@0 {
596 pins = "PL11";
597 function = "s_cir_rx";
598 };
599 };
600 };
601};
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index bc6f342be59f..244e8b7565f9 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -1,5 +1,6 @@
1dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb 1dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
2dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb 2dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
3dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
3 4
4always := $(dtb-y) 5always := $(dtb-y)
5subdir-y := $(dts-dirs) 6subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
new file mode 100644
index 000000000000..dfecc17dcc92
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -0,0 +1,188 @@
1/*
2 * Copyright (C) 2016 ARM Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "sun50i-h5.dtsi"
45
46#include <dt-bindings/gpio/gpio.h>
47#include <dt-bindings/input/input.h>
48#include <dt-bindings/pinctrl/sun4i-a10.h>
49
50/ {
51 model = "Xunlong Orange Pi PC 2";
52 compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
53
54 reg_vcc3v3: vcc3v3 {
55 compatible = "regulator-fixed";
56 regulator-name = "vcc3v3";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 };
60
61 aliases {
62 serial0 = &uart0;
63 };
64
65 chosen {
66 stdout-path = "serial0:115200n8";
67 };
68
69 leds {
70 compatible = "gpio-leds";
71
72 pwr {
73 label = "orangepi:green:pwr";
74 gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
75 default-state = "on";
76 };
77
78 status {
79 label = "orangepi:red:status";
80 gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
81 };
82 };
83
84 r-gpio-keys {
85 compatible = "gpio-keys";
86
87 sw4 {
88 label = "sw4";
89 linux,code = <BTN_0>;
90 gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
91 };
92 };
93
94 reg_usb0_vbus: usb0-vbus {
95 compatible = "regulator-fixed";
96 regulator-name = "usb0-vbus";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 enable-active-high;
100 gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
101 status = "okay";
102 };
103};
104
105&codec {
106 allwinner,audio-routing =
107 "Line Out", "LINEOUT",
108 "MIC1", "Mic",
109 "Mic", "MBIAS";
110 status = "okay";
111};
112
113&ehci0 {
114 status = "okay";
115};
116
117&ehci1 {
118 status = "okay";
119};
120
121&ehci2 {
122 status = "okay";
123};
124
125&ehci3 {
126 status = "okay";
127};
128
129&ir {
130 pinctrl-names = "default";
131 pinctrl-0 = <&ir_pins_a>;
132 status = "okay";
133};
134
135&mmc0 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
138 vmmc-supply = <&reg_vcc3v3>;
139 bus-width = <4>;
140 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
141 status = "okay";
142};
143
144&ohci0 {
145 status = "okay";
146};
147
148&ohci1 {
149 status = "okay";
150};
151
152&ohci2 {
153 status = "okay";
154};
155
156&ohci3 {
157 status = "okay";
158};
159
160&uart0 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&uart0_pins_a>;
163 status = "okay";
164};
165
166&uart1 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&uart1_pins>;
169 status = "disabled";
170};
171
172&uart2 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&uart2_pins>;
175 status = "disabled";
176};
177
178&usb_otg {
179 dr_mode = "otg";
180 status = "okay";
181};
182
183&usbphy {
184 /* USB Type-A ports' VBUS is always on */
185 usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
186 usb0_vbus-supply = <&reg_usb0_vbus>;
187 status = "okay";
188};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
new file mode 100644
index 000000000000..4d314a253fd9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -0,0 +1,124 @@
1/*
2 * Copyright (C) 2016 ARM Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "sunxi-h3-h5.dtsi"
44
45/ {
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@0 {
51 compatible = "arm,cortex-a53", "arm,armv8";
52 device_type = "cpu";
53 reg = <0>;
54 enable-method = "psci";
55 };
56
57 cpu@1 {
58 compatible = "arm,cortex-a53", "arm,armv8";
59 device_type = "cpu";
60 reg = <1>;
61 enable-method = "psci";
62 };
63
64 cpu@2 {
65 compatible = "arm,cortex-a53", "arm,armv8";
66 device_type = "cpu";
67 reg = <2>;
68 enable-method = "psci";
69 };
70
71 cpu@3 {
72 compatible = "arm,cortex-a53", "arm,armv8";
73 device_type = "cpu";
74 reg = <3>;
75 enable-method = "psci";
76 };
77 };
78
79 psci {
80 compatible = "arm,psci-0.2";
81 method = "smc";
82 };
83
84 timer {
85 compatible = "arm,armv8-timer";
86 interrupts = <GIC_PPI 13
87 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 14
89 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 11
91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10
93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94 };
95};
96
97&ccu {
98 compatible = "allwinner,sun50i-h5-ccu";
99};
100
101&mmc0 {
102 compatible = "allwinner,sun50i-h5-mmc",
103 "allwinner,sun50i-a64-mmc";
104 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
105 clock-names = "ahb", "mmc";
106};
107
108&mmc1 {
109 compatible = "allwinner,sun50i-h5-mmc",
110 "allwinner,sun50i-a64-mmc";
111 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
112 clock-names = "ahb", "mmc";
113};
114
115&mmc2 {
116 compatible = "allwinner,sun50i-h5-emmc",
117 "allwinner,sun50i-a64-emmc";
118 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
119 clock-names = "ahb", "mmc";
120};
121
122&pio {
123 compatible = "allwinner,sun50i-h5-pinctrl";
124};
diff --git a/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi
new file mode 120000
index 000000000000..036f01dc2b9b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi
@@ -0,0 +1 @@
../../../../arm/boot/dts/sunxi-h3-h5.dtsi \ No newline at end of file