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authorShawn Guo2016-09-22 06:48:39 -0500
committerShawn Guo2017-03-24 03:25:12 -0500
commit25bd9d5e2822a504481089933bbb8ba98c96199f (patch)
treedeb47a0cbfeb0de2b6097b60995ca330d9f6e876
parent25798d52b87d7c7d775dc7985817592f0ef3dffd (diff)
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arm64: dts: zte: add vou and hdmi devices for zx296718
It adds VOU DPC device and enables HDMI support, which includes both display and audio through SPDIF interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm64/boot/dts/zte/zx296718-evb.dts20
-rw-r--r--arch/arm64/boot/dts/zte/zx296718.dtsi46
2 files changed, 66 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts
index 238311b4cf0f..bb900d2bbcfb 100644
--- a/arch/arm64/boot/dts/zte/zx296718-evb.dts
+++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts
@@ -57,16 +57,36 @@
57 reg = <0x40000000 0x40000000>; 57 reg = <0x40000000 0x40000000>;
58 }; 58 };
59 59
60 sound0 {
61 compatible = "simple-audio-card";
62 simple-audio-card,name = "zx_snd_spdif0";
63
64 simple-audio-card,cpu {
65 sound-dai = <&spdif0>;
66 };
67
68 simple-audio-card,codec {
69 sound-dai = <&hdmi>;
70 };
71 };
60}; 72};
61 73
62&emmc { 74&emmc {
63 status = "okay"; 75 status = "okay";
64}; 76};
65 77
78&hdmi {
79 status = "okay";
80};
81
66&sd1 { 82&sd1 {
67 status = "okay"; 83 status = "okay";
68}; 84};
69 85
86&spdif0 {
87 status = "okay";
88};
89
70&uart0 { 90&uart0 {
71 status = "okay"; 91 status = "okay";
72}; 92};
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index 30d007b6ab6c..fc1fdf10df76 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -366,6 +366,40 @@
366 #clock-cells = <1>; 366 #clock-cells = <1>;
367 }; 367 };
368 368
369 vou: vou@1440000 {
370 compatible = "zte,zx296718-vou";
371 #address-cells = <1>;
372 #size-cells = <1>;
373 ranges = <0 0x1440000 0x10000>;
374
375 dpc: dpc@0 {
376 compatible = "zte,zx296718-dpc";
377 reg = <0x0000 0x1000>, <0x1000 0x1000>,
378 <0x5000 0x1000>, <0x6000 0x1000>,
379 <0xa000 0x1000>;
380 reg-names = "osd", "timing_ctrl",
381 "dtrc", "vou_ctrl",
382 "otfppu";
383 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
385 <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
386 clock-names = "aclk", "ppu_wclk",
387 "main_wclk", "aux_wclk";
388 };
389
390 hdmi: hdmi@c000 {
391 compatible = "zte,zx296718-hdmi";
392 reg = <0xc000 0x4000>;
393 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
394 clocks = <&topcrm HDMI_OSC_CEC>,
395 <&topcrm HDMI_OSC_CLK>,
396 <&topcrm HDMI_XCLK>;
397 clock-names = "osc_cec", "osc_clk", "xclk";
398 #sound-dai-cells = <0>;
399 status = "disabled";
400 };
401 };
402
369 topcrm: clock-controller@1461000 { 403 topcrm: clock-controller@1461000 {
370 compatible = "zte,zx296718-topcrm"; 404 compatible = "zte,zx296718-topcrm";
371 reg = <0x01461000 0x1000>; 405 reg = <0x01461000 0x1000>;
@@ -403,5 +437,17 @@
403 reg = <0x01480000 0x1000>; 437 reg = <0x01480000 0x1000>;
404 #clock-cells = <1>; 438 #clock-cells = <1>;
405 }; 439 };
440
441 spdif0: spdif@1488000 {
442 compatible = "zte,zx296702-spdif";
443 reg = <0x1488000 0x1000>;
444 clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
445 clock-names = "tx";
446 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
447 #sound-dai-cells = <0>;
448 dmas = <&dma 30>;
449 dma-names = "tx";
450 status = "disabled";
451 };
406 }; 452 };
407}; 453};