aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOrson Zhai2017-04-20 22:47:20 -0500
committerArnd Bergmann2017-04-27 14:56:14 -0500
commit3c0e3abd5ee59acbcbd5d8fc624eaf63f6e7b53c (patch)
treeeecdd51fc2c77e1495b844c0e717cf589fe613e2
parent052bc8fc8f6de1d015ed7714a77ad65c9d9b2e4f (diff)
downloadkernel-3c0e3abd5ee59acbcbd5d8fc624eaf63f6e7b53c.tar.gz
kernel-3c0e3abd5ee59acbcbd5d8fc624eaf63f6e7b53c.tar.xz
kernel-3c0e3abd5ee59acbcbd5d8fc624eaf63f6e7b53c.zip
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum. According to regular hierarchy of sprd dts, whale2.dtsi contains SoC peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff and sp9860g dts is for the board level. Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm64/boot/dts/sprd/Makefile3
-rw-r--r--arch/arm64/boot/dts/sprd/sc9860.dtsi569
-rw-r--r--arch/arm64/boot/dts/sprd/sp9860g-1h10.dts56
-rw-r--r--arch/arm64/boot/dts/sprd/whale2.dtsi71
4 files changed, 698 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile
index b658c5e09b15..f0535e6eaaaa 100644
--- a/arch/arm64/boot/dts/sprd/Makefile
+++ b/arch/arm64/boot/dts/sprd/Makefile
@@ -1,4 +1,5 @@
1dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb 1dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
2 sp9860g-1h10.dtb
2 3
3always := $(dtb-y) 4always := $(dtb-y)
4subdir-y := $(dts-dirs) 5subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
new file mode 100644
index 000000000000..7b7d8cedacda
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
@@ -0,0 +1,569 @@
1/*
2 * Spreadtrum SC9860 SoC
3 *
4 * Copyright (C) 2016, Spreadtrum Communications Inc.
5 *
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include "whale2.dtsi"
11
12/ {
13 cpus {
14 #address-cells = <2>;
15 #size-cells = <0>;
16
17 cpu-map {
18 cluster0 {
19 core0 {
20 cpu = <&CPU0>;
21 };
22 core1 {
23 cpu = <&CPU1>;
24 };
25 core2 {
26 cpu = <&CPU2>;
27 };
28 core3 {
29 cpu = <&CPU3>;
30 };
31 };
32
33 cluster1 {
34 core0 {
35 cpu = <&CPU4>;
36 };
37 core1 {
38 cpu = <&CPU5>;
39 };
40 core2 {
41 cpu = <&CPU6>;
42 };
43 core3 {
44 cpu = <&CPU7>;
45 };
46 };
47 };
48
49 CPU0: cpu@530000 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a53", "arm,armv8";
52 reg = <0x0 0x530000>;
53 enable-method = "psci";
54 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
55 };
56
57 CPU1: cpu@530001 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a53", "arm,armv8";
60 reg = <0x0 0x530001>;
61 enable-method = "psci";
62 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
63 };
64
65 CPU2: cpu@530002 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53", "arm,armv8";
68 reg = <0x0 0x530002>;
69 enable-method = "psci";
70 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
71 };
72
73 CPU3: cpu@530003 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a53", "arm,armv8";
76 reg = <0x0 0x530003>;
77 enable-method = "psci";
78 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
79 };
80
81 CPU4: cpu@530100 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x0 0x530100>;
85 enable-method = "psci";
86 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
87 };
88
89 CPU5: cpu@530101 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a53", "arm,armv8";
92 reg = <0x0 0x530101>;
93 enable-method = "psci";
94 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
95 };
96
97 CPU6: cpu@530102 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a53", "arm,armv8";
100 reg = <0x0 0x530102>;
101 enable-method = "psci";
102 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
103 };
104
105 CPU7: cpu@530103 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a53", "arm,armv8";
108 reg = <0x0 0x530103>;
109 enable-method = "psci";
110 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
111 };
112 };
113
114 idle-states{
115 entry-method = "arm,psci";
116
117 CORE_PD: core_pd {
118 compatible = "arm,idle-state";
119 entry-latency-us = <1000>;
120 exit-latency-us = <700>;
121 min-residency-us = <2500>;
122 local-timer-stop;
123 arm,psci-suspend-param = <0x00010002>;
124 };
125
126 CLUSTER_PD: cluster_pd {
127 compatible = "arm,idle-state";
128 entry-latency-us = <1000>;
129 exit-latency-us = <1000>;
130 min-residency-us = <3000>;
131 local-timer-stop;
132 arm,psci-suspend-param = <0x01010003>;
133 };
134 };
135
136 gic: interrupt-controller@12001000 {
137 compatible = "arm,gic-400";
138 reg = <0 0x12001000 0 0x1000>,
139 <0 0x12002000 0 0x2000>,
140 <0 0x12004000 0 0x2000>,
141 <0 0x12006000 0 0x2000>;
142 #interrupt-cells = <3>;
143 interrupt-controller;
144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
145 | IRQ_TYPE_LEVEL_HIGH)>;
146 };
147
148 psci {
149 compatible = "arm,psci-0.2";
150 method = "smc";
151 };
152
153 timer {
154 compatible = "arm,armv8-timer";
155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
156 | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
158 | IRQ_TYPE_LEVEL_LOW)>,
159 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
160 | IRQ_TYPE_LEVEL_LOW)>,
161 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
162 | IRQ_TYPE_LEVEL_LOW)>;
163 };
164
165 pmu {
166 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
167 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
175 interrupt-affinity = <&CPU0>,
176 <&CPU1>,
177 <&CPU2>,
178 <&CPU3>,
179 <&CPU4>,
180 <&CPU5>,
181 <&CPU6>,
182 <&CPU7>;
183 };
184
185 soc {
186 funnel@10001000 { /* SoC Funnel */
187 compatible = "arm,coresight-funnel", "arm,primecell";
188 reg = <0 0x10001000 0 0x1000>;
189 clocks = <&ext_26m>;
190 clock-names = "apb_pclk";
191 ports {
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 port@0 {
196 reg = <0>;
197 soc_funnel_out_port: endpoint {
198 remote-endpoint = <&etb_in>;
199 };
200 };
201
202 port@1 {
203 reg = <0>;
204 soc_funnel_in_port0: endpoint {
205 slave-mode;
206 remote-endpoint =
207 <&main_funnel_out_port>;
208 };
209 };
210
211 port@2 {
212 reg = <4>;
213 soc_funnel_in_port1: endpoint {
214 slave-mode;
215 remote-endpioint =
216 <&stm_out_port>;
217 };
218 };
219 };
220 };
221
222 etb@10003000 {
223 compatible = "arm,coresight-tmc", "arm,primecell";
224 reg = <0 0x10003000 0 0x1000>;
225 clocks = <&ext_26m>;
226 clock-names = "apb_pclk";
227 port {
228 etb_in: endpoint {
229 slave-mode;
230 remote-endpoint =
231 <&soc_funnel_out_port>;
232 };
233 };
234 };
235
236 stm@10006000 {
237 compatible = "arm,coresight-stm", "arm,primecell";
238 reg = <0 0x10006000 0 0x1000>,
239 <0 0x01000000 0 0x180000>;
240 reg-names = "stm-base", "stm-stimulus-base";
241 clocks = <&ext_26m>;
242 clock-names = "apb_pclk";
243 port {
244 stm_out_port: endpoint {
245 remote-endpoint =
246 <&soc_funnel_in_port1>;
247 };
248 };
249 };
250
251 funnel@11001000 { /* Cluster0 Funnel */
252 compatible = "arm,coresight-funnel", "arm,primecell";
253 reg = <0 0x11001000 0 0x1000>;
254 clocks = <&ext_26m>;
255 clock-names = "apb_pclk";
256 ports {
257 #address-cells = <1>;
258 #size-cells = <0>;
259
260 port@0 {
261 reg = <0>;
262 cluster0_funnel_out_port: endpoint {
263 remote-endpoint =
264 <&cluster0_etf_in>;
265 };
266 };
267
268 port@1 {
269 reg = <0>;
270 cluster0_funnel_in_port0: endpoint {
271 slave-mode;
272 remote-endpoint = <&etm0_out>;
273 };
274 };
275
276 port@2 {
277 reg = <1>;
278 cluster0_funnel_in_port1: endpoint {
279 slave-mode;
280 remote-endpoint = <&etm1_out>;
281 };
282 };
283
284 port@3 {
285 reg = <2>;
286 cluster0_funnel_in_port2: endpoint {
287 slave-mode;
288 remote-endpoint = <&etm2_out>;
289 };
290 };
291
292 port@4 {
293 reg = <4>;
294 cluster0_funnel_in_port3: endpoint {
295 slave-mode;
296 remote-endpoint = <&etm3_out>;
297 };
298 };
299 };
300 };
301
302 funnel@11002000 { /* Cluster1 Funnel */
303 compatible = "arm,coresight-funnel", "arm,primecell";
304 reg = <0 0x11002000 0 0x1000>;
305 clocks = <&ext_26m>;
306 clock-names = "apb_pclk";
307 ports {
308 #address-cells = <1>;
309 #size-cells = <0>;
310
311 port@0 {
312 reg = <0>;
313 cluster1_funnel_out_port: endpoint {
314 remote-endpoint =
315 <&cluster1_etf_in>;
316 };
317 };
318
319 port@1 {
320 reg = <0>;
321 cluster1_funnel_in_port0: endpoint {
322 slave-mode;
323 remote-endpoint = <&etm4_out>;
324 };
325 };
326
327 port@2 {
328 reg = <1>;
329 cluster1_funnel_in_port1: endpoint {
330 slave-mode;
331 remote-endpoint = <&etm5_out>;
332 };
333 };
334
335 port@3 {
336 reg = <2>;
337 cluster1_funnel_in_port2: endpoint {
338 slave-mode;
339 remote-endpoint = <&etm6_out>;
340 };
341 };
342
343 port@4 {
344 reg = <3>;
345 cluster1_funnel_in_port3: endpoint {
346 slave-mode;
347 remote-endpoint = <&etm7_out>;
348 };
349 };
350 };
351 };
352
353 etf@11003000 { /* ETF on Cluster0 */
354 compatible = "arm,coresight-tmc", "arm,primecell";
355 reg = <0 0x11003000 0 0x1000>;
356 clocks = <&ext_26m>;
357 clock-names = "apb_pclk";
358
359 ports {
360 #address-cells = <1>;
361 #size-cells = <0>;
362
363 port@0 {
364 reg = <0>;
365 cluster0_etf_out: endpoint {
366 remote-endpoint =
367 <&main_funnel_in_port0>;
368 };
369 };
370
371 port@1 {
372 reg = <0>;
373 cluster0_etf_in: endpoint {
374 slave-mode;
375 remote-endpoint =
376 <&cluster0_funnel_out_port>;
377 };
378 };
379 };
380 };
381
382 etf@11004000 { /* ETF on Cluster1 */
383 compatible = "arm,coresight-tmc", "arm,primecell";
384 reg = <0 0x11004000 0 0x1000>;
385 clocks = <&ext_26m>;
386 clock-names = "apb_pclk";
387
388 ports {
389 #address-cells = <1>;
390 #size-cells = <0>;
391
392 port@0 {
393 reg = <0>;
394 cluster1_etf_out: endpoint {
395 remote-endpoint =
396 <&main_funnel_in_port1>;
397 };
398 };
399
400 port@1 {
401 reg = <0>;
402 cluster1_etf_in: endpoint {
403 slave-mode;
404 remote-endpoint =
405 <&cluster1_funnel_out_port>;
406 };
407 };
408 };
409 };
410
411 funnel@11005000 { /* Main Funnel */
412 compatible = "arm,coresight-funnel", "arm,primecell";
413 reg = <0 0x11005000 0 0x1000>;
414 clocks = <&ext_26m>;
415 clock-names = "apb_pclk";
416
417 ports {
418 #address-cells = <1>;
419 #size-cells = <0>;
420
421 port@0 {
422 reg = <0>;
423 main_funnel_out_port: endpoint {
424 remote-endpoint =
425 <&soc_funnel_in_port0>;
426 };
427 };
428
429 port@1 {
430 reg = <0>;
431 main_funnel_in_port0: endpoint {
432 slave-mode;
433 remote-endpoint =
434 <&cluster0_etf_out>;
435 };
436 };
437
438 port@2 {
439 reg = <1>;
440 main_funnel_in_port1: endpoint {
441 slave-mode;
442 remote-endpoint =
443 <&cluster1_etf_out>;
444 };
445 };
446 };
447 };
448
449 etm@11440000 {
450 compatible = "arm,coresight-etm4x", "arm,primecell";
451 reg = <0 0x11440000 0 0x1000>;
452 cpu = <&CPU0>;
453 clocks = <&ext_26m>;
454 clock-names = "apb_pclk";
455
456 port {
457 etm0_out: endpoint {
458 remote-endpoint =
459 <&cluster0_funnel_in_port0>;
460 };
461 };
462 };
463
464 etm@11540000 {
465 compatible = "arm,coresight-etm4x", "arm,primecell";
466 reg = <0 0x11540000 0 0x1000>;
467 cpu = <&CPU1>;
468 clocks = <&ext_26m>;
469 clock-names = "apb_pclk";
470
471 port {
472 etm1_out: endpoint {
473 remote-endpoint =
474 <&cluster0_funnel_in_port1>;
475 };
476 };
477 };
478
479 etm@11640000 {
480 compatible = "arm,coresight-etm4x", "arm,primecell";
481 reg = <0 0x11640000 0 0x1000>;
482 cpu = <&CPU2>;
483 clocks = <&ext_26m>;
484 clock-names = "apb_pclk";
485
486 port {
487 etm2_out: endpoint {
488 remote-endpoint =
489 <&cluster0_funnel_in_port2>;
490 };
491 };
492 };
493
494 etm@11740000 {
495 compatible = "arm,coresight-etm4x", "arm,primecell";
496 reg = <0 0x11740000 0 0x1000>;
497 cpu = <&CPU3>;
498 clocks = <&ext_26m>;
499 clock-names = "apb_pclk";
500
501 port {
502 etm3_out: endpoint {
503 remote-endpoint =
504 <&cluster0_funnel_in_port3>;
505 };
506 };
507 };
508
509 etm@11840000 {
510 compatible = "arm,coresight-etm4x", "arm,primecell";
511 reg = <0 0x11840000 0 0x1000>;
512 cpu = <&CPU4>;
513 clocks = <&ext_26m>;
514 clock-names = "apb_pclk";
515
516 port {
517 etm4_out: endpoint {
518 remote-endpoint =
519 <&cluster1_funnel_in_port0>;
520 };
521 };
522 };
523
524 etm@11940000 {
525 compatible = "arm,coresight-etm4x", "arm,primecell";
526 reg = <0 0x11940000 0 0x1000>;
527 cpu = <&CPU5>;
528 clocks = <&ext_26m>;
529 clock-names = "apb_pclk";
530
531 port {
532 etm5_out: endpoint {
533 remote-endpoint =
534 <&cluster1_funnel_in_port1>;
535 };
536 };
537 };
538
539 etm@11a40000 {
540 compatible = "arm,coresight-etm4x", "arm,primecell";
541 reg = <0 0x11a40000 0 0x1000>;
542 cpu = <&CPU6>;
543 clocks = <&ext_26m>;
544 clock-names = "apb_pclk";
545
546 port {
547 etm6_out: endpoint {
548 remote-endpoint =
549 <&cluster1_funnel_in_port2>;
550 };
551 };
552 };
553
554 etm@11b40000 {
555 compatible = "arm,coresight-etm4x", "arm,primecell";
556 reg = <0 0x11b40000 0 0x1000>;
557 cpu = <&CPU7>;
558 clocks = <&ext_26m>;
559 clock-names = "apb_pclk";
560
561 port {
562 etm7_out: endpoint {
563 remote-endpoint =
564 <&cluster1_funnel_in_port3>;
565 };
566 };
567 };
568 };
569};
diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
new file mode 100644
index 000000000000..ae0b28ce6319
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
@@ -0,0 +1,56 @@
1/*
2 * Spreadtrum SP9860g board
3 *
4 * Copyright (C) 2017, Spreadtrum Communications Inc.
5 *
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */
8
9/dts-v1/;
10
11#include "sc9860.dtsi"
12
13/ {
14 model = "Spreadtrum SP9860G 3GFHD Board";
15
16 compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
17
18 aliases {
19 serial0 = &uart0; /* for Bluetooth */
20 serial1 = &uart1; /* UART console */
21 serial2 = &uart2; /* Reserved */
22 serial3 = &uart3; /* for GPS */
23 };
24
25 memory{
26 device_type = "memory";
27 reg = <0x0 0x80000000 0 0x60000000>,
28 <0x1 0x80000000 0 0x60000000>;
29 };
30
31 chosen {
32 stdout-path = "serial1:115200n8";
33 };
34
35 reserved-memory {
36 #address-cells = <2>;
37 #size-cells = <2>;
38 ranges;
39 };
40};
41
42&uart0 {
43 status = "okay";
44};
45
46&uart1 {
47 status = "okay";
48};
49
50&uart2 {
51 status = "okay";
52};
53
54&uart3 {
55 status = "okay";
56};
diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
new file mode 100644
index 000000000000..7c217c547f85
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
@@ -0,0 +1,71 @@
1/*
2 * Spreadtrum Whale2 platform peripherals
3 *
4 * Copyright (C) 2016, Spreadtrum Communications Inc.
5 *
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */
8
9/ {
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 soc: soc {
15 compatible = "simple-bus";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 ranges;
19
20 ap-apb {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges = <0 0x0 0x70000000 0x10000000>;
25
26 uart0: serial@0 {
27 compatible = "sprd,sc9860-uart",
28 "sprd,sc9836-uart";
29 reg = <0x0 0x100>;
30 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&ext_26m>;
32 status = "disabled";
33 };
34
35 uart1: serial@100000 {
36 compatible = "sprd,sc9860-uart",
37 "sprd,sc9836-uart";
38 reg = <0x100000 0x100>;
39 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
40 clocks = <&ext_26m>;
41 status = "disabled";
42 };
43
44 uart2: serial@200000 {
45 compatible = "sprd,sc9860-uart",
46 "sprd,sc9836-uart";
47 reg = <0x200000 0x100>;
48 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&ext_26m>;
50 status = "disabled";
51 };
52
53 uart3: serial@300000 {
54 compatible = "sprd,sc9860-uart",
55 "sprd,sc9836-uart";
56 reg = <0x300000 0x100>;
57 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&ext_26m>;
59 status = "disabled";
60 };
61 };
62
63 };
64
65 ext_26m: ext-26m {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <26000000>;
69 clock-output-names = "ext_26m";
70 };
71};
generated by cgit v1.2.3 (git 2.25.1)