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authorShawn Guo2017-03-21 03:42:45 -0500
committerShawn Guo2017-03-24 03:16:50 -0500
commit6d7e05ab8ff6f6bb91ecfbbd542240c7b6c23502 (patch)
treedbe88d8abdc7473b3e3b99cfde2389c6a8ee67ae
parentc1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 (diff)
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arm64: dts: zte: remove zx296718 pll_vga clock
Rather than a fixed rate clock, pll_vga is a PLL can be programmed into different freqencies. Let's drop it from device tree and get it registered from clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm64/boot/dts/zte/zx296718.dtsi7
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index b850b2cd0adc..1f256495b902 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -235,13 +235,6 @@
235 clock-output-names = "pll_mac"; 235 clock-output-names = "pll_mac";
236 }; 236 };
237 237
238 pll_vga: clk-pll-1073m {
239 compatible = "fixed-clock";
240 #clock-cells = <0>;
241 clock-frequency = <1073000000>;
242 clock-output-names = "pll_vga";
243 };
244
245 pll_mm0: clk-pll-1188m { 238 pll_mm0: clk-pll-1188m {
246 compatible = "fixed-clock"; 239 compatible = "fixed-clock";
247 #clock-cells = <0>; 240 #clock-cells = <0>;